High Voltage Charge Pump, PLL Synthesizer ADF4113HV Data Sheet FEATURES GENERAL DESCRIPTION High voltage charge pump (15 V) 2.7 V to 5.5 V power supply 200 MHz to 4.0 GHz frequency range Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113 ADF4106, and ADF4002 synthesizers Two selectable charge pump currents Digital lock detect Power-down mode Loop filter design possible with ADIsimPLL™ The ADF4113HV is an integer-N frequency synthesizer with a high voltage charge pump (15 V). The synthesizer is designed for use with voltage controlled oscillators (VCOs) that have high tuning voltages (up to 15 V). Active loop filters are often used to achieve high tuning voltages, but the ADF4113HV charge pump can drive a high voltage VCO directly with a passive-loop filter. The ADF4113HV can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision high voltage charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). APPLICATIONS Applications using high voltage VCOs IF/RF local oscillator (LO) generation in base stations Point-to-point radio LO generation Clock for analog-to-digital and digital-to-analog converters Wireless LANs, PMR Communications test equipment A simple 3-wire interface controls all of the on-chip registers. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD VP DVDD RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP LOCK DETECT CURRENT SETTING CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER FUNCTION LATCH 22 A, B COUNTER LATCH SDOUT FROM FUNCTION LATCH RFINB AVDD 13 N = BP + A RFINA HIGH Z 19 MUX MUXOUT SDOUT 13-BIT B COUNTER LOAD PRESCALER P/P + 1 M3 M2 M1 LOAD 6-BIT A COUNTER ADF4113HV CE AGND 06223-001 6 DGND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADF4113HV Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Prescaler (P/P + 1) ........................................................................9 Applications ....................................................................................... 1 A and B Counters ..........................................................................9 Functional Block Diagram .............................................................. 1 R Counter .......................................................................................9 Revision History ............................................................................... 2 Phase Frequency Detector (PFD) and Charge Pump............ 10 Specifications..................................................................................... 3 Muxout and Lock Detect ........................................................... 10 Timing Characteristics ................................................................ 4 Input Shift Register .................................................................... 10 Absolute Maximum Ratings ............................................................ 5 Function Latch ............................................................................ 13 Transistor Count ........................................................................... 5 Applications..................................................................................... 15 Thermal Resistance ...................................................................... 5 Using a Digitial-to-Analog Converter to Drive the RSET Pin .................................................................................. 15 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description ........................................................................... 9 Reference Input Section ............................................................... 9 Interfacing ................................................................................... 15 PCB Design Guidelines for Chip Scale Package .................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 RF Input Stage ............................................................................... 9 REVISION HISTORY 10/12—Rev. A to Rev. B Changed CP-20-1 Package to CP-20-6 Package ............. Universal Changes to Table 3 and Table 4 ....................................................... 5 Added EPAD Notation..................................................................... 6 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 9/08—Rev. 0 to Rev. A Changes to Figure 22 ...................................................................... 13 1/07—Revision 0: Initial Version Rev. B | Page 2 of 20 Data Sheet ADF4113HV SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C. Table 1. Parameter RF CHARACTERISTICS (3 V) RF Input Sensitivity RF Input Frequency Prescaler Output Frequency 2 RF CHARACTERISTICS (5 V) RF Input Sensitivity RF Input Frequency Prescaler Output Frequency REFIN CHARACTERISTICS REFIN Input Frequency Reference Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR FREQUENCY CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 5 (AIDD + DIDD) IP Low Power Sleep Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor 6 B Version B Chips 1 Unit Test Conditions/Comments −15/0 0.2/3.7 165 −15/0 0.2/3.7 165 dBm min/max GHz min/max MHz max For lower frequencies, ensure SR > 130 V/μs −10/0 0.2/3.7 0.2/4.0 200 −10/0 0.2/3.7 0.2/4.0 200 dBm min/max GHz min/max GHz min/max MHz max For lower frequencies, ensure SR > 130 V/µs Input level = −5 dBm 5/150 0.4/AVDD 1.0/AVDD 10 ±100 5 5/150 0.4/AVDD 1.0/AVDD 10 ±100 5 MHz min/max V p-p min/max V p-p min/max pF max µA max MHz max 640 80 2.5 3.9/10 5 3 1.5 2 640 80 2.5 3.9/10 5 3 1.5 2 μA typ µA typ % typ kΩ typ nA max % typ % typ % typ 0.8 × DVDD 0.2 × DVDD ±1 10 0.8 × DVDD 0.2 × DVDD ±1 10 V min V max µA max pF max DVDD − 0.4 0.4 DVDD − 0.4 0.4 V min V max 2.7/5.5 AVDD 13.5/16.5 16 0.25 1 2.7/5.5 AVDD 13.5/16.5 11 0.25 1 V min/V max V min/V max mA max mA max µA typ −212 −212 dBc/Hz typ For f < 5 MHz, ensure SR > 100 V/µs AVDD = 3.3 V, biased at AVDD/2 3 For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/23, 4 RSET = 4.7 kΩ 1 1 V ≤ VCP ≤ VP – 1 V 1 V ≤ VCP ≤ VP – 1 V VCP = VP/2 IOH = 500 µA IOL = 500 µA 11 mA typical TA = 25°C The B chip specifications are given as typical values. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by characterization. 5 TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logfPFD: PNSYNTH = PNTOT − 10logfPFD − 20logN. 2 Rev. B | Page 3 of 20 ADF4113HV Data Sheet TIMING CHARACTERISTICS Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V ≤ VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Timing Diagram t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 06223-002 t6 LE Figure 2. Timing Diagram Rev. B | Page 4 of 20 Data Sheet ADF4113HV ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. TRANSISTOR COUNT Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow, Soldering Peak Temperature Time at Peak Temperature 1 The transistor count is 12,150 (CMOS) and 348 (bipolar). Rating −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +18 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V ±320 mV THERMAL RESISTANCE Table 4. Thermal Resistance Package Type TSSOP LFCSP (Paddle Soldered)1 1 Unit °C/W °C/W Two signal planes (that is, on top and bottom surfaces), two buried planes, and four thermal vias. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C θJA 150.4 62.82 260°C 40 sec GND = AGND = DGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <1 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. Rev. B | Page 5 of 20 ADF4113HV Data Sheet 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DVDD MUXOUT 13 LE RFINB 5 12 DATA RFINA 6 11 CLK AVDD 7 10 CE REFIN 8 9 ADF4113HV AGND 4 TOP VIEW (Not to Scale) DGND 1 2 3 4 5 ADF4113HV TOP VIEW (Not to Scale) 15 14 13 12 11 MUXOUT LE DATA CLK CE NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. Figure 3. TSSOP Pin Configuration 06223-004 15 14 CP 2 CPGND 3 CPGND AGND AGND RFINB RFINA VP AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 16 06223-003 RSET 1 Figure 4. LFCSP Pin Configuration Table 5. Pin Function Descriptions TSSOP Pin No. 1 LFCSP Pin No. 19 Mnemonic RSET 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND CE 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP N/A 21 EPAD Description Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.56 V for the ADF4113HV. The relationship between ICP and RSET is ICPmax = 3/RSET. Therefore, with RSET = 4.7 kΩ, ICPmax = 640 μA. Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter; in turn, this drives the external VCO. Charge Pump Ground. CPGND is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO. Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. This pin is a CMOS input with a nominal threshold of VDD/2, and an equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled. Digital Ground. Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device depending on the status of the Power-Down Bit PD1. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be externally accessed. Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1μF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical but should still be within 5 mm of the pin. DVDD must have the same value as AVDD. Charge Pump Power Supply. VP can range from 13.5 V to 16.5 V and should be decoupled appropriately. Exposed Pad. The exposed pad must be connected to AGND. Rev. B | Page 6 of 20 Data Sheet ADF4113HV TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 25 kHz, reference = 10 MHz reference from Agilent E4440A PSA, VCO = Sirenza VCO190-1500T(Y), evaluation board = EV-ADF4113HVSDZ1. DATA KEYWORD –FORMAT MA R FREQ 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 MAGS11 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954 0.92087 0.93788 ANGS11 –2.0571 –4.4427 –6.3212 –2.1393 –12.13 –13.52 –15.746 –18.056 –19.693 –22.246 –24.336 –25.948 –28.457 –29.735 –31.879 –32.681 –31.522 –34.222 –36.961 –39.343 MAGS11 0.9512 0.93458 0.94782 0.96875 0.92216 0.93755 0.96178 0.94354 0.95189 0.97647 0.98619 0.95459 0.97945 0.98864 0.97399 0.97216 –5 ANGS11 –40.134 –43.747 –44.393 –46.937 –49.6 –51.884 –51.21 –53.55 –56.786 –58.781 –60.545 –61.43 –61.241 –64.051 –66.19 –63.775 –15 –25 –35 –45 –55 –65 1MHz –92.428dBc –75 06223-005 FREQ 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 5 IMPEDANCE –OHMS 50 06223-043 PARAM –TYPE S POWER (dB) FREQ –UNIT GHz –85 1.25M 1.00M 0.75M 0.50M 0.25M 1.00G –0.25M –0.50M –0.75M –1.00M –1.25M –95 FREQUENCY (Hz) Figure 5. S-Parameter Data for the ADF4113HV RF Input (Up to 1.8 GHz) Figure 8. Reference Spurs (RF = 1000 MHz, PFD = 1 MHz) 0 –70 –5 –80 –90 PHASE NOISE (dBc/Hz) –15 –20 +85°C –25 +25°C –30 –40°C –35 1kHz –86.33dBc/Hz –100 –110 –120 CARRIER POWER: –0.88dBm –130 –140 –45 4k 5k –170 100 6k 1k RF INPUT FREQUENCY (MHz) –70 0 –80 –10 –90 –20 –50 –60 –70 –150 –80 FREQUENCY (Hz) Figure 10. Reference Spurs (RF = 1800 MHz, PFD = 1 MHz) Figure 7. Integrated Phase Noise (RF = 1000 MHz, PFD = 1 MHz, VTUNE = 1.8 V, RMS Noise = 0.93°) Rev. B | Page 7 of 20 1.25M 1M 1.00M 100k 0.75M 10k FREQUENCY OFFSET (Hz) 0.50M 1k –90 –100 –1.25M –160 1MHz –87.264dBc 06223-041 –140 –0.75M –130 –40 –1.00M POWER (dB) CARRIER POWER: –5.09dBm –170 100 1M –30 1kHz –91.08dBc/Hz –110 –120 100k Figure 9. Integrated Phase Noise (RF = 1800 MHz, PFD= 1 MHz, VTUNE = 13.1 V, RMS Noise = 1.16°) 06223-042 PHASE NOISE (dBc/Hz) Figure 6. Input Sensitivity –100 10k FREQUENCY OFFSET (Hz) 0.25M 3k 1.00G 2k –160 –0.25M 1k 0 06223-040 06223-027 –150 –40 –0.50M RF INPUT POWER (dBm) –10 ADF4113HV Data Sheet 800 VDD = 3V VP = 15V 600 CHARGE PUMP CURRENT (µA) –20 –40 –60 –80 200 0 –200 –400 0 2 4 6 8 10 12 Figure 11. PFD Spurs (1 MHz) vs. VTUNE VDD = 3V VP = 15V –60 –70 06223-045 –80 0 20 40 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 13. Charge Pump Output Characteristics –50 –20 1 VCP (V) TUNING VOLTAGE (V) –90 –40 –800 0 16 14 –600 06223-026 –120 PHASE NOISE (dBc/Hz) 400 –100 06223-044 FIRST REFERENCE SPUR LEVEL (dBc) 0 60 80 100 TEMPERATURE (°C) Figure 12. Phase Noise vs. Temperature (RF = 1500 MHz, PFD = 1 MHz) Rev. B | Page 8 of 20 Data Sheet ADF4113HV CIRCUIT DESCRIPTION REFERENCE INPUT SECTION A AND B COUNTERS The reference input stage is shown in Figure 14. SW1 and SW2 are normally closed switches (NC in Figure 14). SW3 is normally open (NO in Figure 14). When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less (for AVDD = 5 V). Thus, with an RF input frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not. POWER-DOWN CONTROL Pulse Swallow Function NC 100kΩ SW2 REFIN NC The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is TO R COUNTER BUFFER SW1 06223-014 SW3 NO fVCO = [(P × B) + A]fREFIN/R Figure 14. Reference Input Stage where: RF INPUT STAGE The RF input stage is shown in Figure 15. It is followed by a two-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler. fVCO = output frequency of external voltage controlled oscillator (VCO). P = preset modulus of dual-modulus prescaler. B = preset divide ratio of binary 13-bit counter (3 to 8191). BIAS GENERATOR 500Ω 1.6V A = preset divide ratio of binary 6-bit swallow counter (0 to 63). AVDD fREFIN = output frequency of the external reference frequency oscillator. 500Ω RFINA R = preset divide ratio of binary 14-bit programmable reference counter (1 to 16,383). N = BP + A 13-BIT B COUNTER Figure 15. RF Input Stage FROM RF INPUT STAGE PRESCALER (P/P + 1) PRESCALER P/P + 1 MODULUS CONTROL Together with the A and B counters, the dual-modulus prescaler (P/P + 1) enables the large division ratio, N, to be realized by N = BP + A TO PFD LOAD LOAD 6-BIT A COUNTER 06223-016 AGND 06223-015 RFINB Figure 16. A and B Counters The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and CMOS B counters. The prescaler is programmable; it can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. Rev. B | Page 9 of 20 ADF4113HV Data Sheet DVDD The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 17 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse. See Figure 20. The only recommended setting for the antibacklash pulse width is 7.2 ns. VP D1 HIGH Q1 CHARGE PUMP U1 R DIVIDER CLR1 ABP1 CLR2 D2 HIGH Q2 CP U3 MUX MUXOUT CONTROL DGND Figure 18. MUXOUT Circuit Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When LDP in the AB counter latch is set to 0, digital lock detect is set high when the phase error on five consecutive phase detector (PD) cycles is less than 10 ns. With LDP set to 1, five consecutive cycles of less than 3 ns are required to set the lock detect. It stays high until a phase error greater than 25 ns is detected on any subsequent PD cycle. UP PROGRAMMABLE DELAY ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT SDOUT 06223-018 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP Operate the N-channel, open-drain, analog lock detect with a 10 kΩ nominal external pull-up resistor. When lock has been detected, this output is high with narrow low-going pulses. ABP2 DOWN INPUT SHIFT REGISTER U2 N DIVIDER CPGND R DIVIDER CP OUTPUT 06223-017 N DIVIDER Figure 17. PFD Simplified Schematic and Timing (in Lock) The ADF4113HV digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK, MSB first. Data is transferred from the shift register to one of three latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 6. Figure 19 shows a summary of how the latches are programmed. Table 6. C2, C1 Truth Table MUXOUT AND LOCK DETECT The output multiplexer on the ADF4113HV allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 22 shows the full truth table (function latch map). Figure 18 shows the MUXOUT section in block diagram form. Control Bits C2 C1 0 0 0 1 1 0 Rev. B | Page 10 of 20 Data Latch R counter N counter (A and B) Function latch (including prescaler) Data Sheet ADF4113HV Latch Summary REFERENCE COUNTER LATCH ANTIBACKLASH PULSE WIDTH RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 0 0 0 0 0 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R9 R10 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R7 R6 R5 R4 R3 R2 R1 R8 DB1 DB0 C2(0) C1(0) RESERVED LD PREC RESERVED N COUNTER LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 L1 0 B13 B12 B11 B10 B8 B9 B5 B6 B7 CONTROL BITS 6-BIT A COUNTER 13-BIT B COUNTER B4 B3 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B1 A6 A5 A4 A3 A2 A1 C2(0) C1(1) MUXOUT CONTROL CONTROL BITS B2 DB1 DB0 P2 0 0 P1 0 0 CP3 CP2 CP1 0 0 0 0 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 M3 M2 M1 F2 F1 0 0 DB1 DB0 06223-019 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 COUNTER RESET RESERVED POWER DOWN CURRENT SETTING RESERVED PD POLARITY PRESCALER VALUE CP THREESTATE FUNCTION LATCH C2(1) C1(0) Figure 19. Latch Summary Tables Reference Counter Latch Map ANTIBACKLASH PULSE WIDTH RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 0 0 0 0 0 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R10 R9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R7 R6 R5 R4 R3 R2 R1 R8 DB1 DB0 C2(0) C1(0) THESE BITS MUST BE SET AS INDICATED FOR NORMAL OPERATION ABP1 1 0 ANTI-BACKLASH PULSE WIDTH 7.2ns (ONLY ALLOWED SETTING) R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 0 0 0 0 0 0 0 .......... .......... .......... 0 0 0 0 1 1 1 0 1 1 2 0 .......... 1 0 0 3 4 . . . . . . . .......... .......... . . . . . . . . 1 . 1 . 1 .......... .......... . 1 . 0 . 0 1 1 1 1 1 1 .......... .......... 1 1 1 1 1 .......... 1 Figure 20. Reference Counter Latch Bit Map Rev. B | Page 11 of 20 0 1 1 1 0 1 . 16380 16381 16382 16383 06223-020 ABP2 ADF4113HV Data Sheet 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 1 0 B13 B12 B11 B10 L2 LOCK DETECT PRECISION 0 10ns 1 3ns B13 B12 B11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 B9 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... B8 B7 B6 CONTROL BITS 6-BIT A COUNTER B5 B4 B3 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B1 A6 A5 A4 A3 A2 A1 B2 A6 A5 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 0 1 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 8188 8189 8190 8191 Figure 21. B Counter Latch Map Rev. B | Page 12 of 20 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... DB1 DB0 C2(0) C1(1) A2 A1 A COUNTER DIVIDE RATIO 0 0 0 1 . . . 0 1 1 0 1 0 1 . . . 1 0 1 0 1 2 3 . . . 61 62 63 06223-021 RESERVED LD PREC RESERVED AB Counter Latch Map Data Sheet ADF4113HV P2 P1 0 0 0 0 CP3 CP2 CP1 0 0 0 ICP (µA) 0 0 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 M3 M2 M1 F2 F1 0 COUNTER OPERATION 0 NORMAL 1 R, A, B COUNTERS HELD IN RESET CPI1 4.7kΩ 0 NORMAL 0 1 0 1 80 640 1 THREE-STATE 0 0 8/9 0 1 16/17 1 1 0 1 32/33 64/65 DB0 F1 CPI2 PRESCALER VALUE DB1 C2(1) C1(0) CHARGE PUMP OUTPUT 0 1 P1 CONTROL BITS F4 CPI3 P2 MUXOUT CONTROL F3 PHASE DETECTOR POLARITY PD1 OPERATION 1 0 POSITIVE NEGATIVE 0 1 NORMAL POWER DOWN M3 M2 M1 OUTPUT 0 0 0 0 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT ANALOG LOCK DETECT SERIAL DATA OUTPUT 1 1 1 DGND 06223-022 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 COUNTER RESET RESERVED POWER DOWN CURRENT SETTING RESERVED PD POLARITY PRESCALER VALUE CP THREESTATE Function Latch Map Figure 22. Function Latch Map FUNCTION LATCH The on-chip function latch is programmed with C2 and C1 set to 1,0, respectively. Figure 22 shows the input data format for programming the function latch. Counter Reset • The RFINA and RFINB inputs are debiased. • The reference input buffer circuitry is disabled. • The input register remains active and capable of loading and latching data. DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit must be disabled, and the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.) The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4113HV. Figure 22 shows the truth table. Power-Down CPI3, CPI2, and CPI1 program the current setting for the charge pump. The truth table is given in Figure 22. DB3 (F2) in the function latch provides a software power-down for the ADF4113HV. The device powers down immediately after latching a 1 into Bit F2. When the CE pin is low, the device immediately powers down regardless of the state of the power-down bit (F2). When a power-down is activated (either through software or a CE pin activated power-down), the following events occur: • All active dc current paths are removed. • The R, N, and timeout counters are forced to their load state conditions. • The charge pump is forced into three-state mode. • The digital clock detect circuitry is reset. MUXOUT Control Charge Pump Currents Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 200 MHz. Thus, with an RF frequency of 2 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not. PD Polarity This bit sets the phase detector polarity bit. See Figure 22. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. Rev. B | Page 13 of 20 ADF4113HV Data Sheet DEVICE PROGRAMMING AFTER INITIAL POWER-UP grammed each time the device is disabled and enabled as long as it has been programmed at least once after VDD was initially applied. After initial power-up of the device, there are two ways to program the device. Counter Reset Method 1. Apply VDD. CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. 3. Program the function latch (10). Program the R counter latch (00). Program the AB counter latch (01). 4. Bring CE high to take the device out of power-down. The R and AB counters resume counting in close alignment. After CE goes high, a duration of 1 µs is sometimes required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. 2. Conduct a function latch load (10 in 2 LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Conduct an R counter load (00 in 2 LSBs). 4. Conduct an AB counter load (01 in 2 LSBs). 5. Conduct a function latch load (10 in 2 LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. CE can be used to power the device up and down to check for channel activity. The input register does not need to be repro- Rev. B | Page 14 of 20 Data Sheet ADF4113HV APPLICATIONS RFOUT 100pF 8 REFIN FREFIN VCO LOOP FILTER CP 2 INPUT OUTPUT MUXOUT 14 1 RSET 18Ω 18Ω 18Ω GND ADF4113HV CE CLK DATA LE 100pF LOCK DETECT 100pF RFINA 6 2.7kΩ 51Ω RFINB 5 100pF AD5320 12-BIT V-OUT DAC 06223-023 SPI-COMPATIBLE SERIAL BUS NOTES 1. POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS ARE OMITTED FOR CLARITY. Figure 23. Driving the RSET Pin with a Digital-to-Analog Converter A digital-to-analog converter (DAC) can be used to drive the RSET pin of the ADF4113HV, thus increasing the level of control over the charge pump current (ICP). This can be advantageous in wideband applications where the sensitivity of the VCO varies over the tuning range. To compensate for this, ICP can be varied to maintain good phase margin and ensure loop stability. See Figure 23 for this configuration. INTERFACING The ADF4113HV has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When latch enable (LE) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 6 for the latch truth table. microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4113HV needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. I/O port lines on the ADuC812 are also used to control powerdown (CE input), and to detect lock (MUXOUT configured as lock detect and polled by the port input). When the ADuC812 is operating in the SPI master mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz, or one update every 1.2 µs. This rate is more than adequate for systems that have typical lock times in the hundreds of microseconds. ADuC812 Interface SCLOCK ADuC812 MOSI CLK DATA LE ADF4113HV I/O PORTS CE MUXOUT (LOCK DETECT) Figure 24. ADuC812 to ADF4113HV Interface Figure 24 shows the interface between the ADF4113HV and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based Rev. B | Page 15 of 20 06223-024 USING A DIGITIAL-TO-ANALOG CONVERTER TO DRIVE THE RSET PIN ADF4113HV Data Sheet ADSP-21xx Interface Figure 25 shows the interface between the ADF4113HV and the ADSP-21xx digital signal processor. The ADF4113HV needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the auto buffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. ADSP-21xx DT TFS I/O FLAGS CLK DATA LE ADF4113HV CE MUXOUT (LOCK DETECT) 06223-025 SCLK Figure 25. ADSP-21xx to ADF4113HV Interface Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the auto buffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-6) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. The land should be centered on the pad to ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. B | Page 16 of 20 Data Sheet ADF4113HV OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 20 16 15 0.50 BSC 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 5 6 10 0.65 0.60 0.55 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.20 MIN BOTTOM VIEW 08-16-2010-B PIN 1 INDICATOR 0.30 0.25 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-20-6) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1 ADF4113HVBRUZ ADF4113HVBRUZ-RL ADF4113HVBRUZ-RL7 ADF4113HVBCPZ ADF4113HVBCPZ-RL ADF4113HVBCPZ-RL7 EV-ADF4113HVSD1Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. The CP-20-6 package was formerly the CP-20-1 package. Rev. B | Page 17 of 20 Package Option2 RU-16 RU-16 RU-16 CP-20-6 CP-20-6 CP-20-6 ADF4113HV Data Sheet NOTES Rev. B | Page 18 of 20 Data Sheet ADF4113HV NOTES Rev. B | Page 19 of 20 ADF4113HV Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06223-0-10/12(B) Rev. B | Page 20 of 20