AD ADUM5240BRZ Dual-channel isolators with integrated dc/dc converter, 50 mw Datasheet

Dual-Channel Isolators with
Integrated DC/DC Converter, 50 mW
ADuM5240/ADuM5241/ADuM5242
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
Integrated isolated DC/DC converter
Regulated 5V/10 mA output
Dual dc-to-10 Mbps (NRZ) signal isolation channels
Narrow body SOIC 8-lead package
High temperature operation: 105°C
Precise timing characteristics:
3 ns maximum pulse-width distortion
3 ns maximum channel-to-channel matching
70 ns maximum propagation delay
High common-mode transient immunity: > 25 kV/μs
Safety and regulatory approvals (pending)
UL recognition
2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000
VIORM = 425 V peak
The ADuM524x1 are dual-channel digital isolators having an
integrated DC/DC converter. Based on Analog Devices’
iCoupler® technology, the DC/DC converter provides up to
50 mW of regulated, isolated power at +5V. This eliminates the
need for a separate isolated DC/DC converter in low-power
isolated designs. Analog Devices’ chip-scale transformer
iCoupler® technology is used both for the isolation of the logic
signals as well as for the DC/DC converter. The result is a small
form-factor total-isolation solution.
ADuM524x units may be used in combination or with other
iCoupler products to achieve greater channel counts.
The ADuM524x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see Ordering Guide) operating off a 5V input supply.
1
Protected by U.S. Patents 5,952,849 6,873,065 and 7,075,329 Other patents
pending.
FUNCTIONAL BLOCK DIAGRAM
VDD 1
osc.
rect.
8 VISO
VDD 1
osc.
rect.
8 VISO
VDD 1
osc.
rect.
8 VISO
VIA 2
ENCODE
DECODE
7 VOA
VOA 2
DECODE
ENCODE
7 VIA
VOA 2
DECODE
ENCODE
7 V
IA
VIB 3
ENCODE
DECODE
6 VOB
VIB 3
ENCODE
DECODE
6 VOB
VOB 3
DECODE
ENCODE
6 VIB
GND 4
GND
5 GNDISO
Figure 1. ADuM5240 Functional Block
Diagram
4
GND
5 GNDISO
Figure 2. ADuM5241 Functional Block
Diagram
4
5 GNDISO
Figure 3. ADuM5242 Functional Block
Diagram
Rev. PrN
November 17, 2006
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2006 Analog Devices, Inc. All rights reserved.
ADuM5240/ADuM5241/ADuM5242
Preliminary Technical Data
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD = 5.0 V, VISO = 5.0 V.
Table 1.
Parameter
With DC/DC Converter Enabled:
DC to 2 Mbps Data Rate:
Setpoint
Maximum Output Current
Input Supply Current2
At Maximum Output Current
With No Output Current
10 Mbps Data Rate:
Setpoint
Maximum Output Current
ADuM5240
ADuM5241
ADum5242
Input Supply Current3
At Maximum Output Current
With No Output Current
With DC/DC Converter Disabled:
DC to 2 Mbps
Input Supply Current, VDD 2
ADuM5240
ADuM5241
ADuM5242
Input Supply Current, VISO 2
ADuM5240
ADuM5241
ADum5242
10 Mbps
Input Supply Current, VDD 2
ADuM5240
ADuM5241
ADum5242
Input Supply Current, VISO 2
ADuM5240
ADuM5241
ADuM5242
Enable Threshold4
4
Symbol
Min
VISO
IISO(max)
5.0
10
Typ
Max
Unit
5.5
V
mA
125
95
mA
mA
5.5
V
Test Conditions
Logic signal freq. ≤ 1 MHz
IDD(max)
IDD(0)
VISO
IISO(max, 10)
4.5
8.5
7.0
5.7
mA
mA
mA
IDD(max)
IDD(0)
125
100
mA
mA
IDD(2)
3.3
2.7
2.2
mA
mA
mA
1.6
3.1
2.5
mA
mA
mA
IISO=0, Logic signal freq.≤5 MHz
VENABLE
VDISABLE
IIA, IIB
VIH
VIL
VOAH, VOBH
Logic Low Output Voltages
VOAL, VOBL
IISO(max, 10), Logic signal freq. = 5 MHz
IISO = 0, Logic signal freq. = 5 MHz
Logic signal freq.≤1 MHz
IDD(10)
Disable Threshold
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
IISO = 10 mA, Logic signal freq. ≤ 1 MHz
IISO= 0
Logic signal freq. = 5 MHz
4.0
−10
0.3 VISO
VDD, − 0.1
VDD, − 0.5
+0.01
5.0
4.8
0.0
0.0
Rev. PrN | Page 2 of 10
6.1
5.0
4.0
mA
mA
mA
3.8
5.0
6.2
4.5
mA
mA
mA
V
4.5
+10
0.7 VISO
V
μA
V
V
V
V
V
V
0.1
0.4
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Preliminary Technical Data
Parameter
AC SPECIFICATIONS
Minimum Pulse Width5
Maximum Data Rate6
Propagation Delay7
Pulse-Width Distortion, |tPLH − tPHL|7
Propagation Delay Skew8
Channel-to-Channel Matching,
Codirectional Channels9
Channel-to-Channel Matching,
Opposing-Directional Channels10
Ripple11
Enable Time12
Disable Time12
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Refresh Frequency
ADuM5240/ADuM5241/ADuM5242
Symbol
Min
Typ
PW
tPHL, tPLH
PWD
tPSK
tPSKCD
10
25
tPSKCD
TENABLE
TDISABLE
tR/tF
|CMH|
|CML|
Max
Unit
Test Conditions
100
70
3
45
3
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
15
ns
CL = 15 pF, CMOS signal levels
25
200
50
50
2.5
35
mVP-P
ns
ns
ns
kV/μs
25
35
kV/μs
1.0
MHz
fr
CL = 15 pF, CMOS signal levels
VIx = VDD, VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, V = 1000 V,
transient magnitude = 800 V
1
All voltages are relative to their respective ground.
Supply current values are specified with no load present on the digital outputs.
3
Supply current values are specified with no load present on the digital outputs.
4
Enable/disable threshold is the voltage at which the internal DC/DC converter is enabled/disabled.
5
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
6
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
7
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
8
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
9
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
10
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
11
Ripple occurs at frequency corresponding to the input signal data rate or the refresh frequency for data rates below 1Mbps.
12
Enable time is the duration from when input supply voltage rises above the enable threshold to when the internal DC/DC converter starts charging an external load.
Disable time is the duration from when the input supply voltage drops below the disable threshold to when the internal DC/DC converter stops charging an external
load
2
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input-Output)
Capacitance (Input-Output)
Input Capacitance
IC Junction-to-Air Thermal Resistance
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
1.0
4.0
150
Rev. PrN | Page 3 of 10
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
f = 1 MHz
ADuM5240/ADuM5241/ADuM5242
Preliminary Technical Data
REGULATORY INFORMATION
The ADuM5240/5241/5242 will be approved by the following organizations upon product release:
Table 3.
UL (pending)
Recognized under 1577 Component
Recognition Program1
Basic insulation, 2500 V rms isolation
rating
CSA (pending)
Approved under CSA Component
Acceptance Notice #5A
Basic insulation per CSA 60950-1-03
and IEC 60950-1, 300 V rms (425 V
peak) maximum working voltage
VDE (pending)
Certified according to
DIN EN 60747-5-2 (VDE 0884 Part 2):2003-012
Basic insulation,300 V rms (425 V peak) maximum
working voltage
File E214100
File 205078
File 2471900-4880-0001
1
2
In accordance with UL1577, each ADuM524x is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).
In accordance with DIN EN 60747-5-2, each ADuM524x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection
limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
Isolation Group
L(I01)
Value
2500
4.90 min
Unit
V rms
mm
L(I02)
4.01 min
mm
0.017 min
mm
Conditions
1 minute duration
Measured from input terminals to output terminals, shortest
distance through air
Measured from input terminals to output terminals, shortest
distance path along body
Insulation distance through insulation
>175
V
DIN IEC 112/VDE 0303 Part 1
CTI
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. PrN | Page 4 of 10
Preliminary Technical Data
ADuM5240/ADuM5241/ADuM5242
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 5.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)
Safety-Limiting Values (maximum value allowed in the event of a failure; also see the thermal
derating curve, Figure 4)
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Unit
VIORM
VPR
I−IV
I−III
40/105/21
2
425
797
V peak
V peak
680
V peak
VTR
510
4000
V peak
V peak
TS
IS1
IS2
RS
150
160
170
>109
°C
mA
mA
Ω
VPR
Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 425 V peak working voltage.
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
[Figure to be added]
RECOMMENDED OPERATING CONDITIONS
Figure 4. Thermal Derating Curve, Dependence of Safety
Limiting Values on Case Temperature, per DIN EN 60747-52
Table 6.
Parameter
Operating Temperature
Supply Voltages1
VDD, DC/DC Conv. Enabled
VDD, DC/DC Conv. Disabled
VISO, DC/DC Conv. Disabled
Input Signal Rise and Fall Times
Input Supply Slew Rate
1
Symbol
TA
Min
−40
Max
+105
Unit
°C
VDD
VDD
VISO
4.5
2.7
2.7
5.5
4.0
5.5
1.0
10
V
V
V
ms
V/ms
All voltages are relative to their respective ground.
Rev. PrN | Page 5 of 10
ADuM5240/ADuM5241/ADuM5242
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 7.
Parameter
Storage Temperature
Ambient Operating Temperature
Supply Voltages1
Input Voltage1
Output Voltage1
Average Output Current, per Pin2
Common-Mode Transients3
Symbol
TST
TA
VDD, VISO
VIA, VIB
VOA, VOB
IO
Min
−55
−40
−0.5
−0.5
−0.5
Max
150
105
7.0
VDD/ISO + 0.5
VDD/ISO + 0.5
−100
+100
Unit
°C
°C
V
V
V
mA
kV/μs
1
All voltages are relative to their respective ground.
See Figure 4 for maximum rated current values for various temperatures.
3
Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or
permanent damage.
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 8. Truth Table, ADuM5240
VDD State
Powered
DC/DC
Converter
Enabled
Powered
Enabled
Powered
Enabled
Powered
Enabled
Powered
Disabled
Powered
Disabled
Powered
Disabled
Powered
Disabled
Powered
Unpowered
Disabled
Disabled
Unpowered
Disabled
VISO State
Powered
(Internally)
Powered
(Internally)
Powered
(Internally)
Powered
(Internally)
Powered
(Externally)
Powered
(Externally)
Powered
(Externally)
Powered
(Externally)
Unpowered
Powered
(Externally)
Unpowered
VIA
Input
H
VIB
Input
H
VOA
Output
H
VOB
Output
H
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
L
L
L
L
H
L
H
L
L
H
L
H
X
X
X
X
Z
L
Z
L
X
X
Z
Z
Rev. PrN | Page 6 of 10
Preliminary Technical Data
ADuM5240/ADuM5241/ADuM5242
Table 9. Truth Table, ADuM5241
VDD State
Powered
DC/DC
Converter
Enabled
Powered
Enabled
Powered
Enabled
Powered
Enabled
Powered
Disabled
Powered
Disabled
Powered
Disabled
Powered
Disabled
Powered
Unpowered
Disabled
Disabled
Unpowered
Disabled
VISO State
Powered
(Internally)
Powered
(Internally)
Powered
(Internally)
Powered
(Internally)
Powered
(Externally)
Powered
(Externally)
Powered
(Externally)
Powered
(Externally)
Unpowered
Powered
(Externally)
Unpowered
VIA
Input
H
VIB
Input
H
VOA
Output
H
VOB
Output
H
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
L
L
L
L
H
L
H
L
L
H
L
H
X
X
X
X
L
Z
Z
L
X
X
Z
Z
VIA
Input
H
VIB
Input
H
VOA
Output
H
VOB
Output
H
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
L
L
L
L
H
L
H
L
L
H
L
H
X
X
X
X
L
Z
L
Z
X
X
Z
Z
Table 10. Truth Table, ADuM5242
VDD State
Powered
DC/DC
Converter
Enabled
Powered
Enabled
Powered
Enabled
Powered
Enabled
Powered
Disabled
Powered
Disabled
Powered
Disabled
Powered
Disabled
Powered
Unpowered
Disabled
Disabled
Unpowered
Disabled
VISO State
Powered
(Internally)
Powered
(Internally)
Powered
(Internally)
Powered
(Internally)
Powered
(Externally)
Powered
(Externally)
Powered
(Externally)
Powered
(Externally)
Unpowered
Powered
(Externally)
Unpowered
Rev. PrN | Page 7 of 10
ADuM5240/ADuM5241/ADuM5242
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIA 2
ADuM5240
7 VOA
TOP VIEW
6 VOB
(Not to Scale)
4
5 GNDISO
GND
VOA 2
VDD 1
ADuM5241
7 VIA
TOP VIEW
6 VOB
(Not to Scale)
4
5 GNDISO
GND
VIB 3
Figure 5. ADuM5240 Pin
Configuration
8 VISO
VDD 1
8 VISO
VDD 1
VIB 3
Figure 6. ADuM5241 Pin
Configuration
VOA 2
8 VISO
ADuM5242
7 VIA
TOP VIEW
6 VIB
(Not to Scale)
5 GNDISO
4
GND
VOB 3
Figure 7. ADuM5242 Pin
Configuration
Table 11. ADuM5240 Pin Function Descriptions
Table 13. ADuM5242 Pin Function Descriptions
Pin
No.
1
Mnemonic
VDD1
Pin
No.
1
Mnemonic
VDD1
2
3
4
VIA
VIB
GND
2
3
4
VOA
VOB
GND
5
GNDISO
5
GNDISO
6
7
8
VOB
VOA
VISO
6
7
8
VIB
VIA
VISO
Function
Supply Voltage for Isolator Side 1,
4.5 V to 5.5 V (DC/DC Enabled), 2.7 V to 4.0
V (DC/DC Disabled)
Logic Input A.
Logic Input B.
Ground. Ground reference for Isolator
Side 1.
Isolated Ground. Ground reference for
Isolator Side 2.
Logic Output B.
Logic Output A.
Isolated Supply Voltage for Isolator Side 2,
5.0 V to 5.5 V Output (DC/DC Enabled), 4.5
V to 5.5 V Input (DC/DC Disabled)
Table 12. ADuM5241 Pin Function Descriptions
Pin
No.
1
Mnemonic
VDD1
2
3
4
VOA
VIB
GND
5
GNDISO
6
7
8
VOB
VIA
VISO
Function
Supply Voltage for Isolator Side 1,
4.5 V to 5.5 V (DC/DC Enabled), 2.7 V to 4.0
V (DC/DC Disabled)
Logic Output A.
Logic Input B.
Ground. Ground reference for Isolator
Side 1.
Isolated Ground. Ground reference for
Isolator Side 2.
Logic Output B.
Logic Input A.
Isolated Supply Voltage for Isolator Side 2,
5.0 V to 5.5 V Output (DC/DC Enabled), 4.5
V to 5.5 V Input (DC/DC Disabled)
Rev. PrN | Page 8 of 10
Function
Supply Voltage for Isolator Side 1,
4.5 V to 5.5 V (DC/DC Enabled), 2.7 V to 4.0
V (DC/DC Disabled)
Logic Output A.
Logic Output B.
Ground. Ground reference for Isolator
Side 1.
Isolated Ground. Ground reference for
Isolator Side 2.
Logic Input B.
Logic Input A.
Isolated Supply Voltage for Isolator Side 2,
5.0 V to 5.5 V Output (DC/DC Enabled), 4.5
V to 5.5 V Input (DC/DC Disabled)
Preliminary Technical Data
ADuM5240/ADuM5241/ADuM5242
APPLICATION INFORMATION
DC/DC CONVERTER
The ADuM524x can be operated with the internal DC/DC
enabled or disabled. With the internal DC/DC converter
enabled, the Pin 8 isolated supply provides output power as well
as power to the part’s isolated-side circuitry. Since the power
consumed by the ADuM524x is a function of the input signals’
data rate, the available isolated output power is determined by
the data rate at which the part’s data channels are operating.
The ADuM524x’s internal DC/DC converter state is controlled
by the input VDD voltage as defined in Table 6. In normal
operating mode, VDD is set between 4.5 V and 5.5 V and the
internal DC/DC converter is enabled. When/if it is desired to
disable the DC/DC converter, VDD is lowered to a value between
2.7 V and 4.0 V. In this mode, the VISO supply is supplied by the
user and the ADuM524x’s signal channels continue to operate
normally.
GUIDELINES FOR PRE-PRODUCTION SAMPLES
Pre production samples meet all data sheet specifications;
however, a limitation in the internal circuitry of the ADuM524x
prevents proper start-up under all load conditions. This
limitation will be corrected in the final product.
At certain temperature and load conditions the ADuM524x will
not regulate its VISO output to the 5.25V target voltage at
converter start-up. The output stabilizes at just under 4V with
no external load or as low as 3V with an external load. If the
converter starts successfully, the output voltage will continue to
regulate properly even as temperature and load conditions
change.
The start-up issue is affected by several circuit and
environmental conditions: slew rate applied to VDD1, ambient
temperature, and VISO capacitive load. The recommendations in
the PC board layout section address the VDD1 slew rate
dependence in most cases. Good results have been obtained
when the system power supply slews at ~0.5V/μS. Faster slew
rates can be tolerated but should be verified over temperature.
Table 14 contains guidelines for the maximum reliable start-up
temperature for two common values of load capacitance.
The VISO start-up issue is strongly temperature dependant. The
ADuM542x dissipates between 40 and 63mW under normal
operation, causing the internal temperature of the device to be
higher than ambient during normal operation. A “warm start”
after the device has reached its equilibrium temperature is the
worst case condition and will give the highest probability of
incorrect regulation of output voltage. The guidelines in Table
14 are based on “warm start” at full load. Cold start will be
successful at higher ambient temperatures.
When these guidelines are followed, pre-production samples
may be used for prototype and evaluation. As mentioned above
this issue will be corrected in final silicon and the ADuM524x
will operate at specified load and temperature conditions.
Table 14. Special Usage Conditions for Pre-production
Devices
Max Temperature by Load Capacitance1
1
ADuM5240
10nF
105°C
100nF
ADuM5241
105°C
Not Recommended
65°C
ADuM5242
80°C
80°C
Value of load capacitor C3 in Figure 8
PC BOARD LAYOUT
The ADuM524x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins as
shown in Figure 8. For the ADuM5240 and ADuM5241, a
bypass capacitance (C1) of 44 μF is required at the VDD input to
ensure proper power-up. For all models bypass capacitance is
recommended with C2=0.1 μF on the non-isolated side and
C3=10 nF on the isolated side. Due to high inductance
associated with larger capacitors such as C1, it is recommended
that both C1 and C2 be used on the ADuM5240 and
ADuM5241. The bypass capacitors should be placed as close as
possible to the ADuM524x device.
In cases where EMI is a concern, inductance should be added
between the system supply and ground and the ADuM524x
supply and ground as shown in Figure 8. Inductance can be
added in the form of discrete inductors or ferrite beads, and it’s
recommended the value correspond to an impedance between
50Ω and 100Ω at approximately 300MHz.
Figure 8. Recommended Application Circuit. C1 may be
omitted for ADuM5242, and L1 and L2 should be included
where EMI is a concern.
Rev. PrN | Page 9 of 10
ADuM5240/ADuM5241/ADuM5242
Preliminary Technical Data
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
0.31 (0.0122)
SEATING
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 9. 8-Lead Standard Small Outline Package [SOIC]—Narrow Body
(R-8)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model
ADuM5240BRZ2,3
ADuM5241BRZ2, 3
ADuM5242BRZ2, 3
1
2
3
Number
of Inputs,
VDD1 Side
2
1
0
Number
of Inputs,
VDD2 Side
0
1
2
Maximum
Data Rate
(Mbps)
10
10
10
Temperature
Range (°C)
−40 to +105
−40 to +105
−40 to +105
Package
Option1
R-8
R-8
R-8
R-8 = 8-lead narrow body SOIC.
Tape and reel are available. The addition of an “-RL7” suffix designates a 7” (1,000 units) tape and reel option.
Z = Pb-free part.
Rev. PrN | Page 10 of 10
PR06014-0-11/06(PrN)
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