www.fairchildsemi.com RM3283 Dual ARINC 429 Line Receiver Features • • • • • • • • Two separate analog receiver channels Converts ARINC 429 levels to serial data Built-in TTL compatible complete channel test inputs TTL and CMOS compatible outputs Low power dissipation Internal bandgap Short circuit protected Available in 20-Lead ceramic DIP Description The RM3283 consists of two analog ARINC 429 receivers which take differentially encoded ARINC level data and convert it to serial TTL level data. The RM3283 provides two complete analog ARINC receivers and no external components are required. Input level shifting thin film resistors and bipolar technology allow ARINC input voltage transients up to ±100V without damage to the RM3283. Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible. Two TTL compatible test inputs used to test the ARINC channels are available. They can be used to override the ARINC input data and set the channel outputs to a known state. The Fairchild RM3182A line driver is the companion chip to the RM3283 line receiver. Together they provide the analog functions needed for the ARINC 429 interface. Digital data processing involving serial-to-parallel conversion and clock recovery can be accomplished using one of the ARINC interface IC’s available or by an equivalent gate array implementation. Block Diagram +VL +VS 11 RM3283 In 1A In 1B Cap 1A Cap 1B Test A Test B Cap 2A Cap 2B In 2A In 2B 9 Bit Detection and Level Shifting Hysteresis 18 16 15 Output Driver 12 Out 1A Out 1B 19 17 2 20 Channel Test Circuitry Bandgap Voltage Reference Threshold Generator 7 3 Bit Detection and Level Shifting Hysteresis 6 4 1 -VS 8 Output Driver 5 Out 2A Out 2B 14 Gnd 65-3283-01 REV. 1.0.1 12/7/00 RM3283 PRODUCT SPECIFICATION Pin Assignments DIP Top View -VS 20 TestB TestA 2 19 Cap1A Cap2B 3 18 In1A In2B 4 17 Cap1B Out2B 5 16 In1B In2A 6 15 Out1A Cap2A 7 14 GND Out2A 8 13 NC +VL 9 12 Out1B NC 10 11 +VS 65-3283-02 Functional Description The RM3283 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. The first stage provides overvoltage protection and biases the signal using voltage dividers and current sources, providing excellent input common mode rejection. The test inputs are provided to set the outputs to a predetermined state for built-in channel test capability. If the test inputs are not used, they should be grounded. The window comparator section detects data from the resistor input network. A Logic 1 corresponds to ARINC “High” state (OUTA) and a Logic 0, to ARINC “Low” state (OutB). An ARINC “Null” state at the inputs forces both outputs to Logic 0. Threshold and hysteresis voltages are generated by a bandgap voltage reference to maintain stable switching characteristics over temperature and power supply variations. The output stage generates a TTL compatible logic output capable of driving 3mA of load. Absolute Maximum Ratings Parameter Min. Max. Units Supply Voltage (VCC to VEE) +36 V VLOGIC Voltage +7 V VLOGIC + 0.3 V Logic Input Voltage Temperature Range -0.3 Storage -65 +150 °C Operating -55 +125 °C -55 +175 °C 60 sec., DIP, LCC +300 °C 10 sec., SOIC +260 °C Junction Temperature Lead Soldering Temperature 2 REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION RM3283 Thermal Characteristics (Still air, soldered on a PC board) Parameter DIP Maximum Junction Temperature +175°C Thermal Resistance, θJC 70°C/W Thermal Resistance, θJC 28°C/W1 Note: 1. MIL-STD-1835. DC Electrical Characteristics TA = -55°C to +125°C, ±12V ≤ VS ±15V, VL = +5V, unless otherwise noted. Symbol ICC (+VS) IEE (-VS) IL (VL) VTL2 VTH2 VIN VIC3 Parameter Test inputs = 0V Test inputs = 0V Test inputs = 5V V(A)-V(B) V(A)-V(B) V(A)-V(B) V(A) and V(B)-GND RI Input resistance, Input A to Input B RH Input resistance, Input A to Gnd RG Input resistance, B to Gnd CI1,4 Input capacitance, A to B 1,4 CH Input capacitance, A to Gnd CG1,4 Input capacitance, B to Gnd Test Inputs (TestA, TestB) VIH5 Logic 1 input voltage 5 VIL Logic 0 input voltage IIH Logic 1 input current IIL Logic 0 input voltage Outputs VOH IOH = 100 µA IOH = 2.8 mA VOL IOL = 100 µA IOL = 2.0 mA Tr6 Rise Time Tf6 Fall Time TPLH Propagation delay Output low to high TPHL Output high to low Conditlons Min. Low threshold High threshold OutA and OutB = 0 4.7 5.7 -2.5 Maximum common mode frequency = 80 kHz Filter caps disconnected 35 20 20 Typ. 4.3 10.1 14.0 5.0 6.0 0 V 50 25 25 10 10 10 kΩ kΩ kΩ pF pF pF 0.8 300 40 V V µA µA 2.7 0 TA = 25°C Full temperature range TA = 25°C Full temperature range CL = 50 pF, @ 25°C CL = 50 pF, @ 25°C CL = 50 pF, f = 400 kHz Filter caps = 39 pF TA = 25°C 120 15 4.0 3.5 Units mA mA mA V V V ±5 Filter caps disconnected Filter caps disconnected VIH = 5V VIL = 0.8V Max. 6.0 12.0 17.5 5.3 6.3 2.5 4.3 4.0 0.02 0 50 40 700 0.1 0.8 70 70 700 V V V V ns ns ns ns Notes: 1. As stated in ARINC429. 2. VT refers ot the threshold voltage at which the channels output switches from low to high or from high to low. 3. Common mode voltage present at both ARINC inputs. 4. Guaranteed by design. 5. Test inputs should be connected to ground if not used. 6. Sample tested. REV. 1.0.1 12/7/00 3 RM3283 PRODUCT SPECIFICATION Typical Performance Characteristics 20 900 TPHL 800 16 TPLH Current (mA) 500 400 300 65-3283-04 200 100 0 -55 25 IL 14 600 12 10 I EE 8 6 I CC 4 65-3283-05 700 TPHL, TPLH (ns) 18 2 0 -55 125 25 125 Temperature (°C) Temperature (°C) Figure 1. Propagation Delay vs. Temperature CL = 50 pF, CFILTER = 39 pF Figure 2. Supply Current vs. Temperature 1.00 4.5 +125°C 4.3 +125°C +25°C 0.50 65-3283-06 0.25 +55°C 0 0 0.5 1.0 1.5 2.0 2.5 +25°C 4.1 3.9 -55°C 65-3283-07 VOH (Volts) VOL (Volts) 0.75 3.7 3.5 3.0 0 0.5 1.0 IOL (mA) 3.0 TF TR 30 65-3283-08 20 10 25 Temperature ( C) Figure 5. TR and TF vs. Temperature 125 T PLH 2.0 T PHL 1.5 1.0 65-3283-09 50 40 T A = +25 C 2.5 Prop Delay (µs) 60 Rise/Fall Time (ns) 3.0 2.5 Figure 4. Output Voltage High vs. Output Current 70 4 2.0 IOH (mA) Figure 3. Output Voltage Low vs. Output Current 0 -55 1.5 0.5 0 0 50 100 150 200 250 300 350 400 Filter Capacitance (pF) Figure 6. Propagation Delay vs. Filter Capacitance TA = 25°C REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION RM3283 AC Test Waveforms +10V ARINC In (Differential) 0V Logic Out (A Output) 90% 90% Logic Out 10% 10% T PLH TF TR T PHL 65-3283-10 65-3283-11 Figure 7. Propagation Delay Figure 8. Rise/Fall Times Test Circuit +15V 0.1 µF -15V 0.01 µF +5V 0.01 µF In1 A 11 18 9 1 Out 1A 15 50 pF In2 A 6 50 pF RM3283 16 VREF Out 1B 12 Out 2A 8 4 50 pF 19 17 3 7 14 Out 2B 5 50 pF 39pF 39pF 39pF 39pF Notes: 1. VIN = 400 kHz square wave, -3.5V to +3.5V. 2. Set VREF = +3.5 V to test VOUT1 and VOUT3. Set VREF = -3.5 V to test VOUT2 and VOUT4. 65-3283-12 3. 50 pF load capacitance includes probe and wiring capacitance. Figure 9. AC Test Schematic Diagram REV. 1.0.1 12/7/00 5 RM3283 PRODUCT SPECIFICATION Truth Table ARINC nputs V(A) - V(B) Test Inputs Outputs TESTA TESTB OUTA OUTB Output State Null 0 0 0 0 Null Low 0 0 0 1 Low High 0 0 1 0 High X 0 1 0 1 Low X 1 0 1 0 High X 1 1 0 0 Null Applications Discussion The standard connections for the RM3283 are shown in Figure 10. Dual supplies from ±12 to ±15 VDC are recommended for the ±VS supplies. Decoupling of all supplies should be done near the IC to avoid propagation of noise spikes due to switching transients. The ground connection should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possible. The noise filter capacitors are optional and are added to provide extra noise immunity by limiting bandwidth of the input signal before it reaches the window comparator stage. Two capacitors are required for each channel and they must all be the same value. The suggested capacitor value for a 100 kHz operation is 39 pF. For lower data rates, larger values of capacitance may be used to yield better node perfor- 6 mance. To get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate: –6 3.95 × 10 C FILTER = --------------------------FO Where CFILTER is the capacitor value in pF, and FO is the input frequency (10 kHz ≤ FO ≤ 150 kHz). The RM3283 can be used with the Fairchild RM3182A line driver to provide a complete analog ARINC 429 interface. A simple application which can be used for systems requiring a repeater-type circuit for long transmissions is given in Figure 11. More RM3182A drivers may be added to test multiple ARINC channels, as shown. REV. 1.0.1 12/7/00 RM3283 PRODUCT SPECIFICATION Applications +5V +15V 9 11 RM3283 18 ARINC Channel 1 16 39 pF 19 In 1A 15 In 1B Cap 1A 12 A B Channel 1 Data Out To Logic 17 Cap 1B 39 pF 6 ARINC Channel 2 4 In 2A 8 A In 2B 39 pF 7 3 5 Cap 2A Channel 2 Data Out To Logic B Cap 2B 39 pF 2 Logic Test Inputs 20 Test A Test B 1 14 65-3283-13 -15V Figure 10. ARINC Receiver Standard Connections ARINC Test Channel Input A In 1A Out 1A Data (B) In 1B B 1/2 RM3283 A OUT Data (A) A RM3182A B Out 2A B OUT A OUT Data (A) A RM3182A Data (B) To Additional Channels B OUT B Test Channel 1 Test Channel 2 65-3282-14 Figure 11. Repeater Circuit 7 REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION RM3283 Applications (continued) +5V +15V Inputs VCC +V L ARINC Channel 0 In 1A Out 1A H0 In 1B Out 1B L0 VSS RM3182A RM3283 ARINC Channel 1 In 2A Out 2A H1 In 2B Out 2B L1 V R V I Sync Clk +VS Mode N1 Data (A) N0 Data (B) Gnd PE EF4442 CA 75 pF -15V -15V CB 75 pF Reset +15V From Microprocessor IRQ +VS GND -VS In 1A Out 1A H2 R/W In 1B Out 1B L2 Clock RM3283 ARINC Channel 3 ARINC Line Out B OUT -VS +VS GND -VS ARINC Channel 2 A OUT Microprocessor Data Bus D0 - D8 In 2A Out 2A H3 In 2B Out 2B L3 A0 From Address Decoder A1 +VL 65-3283-15 CS To +5V Figure 12. Four-Channel ARINC Receiver Circuit -15V 10 Ω 1/2 W +15V 1 4 10K 18 5 10K 16 RM3283 6 10K 15 10K 8 14 9 11 12 10K 10K 10 Ω 1/2 W 10 Ω 1/2 W 65-3283-16 +5V +15V Figure 13. Burn-In Circuit REV. 1.0.1 12/7/00 8 RM3283 PRODUCT SPECIFICATION Mechanical Dimensions 20-Lead Ceramic DIP Symbol Inches Min. A b1 b2 c1 D E e eA L Q s1 α Max. — .200 .014 .023 .045 .065 .008 .015 — 1.060 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 — 90° 105° Millimeters Min. Notes Max. — 5.08 .36 .58 1.14 1.65 .20 .38 — 25.92 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 — 90° 105° 8 2, 8 8 4 4 5, 9 7 3 6 Notes: 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 10, 11 and 20 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within ±.010 (.25mm) of its exact longitudinal position relative to pins 1 and 20. 6. Applies to all four corner's (leads number 1, 10, 11, and 20). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "α" is 90°. 8. All leads – Increase maximum limit by .003(.08mm) measured at the center of the flat, when lead finish is applied. 9. Eighteen spaces. D Note 1 E s1 eA e A Q L b2 9 α c1 b1 REV. 1.0.1 12/7/00 PRODUCT SPECIFICATION RM3283 Ordering Information Part Number Package Operating Temperature Range RM3283D 20 Lead Ceramic DIP -55°C to +125°C LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12/7/00 0.0m 002 Stock# DS30003283 2000 Fairchild Semiconductor Corporation