Cypress CYM1846V33PM-20C 512k x 32 3.3v static ram module Datasheet

46V33
PRELIMINARY
CYM1846V33
512K x 32 3.3V Static RAM Module
Features
module is constructed from four 512K x 8 SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading
or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects.
• High-density 3.3V 16-megabit SRAM module
• 32-bit Standard Footprint supports densities from
16K x 32 through 2M x 32
• High-speed SRAMs
— Access time of 12 ns
• Low active power
— 1.650W (max.) at 12 ns
• 72 pins
• Available in ZIP, SIMM format
Functional Description
The CYM1846V33 is designed for use with standard 72-pin
SIMM sockets. The pinout is downward compatible with the
64-pin JEDEC ZIP/SIMM module family (CYM1821,
CYM1831, CYM1836, and CYM1841). Thus, a single motherboard design can be used to accommodate memory depth
ranging from 16K words (CYM1821) to 1,024K words
(CYM1851). The CYM1846V33 is offered in vertical SIMM
configuration and is available with either tin-lead or 10
micro-inches of gold flash on the edge contacts.
The CYM1846V33 is a high-performance 3.3V 16-megabit
static RAM module organized as 512K words by 32 bits. This
Presence detect pins (PD0−PD3) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
Pin Configuration
Logic Block Diagram
ZIP/SIMM
Top View
A0–A18
OE
PD0 PD1 PD2 PD3 -
19
OPEN
OPEN
GND
OPEN
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
WE
I/O0–I/O7
512K x 8
SRAM
8
512K x 8
SRAM
8
CS1
I/O7–I/O15
CS2
512K x 8
SRAM
8
512K x 8
SRAM
8
I/O16–I/O23
I/O24–I/O31
CS4
•
3901 North First Street
34
36
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
NC
NC
CS3
Cypress Semiconductor Corporation
Document #: 38-05275 Rev. **
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
•
San Jose
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
•
33
35
NC
PD2
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
CS2
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS 4
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
A18
NC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
CA 95134 • 408-943-2600
Revised March 15, 2002
PRELIMINARY
CYM1846V33
Selection Guide
1846V33-12
1846V33-15
1846V33-20
1846V33-25
1846V33-35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating Current (mA)
820
800
780
780
780
Maximum Standby Current (mA)
120
120
120
120
120
Shaded area contains advance information.
Maximum Ratings [1]
DC Input Voltage ............................................–0.5V to +4.6V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Operating Range
Ambient Temperature with
Power Applied............................................... –10°C to +85°C
Range
Ambient
Temperature
Commercial
0°C to +70°C
VCC
3.3V + 10%
/ –5%
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State ................................................ –0.5V to +VCC
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–10
+10
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–10
ICC
VCC Operating Supply
Current
VCC = Max., IOUT = 0 mA,
CSN < VIL, F = FMAX
ISB1
ISB2
Automatic CS Power-Down
Current[2]
Automatic CS Power-Down
Current[2]
Max. VCC, CS > VIH,
Min. Duty Cycle = 100%
2.4
V
+10
µA
−12
820
mA
−15
800
mA
−20,−25,−35
780
mA
–12
180
mA
−15
160
mA
−20,−25,−35
140
mA
120
mA
Max. VCC, CS > VCC − 0.2V, VIN > VCC − 0.2V,
or VIN < 0.2V
Shaded area contains advance information.
Capacitance[3]
Parameter
Description
CINA
Input Capacitance (WE, OE, A0–18)
CINB
Input Capacitance (CS)
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
32
pF
8
pF
8
pF
Notes:
1. If device is operated at these settings, long term reliability will be affected.
2. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
3. Tested on a sample basis.
Document #: 38-05275 Rev. **
Page 2 of 8
PRELIMINARY
CYM1846V33
AC Test Loads and Waveforms
R1 315 Ω
R1 315 Ω
5V
ALL INPUT PULSES
5V
OUTPUT
R2
351Ω
30 pF
INCLUDING
JIG AND
SCOPE
R2
351Ω
5 pF
INCLUDING
JIG AND
SCOPE
THÉVENIN
90%
10%
GND
10%
≤ 5 ns
≤ 5 ns
(b)
(c)
EQUIVALENT
167 Ω
OUTPUT
90%
OUTPUT
(a)
Equivalent to:
3.0V
1.73V
Switching Characteristics Over the Operating Range[4]
1846V33-12
Parameter
Description
Min.
Max.
1846V33-15
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
12
15
ns
tDOE
OE LOW to Data Valid
7
8
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
[5]
15
12
3
ns
15
3
0
ns
0
7
ns
8
CS LOW to Low Z
tHZCS
CS HIGH to High Z[5, 6]
7
8
ns
CS HIGH to Power-Down
12
15
ns
WRITE CYCLE
3
ns
tLZCS
tPD
3
ns
ns
[7]
tWC
Write Cycle Time
12
15
ns
tSCS
CS LOW to Write End
9
10
ns
tAW
Address Set-Up to Write End
9
10
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
1
1
ns
tPWE
WE Pulse Width
10
12
ns
tSD
Data Set-Up to Write End
7
8
ns
tHD
Data Hold from Write End
1
1
ns
tLZWE
WE HIGH to Low Z
3
tHZWE
WE LOW to High Z[6]
0
3
7
0
ns
8
ns
Shaded area contains advance information.
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.
6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05275 Rev. **
Page 3 of 8
PRELIMINARY
CYM1846V33
Switching Characteristics Over the Operating Range[4] (continued)
1846V33-20
Parameter
Description
Min.
Max.
1846V33-25
Min.
Max.
1846V33-35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z
20
25
20
3
3
20
3
[5, 6]
3
15
0
10
ns
35
25
12
0
[5]
35
25
ns
35
ns
18
ns
0
12
3
ns
ns
15
3
ns
ns
tHZCS
CS HIGH to High Z
10
12
15
ns
tPD
CS HIGH to Power-Down
20
25
35
ns
WRITE CYCLE
[7]
tWC
Write Cycle Time
20
25
35
ns
tSCS
CS LOW to Write End
17
20
30
ns
tAW
Address Set-Up to Write End
17
20
30
ns
tHA
Address Hold from Write End
3
3
3
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tPWE
WE Pulse Width
15
20
30
ns
tSD
Data Set-Up to Write End
12
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
3
3
ns
tHZWE
[6]
WE LOW to High Z
0
12
0
12
0
15
ns
Switching Waveforms
Read Cycle No. 1[8, 9]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
8. WE is HIGH for read cycle.
9. Device is continuously selected, CS = VIL, and OE= VIL.
Document #: 38-05275 Rev. **
Page 4 of 8
PRELIMINARY
CYM1846V33
Switching Waveforms (continued)
Read Cycle No. 2
[8,10]
tRC
CS
tACS
OE
tHZOE
tDOE
tHZCS
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
DATA OUT
tLZCS
tPD
tPU
ICC
V CC
SUPPLY
CURRENT
50%
50%
Write Cycle No. 1 (WE Controlled)
ISB
[7]
tWC
ADDRESS
tSCS
CS
tAW
tSA
tHA
tPWE
WE
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
tHD
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
Note:
10. Address valid prior to or coincident with CS transition LOW.
Document #: 38-05275 Rev. **
Page 5 of 8
PRELIMINARY
CYM1846V33
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled)
[7,11]
tWC
ADDRESS
tSCS
tSA
CS
tAW
tHA
tPWE
WE
tSD
DATA IN
tHD
DATA VALID
tHZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
Truth Table
CS
WE
OE
H
X
X
High Z
Inputs/Output
Deselect/Power-Down
Mode
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
High Z
Deselect
Ordering Information
Speed (ns)
12
15
20
25
Ordering Code
Package
Type
Package Type
CYM1846V33PM-12C
PM21
72-Pin Plastic SIMM Module
CYM1846V33P8-12C
PM21
72-Pin Plastic SIMM Module (gold contacts)
CYM1846V33PZ-12C
PZ11
72-Pin Plastic ZIP Module
CYM1846V33PM-15C
PM21
72-Pin Plastic SIMM Module
CYM1846V33P8-15C
PM11
72-Pin Plastic SIMM Module (gold contacts)
CYM1846V33PZ-15C
PZ11
72-Pin Plastic ZIP Module
CYM1846V33PM-20C
PM21
72-Pin Plastic SIMM Module
CYM1846V33P8-20C
PM21
72-Pin Plastic SIMM Module (gold contacts)
CYM1846V33PZ-20C
PZ11
72-Pin Plastic ZIP Module
CYM1846V33PM-25C
PM21
72-Pin Plastic SIMM Module
CYM1846V33P8-25C
PM21
72-Pin Plastic SIMM Module (gold contacts)
CYM1846V33PZ-25C
PZ11
72-Pin Plastic ZIP Module
Operating
Range
Commercial
Shaded area contains advance information.
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05275 Rev. **
Page 6 of 8
PRELIMINARY
CYM1846V33
Ordering Information (continued)
Speed (ns)
35
Ordering Code
Package
Type
Package Type
CYM1846V33PM-35C
PM21
72-Pin Plastic SIMM Module
CYM1846V33P8-35C
PM21
72-Pin Plastic SIMM Module (gold contacts)
CYM1846V33PZ-35C
PZ11
72-Pin Plastic ZIP Module
Operating
Range
Commercial
Package Diagrams
72-Pin Plastic SIMM Module PM21
72-Pin Plastic ZIP Module PZ11
Document #: 38-05275 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CYM1846V33
Document Title: CYM1846V33 512K x 32 3.3V Static RAM Module
Document Number: 38-05275
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
114176
3/19/02
DSG
Document #: 38-05275 Rev. **
Description of Change
Change from Spec number: 38-M-00089 to 38-05275
Page 8 of 8
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