IRF IRS2608DSPBF Half-bridge driver Datasheet

IRS2608DSPbF
June 1, 2011
IRS2608DSPbF
HALF-BRIDGE DRIVER
Features
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•
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•
•
•
•
•
•
•
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Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V, 5 V and 15 V input logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
High side output in phase with HIN input
Low side output out of phase with LIN input
Internal 530 ns dead-time
Lower di/dt gate driver for better noise immunity
Integrated bootstrap diode
Suitable for both trapezoidal and sinusoidal motor control
RoHS compliant
Packages
8-Lead SOIC
Applications:
*Air Conditioner
*Micro/Mini Inverter Drives
*General Purpose Inverters
*Motor Control
Description
The IRS2608D(S) is a high voltage, high speed power MOSFET an IGBT driver with dependent high and low side
referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic
construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output
drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel
can be used to drive an N-channel power MOSFET or 1GBT in the high side configuration which operates up to
600 V.
Typical Connection
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IRS2608DSPbF
†
Qualification Information
Industrial††
Comments: This IC has passed JEDEC’s
Industrial qualification. IR’s Consumer
qualification level is granted by extension of the
higher Industrial level.
Qualification Level
Moisture Sensitivity Level
Human Body Model
ESD
Machine Model
IC Latch-Up Test
RoHS Compliant
MSL2, 260°C
(per IPC/JEDEC J-STD-020)
Class 2
(per JEDEC standard JESD22-A114)
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Class I, Level A
(per JESD78)
Yes
† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information.
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IRS2608DSPbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
-0.3
620
VB
High side floating absolute voltage
VS
High side floating supply offset voltage
VB - 20
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side and logic fixed supply voltage
-0.3
20
VLO
Low side output voltage
-0.3
VCC + 0.3
COM -0.3
VCC - 20
VCC + 0.3
VCC + 0.3
VIN
COM
dVS/dt
PD
RthJA
Logic input voltage (HIN &LIN)
Logic ground
Allowable offset supply voltage transient
Units
V
—
50
V/ns
Package power dissipation @ TA ≤ +25°C
—
0.625
W
°C/W
Thermal resistance, junction to ambient
—
200
TJ
Junction temperature
—
150
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
—
300
°C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset rating are
tested with all supplies biased at 15V differential.
Symbol
Definition
VB
VS
High side floating supply absolute voltage
VSt
VHO
Transient High side floating supply offset voltage
High side floating output voltage
VCC
Low side and logic fixed supply voltage
VLO
VIN
Low side output voltage
TA
Ambient temperature
Static High side floating supply offset voltage
Logic input voltage
Min.
Max.
VS +10
COM- 8(Note 1)
VS +20
600
-50 (Note2)
600
VS
VB
10
20
0
COM
-40
VCC
VCC
125
Units
V
°C
Note 1: Logic operational for VS of -8 V to +600 V. Logic state held for VS of -8 V to – VBS.
Note 2: Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the
Application Information section of this datasheet for more details.
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IRS2608DSPbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, COM = VCC, CL = 1000 pF, TA = 25°C.
Symbol
Definition
Min Typ Max Units Test Conditions
ton
Turn-on propagation delay
120
250
380
toff
Turn-off propagation delay
Delay matching
ton - toff
120
250
380
MT
—
—
60
tr
Turn-on rise time
—
150
220
tf
Turn-off fall time
Deadtime: LO turn-off to HO turn-on(DTLO-HO)
& HO turn-off to LO turn-on (DTHO-LO)
Delay matching time (t ON , t OFF)
Deadtime matching = DTLO-HO - DTHO-LO
—
50
80
350
530
800
—
—
—
—
60
60
DT
MT
MDT
VS = 0 V or 600 V
VS = 0 V or 600 V
nsec
VS = 0 V
VS = 0 V
VIN = 0 V & 5 V
Without external
deadtime
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V, and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to COM
and are applicable to the respective input leads: HIN and LIN. The VO, IO and Ron parameters are referenced to COM and
are applicable to the respective output leads: HO and LO.
Symbol
Definition
Min Typ Max Units Test Conditions
VIL
Logic “1” input voltage for HIN & logic “0” for LIN —
Logic “0” input voltage for HIN & logic “1” for LIN 0.8
—
—
VOH
High level output voltage, VBIAS - VO
—
0.8
1.4
VOL
Low level output voltage, VO
—
0.3
0.6
ILK
Offset supply leakage current
—
—
50
VB = VS = 600 V
IQBS
Quiescent VBS supply current
—
45
70
VIN = 0 V or 4 V
IQCC
Quiescent VCC supply current
IIN+
IIN-
Logic “1” input bias current
Logic “0” input bias current
VCC and VBS supply undervoltage positive going
threshold
VCC and VBS supply undervoltage negative going
threshold
—
—
15
10
30
20
8.0
8.9
9.8
7.4
8.2
9.0
Hysteresis
—
0.7
—
120
200
—
250
350
—
—
200
—
VIH
VCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
IO+
IORbs
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Output high short circuit pulsed current
Output low short circuit pulsed current
Bootstrap resistance
—
2.2
1000 1700 3000
V
IO = 20 mA
µA
VIN = 0 V or 4 V
VIN = 4 V
VIN = 0 V
V
mA
VO = 0 V,
PW ≤ 10 us
VO = 15 V,
PW ≤ 10 us
Ohm
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IRS2608DSPbF
Functional Block Diagrams
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IRS2608DSPbF
Lead Definitions
Symbol
HIN
LIN
VB
HO
VS
Description
Logic input for high side gate driver output (HO), in phase
Logic input for low side driver output (LO), out of phase
High side floating supply
High side gate drive output
High side floating supply return
VCC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
1
VCC
VB
8
2
HIN
HO
7
3
LIN
VS
6
4
COM
LO
5
8 Lead SOIC
IRS2608DS
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IRS2608DSPbF
Application Information and Additional Details
Informations regarding the following topics are included as subsections within this section of the datasheet.
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IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Undervoltage Lockout Protection
Shoot-Through Protection
Integrated Bootstrap Functionality
Negative VS Transient SOA
PCB Layout Tips
Integrated Bootstrap FET limitation
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS2608D HVICs are designed to drive MOSFET or IGBT power devices. Figures 1 and 2 illustrate several
parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the
gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as
VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called
VOUT and in this case does not differentiate between the high-side or low-side output voltage.
VB
(or VCC)
VB
(or VCC)
IO+
HO
(or LO)
+
HO
(or LO)
IO-
VHO (or VLO)
VS
(or COM)
-
Figure 1: HVIC sourcing current
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VS
(or COM)
Figure 2: HVIC sinking current
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IRS2608DSPbF
Switching and Timing Relationships
The relationships between the input and output signals of the IRS2608D are illustrated below in Figures 3, 4. From
these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated
with this device.
LIN
50%
ton
50%
toff
tr
90%
LO
10%
tf
90%
10%
Figure 3: Switching time waveforms
Figure 4: Input/output timing diagram
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC
portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum
deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned
off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserter whenever the
external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the
deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS2608D is matched with respect to the high- and low-side outputs. Figure 5 defines the two deadtime
parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT) associated with the IRS2608D specifies the
maximum difference between DTLO-HO and DTHO-LO.
Matched Propagation Delays
The IRS2608D family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the
low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter
(MT). The propagation turn-on delay (tON) of the IRS2608D is matched to the propagation turn-on delay (tOFF).
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IRS2608DSPbF
Figure 5: Delay Matching Waveform Definition
Input Logic Compatibility
LIN Input Signal
Input Signal
(IRS23364D)
Input Logic
Level
Input Logic
Level
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2608D has been designed to be
compatible with 3.3 V and 5 V logic-level signals. The IRS2608D features an integrated 5.2 V Zener clamp on the /LIN.
Figure 6 illustrates an input signal to the IRS2608D, its input threshold values, and the logic state of the IC as a result of
the input signal.
V IH
VIL
High
Low
Low
Figure 6: HIN & LIN input thresholds
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IRS2608DSPbF
Undervoltage Lockout Protection
This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply
and the VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over
time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or
disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC
voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault
condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to
inform the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS
voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault
condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be
driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this
could result in very high conduction losses within the power device and could lead to power device failure.
Figure 7: UVLO protection
Shoot-Through Protection
The IRS2608D high-voltage ICs is equipped with shoot-through protection circuitry (also known as cross-conduction
prevention circuitry).
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IRS2608DSPbF
Integrated Bootstrap Functionality
The IRS2608D embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide
range of applications.
A bootstrap FET is connected between the floating supply VB and VCC (see Fig. 8).
Vcc
BootFet
Vb
Figure 8: Semplified BootFET connection
The bootstrap FET is suitable for most PWM modulation schemes, including trapezoidal control, and can be used
either in parallel with the external bootstrap network (diode+ resistor) or as a replacement of it. The use of the
integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following
situations:
• When the motor runs at a very low current (so that the negative phase voltage decay can be longer than
20us) and complementary PWM is not used.
• At a very high PWM duty cycle due to the bootstrap FET equivalent resistance (RBS, see page 3).
The summary for the bootstrap state follows:
• Bootstrap turns-off (immediately) or stays off when at least one of the following conditions are met:
1- HO goes/is high
2- VB goes/is high (> 1.1*VCC)
• Bootstrap turns-on when:
1- LO is high (low side is on) AND VB is low (< 1.1(VCC))
2- LO and HO are low after a LIN transition from H to L (HB output is in tri-state) AND VB goes low
(<1.1*VCC) before a fixed time of 20us.
3- LO and HO are low after a HIN transition from H to L (HB output is in tri-state) AND VB goes low
(<1.1(VCC)) before a retriggerable time of 20us. In this case the time counter is kept in reset state until
VB goes high (>1.1VCC). Please refer to the BootFET timing diagram for more details.
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IRS2608DSPbF
20 us timer
Timer is reset
counter
Timer is reset
Timer expired
HIN
LIN
BootStrap
Fet
VB
1.1*Vcc
+
-
Figure 9: BootFET timing diagram
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IRS2608DSPbF
Negative VS Transient SOA
A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as
the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is
shown in Figure 10; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 11 and 12) switches off, while the U phase current is flowing to an
inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side
switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to
the negative DC bus voltage.
Figure 10: Three phase inverter
DC+ BUS
Q1
ON
IU
VS1
Q2
OFF
D2
DC- BUS
Figure 11: Q1 conducting
Figure 12: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 13 and 14), and Q4 IGBT
switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from
the positive DC bus voltage to the negative DC bus voltage.
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IRS2608DSPbF
Figure 13: D3 conducting
Figure 14: Q4 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it
swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 15 depicts one leg of the three phase inverter; Figures 16 and 17 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the
die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is
below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit.
When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to
the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which
is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced
(i.e., the COM pin of the HVIC is at a higher potential than the VS pin).
Figure 15: Parasitic Elements
Figure 16: VS positive
Figure 17: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater
than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. An indication of the IRS2608D’s robustness can be seen in Figure 18, where there is represented the
IRS2608D Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage
falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or
permanent damage to the IC do not appear if negative Vs transients fall inside SOA.
At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by
design the high-side outputs in the off state for 4.5 µs.
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IRS2608DSPbF
Figure 18: Negative VS transient SOA for IRS2608D @ VBS=15V
Even though the IRS2608D has been shown able to handle these large negative VS transient conditions, it is highly
recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB
layout and component use.
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the
floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case Outline
information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 19).
In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be
reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate
parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the
gate-emitter, thus increasing the possibility of a self turn-on effect.
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IRS2608DSPbF
Figure 19: Antenna Loops
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic 1 µF
ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in
order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the
switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is
recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to
negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to
reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 20),
and in some cases using a clamping diode between COM and VS (see Figure 21). See DT04-4 at www.irf.com for more
detailed information.
Figure 20: VS resistor
Figure 21: VS clamping diode
Integrated Bootstrap FET limitation
The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied
to the HVIC:
•
•
VCC pin voltage = 0V
VS or VB pin voltage > 0
AND
In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a
current conduction path is created between VCC & VB pins, as illustrated in Fig.22 below, resulting in power loss
and possible damage to the HVIC.
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IRS2608DSPbF
Figure 22: Current conduction path between VCC and VB pin
Relevant Application Situations:
The above mentioned bias condition may be encountered under the following situations:
• In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In
this condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes
resulting unwanted current flow to VCC.
• Potential situations in other applications where VS/VB node voltage potential increases before the VCC
voltage is available (for example due to sequencing delays in SMPS supplying VCC bias)
Application Workaround:
Insertion of a standard p-n junction diode between VCC pin of IC and positive terminal of VCC capacitors (as
illustrated in Fig.23) prevents current conduction “out-of” VCC pin of gate driver IC. It is important not to connect the
VCC capacitor directly to pin of IC. Diode selection is based on 25V rating or above & current capability aligned to
ICC consumption of IC - 100mA should cover most application situations. As an example, Part number # LL4154
from Diodes Inc (25V/150mA standard diode) can be used.
VCC
VCC
Capacitor
VB
VSS
(or COM)
Figure 23: Diode insertion between VCC pin and VCC capacitor
Note that the forward voltage drop on the diode (VF) must be taken into account when biasing the VCC pin of the IC
to meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – VF of Diode.
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IRS2608DSPbF
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function
and the document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
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IRS2608DSPbF
Parameters trend in temperature
500
Turn-Off Propagation Delay (ns)
Turn-On Propagation Delay (ns)
Figures 24-43 provide information on the experimental performance of the IRS2608D(S) HVIC. The line plotted in each
figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three
temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist
of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the
understood trend. The individual data points on the curve were determined by calculating the averaged experimental value
of the parameter (for a given temperature).
400
300
Exp.
200
100
0
-50
-25
0
25
50
75
100
500
400
300
Exp.
200
100
0
125
-50
-25
0
o
50
75
100
125
Temperature (oC)
Temperature ( C)
Fig. 24 Turn-on Propagation Delay vs.
Temperature
Fig. 25. Turn-off Propagation Delay vs.
Temperature
250
Turn-Off fall Time (ns)
Turn-On Rise Time (ns)
25
200
150
100
125
100
75
50
Exp.
Exp.
50
25
0
0
-50
-25
0
25
50
75
100
o
Temperature ( C)
Fig. 26. Turn-on Rise Time vs. Temperature
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125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 27. Turn-off Rise Time vs. Temperature
19
4
4
3
3
V BSUV hysteresis (V)
VCCUV hysteresis (V)
IRS2608DSPbF
2
1
Exp.
2
1
Exp.
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
o
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 28. VCC Supply UV Hysteresis vs.
Temperature
Fig. 29. VBS Supply UV Hysteresis vs.
Temperature
100
VBS Quiescent Current (µA)
10
VCC Quiescent Current (mA)
50
8
6
4
2
Exp.
0
-50
-25
0
25
50
75
100
80
60
Exp.
40
20
0
125
-50
-25
0
o
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 30. VCC Quiescent Supply Current vs.
Temperature
Fig. 31 VBS Quiescent Supply Current vs.
Temperature
12
12
VCCUV- Threshold (V)
VCCUV+ Threshold (V)
Exp.
9
6
3
0
9
Exp.
6
3
0
-50
-25
0
25
50
75
100
o
Temperature ( C)
Fig. 32. VCCUV+ Threshold vs. Temperature
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125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 33. VCCUV- Threshold vs. Temperature
20
IRS2608DSPbF
12
12
Exp.
9
VBSUV- Threshold (V)
V BSUV+ Threshold (V)
9
6
3
Exp.
6
3
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
o
75
100
125
Temperature ( C)
Fig. 34. VBSUV+ Threshold vs. Temperature
Fig. 35 VBSUV- Threshold vs. Temperature
400
400
300
200
EXP.
100
0
-50
-25
0
25
50
75
100
125
High Level Output Voltage (mV)
Low Level Output Voltage (mV)
50
o
Temperature ( C)
300
200
Exp.
100
0
-50
-25
0
o
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 36. Low Level Output Voltage vs. Temperature
Fig. 37. High Level Output Voltage vs.
Temperature
8
500
400
LIN VTH+ (V)
Bootstrap Resistance (Ω)
25
300
200
6
4
Exp.
Exp.
2
100
0
0
-50
-25
0
25
50
75
100
o
Temperature ( C)
Fig. 38. Bootstrap Resistance vs. Temperature
www.irf.com
125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 39. LIN VTH+ vs. Temperature
21
8
8
6
6
HIN VTH+ (V)
LIN VTH- (V)
IRS2608DSPbF
4
2
4
Exp.
2
Exp.
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
o
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 40. LIN VTH- vs. Temperature
Fig. 41. HIN VTH+ vs. Temperature
8
600
500
Tbson_VccTYP(ns)
6
HIN VTH- (V)
50
4
2
Exp.
0
400
Exp.
300
200
100
0
-50
-25
0
25
50
75
Temperature (oC)
Fig. 42. HIN VTH- vs. Temperature
www.irf.com
100
125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 43. Tbson_VCCTYP vs. Temperature
22
IRS2608DSPbF
Case Outlines
www.irf.com
23
IRS2608DSPbF
Tape and Reel Details: 8L-SOIC
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
24
IRS2608DSPbF
ORDER INFORMATION
8-Lead SOIC IRS2608DSPbF
8-Lead SOIC Tape & Reel IRS2608DSTRPbF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
25
IRS2608DSPbF
Revision History
Revision Date
Comments/Changed items
1.5
03-17-08
Added application note to include negative Vs curve
1.6
03-17-08
Added Qualification Information on Page 2, Disclaimer information on Page
25, and updated information on Pages 21-23
1.7
03-21-08
Removed revision letter from JEDEC standards under Qualification Information
table.
1.8
04-18-08
Removed “Available in LEAD-FREE” from front page, replaced with “RoHS
compliant”, changed latch up level to A, Changed bootstrap turn-on at point 3
from LIN to HIN, added MT parameter into datasheet.
1.9
05-08-08
Added “Suitable for both trapezoidal and sinusoidal motor control” in page 1.
06-18-08
Corrected internal dead time on front page to 530ns instead of 540ns.
www.irf.com
26
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