Intersil EL9112IL-T7 Triple differential receiver/equalizer Datasheet

EL9111, EL9112
®
Data Sheet
May 17, 2005
FN7450.1
Triple Differential Receiver/Equalizer
Features
The EL9111 and EL9112 are triple channel differential
receivers and equalizers. They contains three high speed
differential receivers with five programmable poles. The
outputs of these pole blocks are then summed into an output
buffer. The equalization length is set with the voltage on a
single pin. The EL9111 and EL9112 also contain a 3-statable
output, enabling multiple devices to be connected in parallel
and used in a multiplexing application.
• 150MHz -3dB bandwidth
The gain can be adjusted up or down on each channel by
6dB using its VGAIN control signal. In addition, a further 6dB
of gain can be switched in to provide a matched drive into a
cable.
The EL9111 and EL9112 have a bandwidth of 150MHz and
consume just 108mA on ±5V supply. A single input voltage is
used to set the compensation levels for the required length
of cable.
The EL9111 is a special version of the EL9112 that decodes
syncs encoded onto the common modes of three pairs of
CAT-5 cable by the EL4543. (Refer to the EL4543 datasheet
for details.)
The EL9111 and EL9112 are available in a 28-pin QFN
package and are specified for operation over the full -40°C to
+85°C temperature range.
• CAT-5 compensation
- 50MHz @ 1000 ft
- 125MHz @ 500 ft
• 108mA supply current
• Differential input range 3.2V
• Common mode input range -4V to +3.5V
• ±5V supply
• Output to within 1.5V of supplies
• Available in 28-pin QFN package
• Pb-free available (RoHS compliant)
Applications
• Twisted-pair receiving/equalizer
• KVM (Keyboard/Video/Mouse)
• VGA over twisted-pair
• Security video
Pinouts
23 VCM_R
24 VCM_G
25 VCM_B
26 X2
28 0V
23 HOUT
24 VOUT
25 SYNCREF
26 X2
27 ENABLE
28 0V
27 ENABLE
EL9112
(28-PIN QFN)
TOP VIEW
EL9111
(28-PIN QFN)
TOP VIEW
VSMO_B 1
22 VSP
VSMO_B 1
22 VSP
VOUT_B 2
21 VINM_B
VOUT_B 2
21 VINM_B
VSPO_B 3
20 VINP_B
VSPO_B 3
20 VINP_B
19 VINM_G
VSPO_G 4
18 VINP_G
VOUT_G 5
VSMO_G 6
17 VINM_R
VSMO_G 6
17 VINM_R
VSMO_R 7
16 VINP_R
VSMO_R 7
16 VINP_R
VOUT_R 8
15 VSM
VOUT_R 8
15 VSM
1
19 VINM_G
VGAIN_B 14
18 VINP_G
VGAIN_G 13
VGAIN_R 12
VREF 11
THERMAL
PAD
VCTRL 10
VGAIN_B 14
VGAIN_G 13
VREF 11
VCTRL 10
VSPO_R 9
VOUT_G 5
VGAIN_R 12
THERMAL
PAD
VSPO_R 9
VSPO_G 4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL9111, EL9112
Ordering Information
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL9111IL
28-Pin QFN
-
MDP0046
EL9111IL-T7
28-Pin QFN
7”
EL9111IL-T13
28-Pin QFN
EL9111ILZ
(Note)
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL9112IL
28-Pin QFN
-
MDP0046
MDP0046
EL9112IL-T7
28-Pin QFN
7”
MDP0046
13”
MDP0046
EL9112IL-T13
28-Pin QFN
13”
MDP0046
28-Pin QFN
(Pb-Free)
-
MDP0046
EL9112ILZ
(Note)
28-Pin QFN
(Pb-Free)
-
MDP0046
EL9111ILZ-T7
(Note)
28-Pin QFN
(Pb-Free)
7”
MDP0046
EL9112ILZ-T7
(Note)
28-Pin QFN
(Pb-Free)
7”
MDP0046
EL9111ILZ-T13
(Note)
28-Pin QFN
(Pb-Free)
13”
MDP0046
EL9112ILZ-T13
(Note)
28-Pin QFN
(Pb-Free)
13”
MDP0046
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7450.1
May 17, 2005
EL9111, EL9112
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . .12V
Maximum Continuous Output Current per Channel. . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
Bandwidth
(See Figure 1)
150
MHz
SR
Slew Rate
VIN = -1V to +1V, VG = 0.39, VC = 0,
RL = 75 + 75Ω
1.5
kV/µs
THD
Total Harmonic Distortion
10MHz 2VP-P out, VG = 1V, X2 gain, VC = 0
-50
dBc
DC PERFORMANCE
V(VOUT)OS
Offset Voltage
X2 = high, no equalization
-110
-10
+78
mV
∆VOS
Channel-to-Channel Offset Matching X2 = high, no equalization
-100
0
+100
mV
INPUT CHARACTERISTICS
CMIR
Common-mode Input Range
-4/+3.5
V
ONOISE
Output Noise
VG = 0V, VC = 0V, X2 = HIGH, RLOAD = 150Ω,
Input 50Ω to GND, 10MHz
-110
dBm
CMRR
Common-mode Rejection Ratio
Measured at 10kHz
-80
dB
CMRR
Common-mode Rejection Ratio
Measured at 10MHz
-55
dB
CMBW
CM Amplifier Bandwidth
10K || 10pF load
50
MHz
CMSLEW
CM Slew Rate
Measured @ +1V to -1V
100
V/µs
CINDIFF
Differential Input Capacitance
Capacitance VINP to VINM
600
fF
RINDIFF
Differential Input Resistance
Resistance VINP to VINM
2.4
MΩ
CINCM
CM Input Capacitance
Capacitance VINP = VINM to GND
1.2
pF
RINCM
CM Input Resistance
Resistance VINP = VINM to GND
2.8
MΩ
+IIN
Positive Input Current
DC bias @ VINP = VINM = 0V
1
µA
-IIN
Negative Input Current
DC bias @ VINP = VINM = 0V
VINDIFF
Differential Input Range
VINP - VINM when slope gain falls to 0.9
1
1
2.5
1
µA
3.2
V
±3.5
V
60
mA
30
Ω
OUTPUT CHARACTERISTICS
V(VOUT)
Output Voltage Swing
RL = 150Ω
I(VOUT)
Output Drive Current
RL = 10Ω, VINP = 1V, VINM = 0V, X2 = high,
VG = 0.39
R(VCM)
CM Output Resistance of
VCM_R/G/B (EL9112 only)
at 100kHz
Gain
Gain
VC = 0, VG = 0.39, X2 = 5, RL = 150Ω
∆Gain
Channel-to-Channel Gain Matching
VC = 0, VG = 0.39, X2 = 5, RL = 150Ω
V(SYNC)HI
High Level output on V/HOUT
(EL9111 only)
3
50
0.85
V(VSP)
- 0.1V
1.0
1.1
3
6
%
V(VSP)
FN7450.1
May 17, 2005
EL9111, EL9112
Electrical Specifications
PARAMETER
V(SYNC)LO
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = 25°C, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
Low Level output on V/HOUT
(EL9111 only)
TYP
0
MAX
UNIT
V(SYNC
REF)
+ 0.1V
SUPPLY
ISON
Supply Current per Channel
VENBL = 5, VINM = 0
32
ISOFF
Supply Current per Channel
VENBL = 0, VINM = 0
0.2
PSRR
Power Supply Rejection Ratio
DC to 100kHz, ±5V supply
36
39
mA
0.4
mA
65
dB
LOGIC CONTROL PINS (ENABLE, X2)
VHI
Logic High Level
VIN - VLOGIC ref for guaranteed high level
VLOW
Logic Low Level
VIN - VLOGIC ref for guaranteed low level
0.8
V
ILOGICH
Logic High Input Current
VIN = 5V, VLOGIC = 0V
50
µA
ILOGICL
Logic Low Input Current
VIN = 0V, VLOGIC = 0V
15
µA
1.35
V
Pin Descriptions
PIN
NUMBER
EL9111IL
PIN NAME
EL9111IL
PIN FUNCTION
1
VSMO_B
-5V to blue output buffer
VSMO_B
-5V to blue output buffer
2
VOUT_B
Blue output voltage referenced to 0V pin
VOUT_B
Blue output voltage referenced to 0V pin
3
VSPO_B
+5V to blue output buffer
VSPO_B
+5V to blue output buffer
4
VSPO_G
+5V to green output buffer
VSPO_G
+5V to green output buffer
5
VOUT_G
Green output voltage referenced to 0V pin
VOUT_G
Green output voltage referenced to 0V pin
6
VSMO_G
-5V to green output buffer
VSMO_G
-5V to green output buffer
7
VSMO_R
-5V to red output buffer
VSMO_R
-5V to red output buffer
8
VOUT_R
Red output voltage referenced to 0V pin
VOUT_R
Red output voltage referenced to 0V pin
9
VSPO_R
+5V to red output buffer
VSPO_R
+5V to red output buffer
10
VCTRL
11
VREF
Equalization control voltage (0V to 1V)
Reference voltage for logic signals, VCTRL and
VGAIN pins
EL9112IL
PIN NAME
VCTRL
VREF
EL9112IL
PIN FUNCTION
Equalization control voltage (0V to 1V)
Reference voltage for logic signals, VCTRL and
VGAIN pins
12
VGAIN_R
Red channel gain voltage (0V to 1V)
VGAIN_R
Red channel gain voltage (0V to 1V)
13
VGAIN_G
Green channel gain voltage (0V to 1V)
VGAIN_G
Green channel gain voltage (0V to 1V)
14
VGAIN_B
Blue channel gain voltage (0V to 1V)
VGAIN_B
Blue channel gain voltage (0V to 1V)
15
VSM
16
VINP_R
Red positive differential input
VINP_R
Red positive differential input
17
VINM_R
Red negative differential input
VINM_R
Red negative differential input
18
VINP_G
Green positive differential input
VINP_G
Green positive differential input
19
VINM_G
Green negative differential input
VINM_G
Green negative differential input
20
VINP_B
Blue positive differential input
VINP_B
Blue positive differential input
21
VINM_B
Blue negative differential input
VINM_B
Blue negative differential input
22
VSP
23
HOUT
-5V to core of chip
+5V to core of chip
VSM
VSP
-5V to core of chip
+5V to core of chip
Decoded Horizontal sync referenced to
SYNCREF
VCM_R
Red common-mode voltage at inputs
24
VOUT
Decoded Vertical sync referenced to SYNCREF
VCM_G
Green common-mode voltage at inputs
25
SYNCREF
Reference level for HOUT and VOUT logic outputs
VCM_B
Blue common-mode voltage at inputs
4
FN7450.1
May 17, 2005
EL9111, EL9112
Pin Descriptions
PIN
NUMBER
EL9111IL
PIN NAME
26
X2
27
ENABLE
28
0V
(Continued)
EL9111IL
PIN FUNCTION
Logic signal for x1/x2 output gain setting
Chip enable logic signal
0V reference for output voltage
EL9112IL
PIN NAME
X2
ENABLE
0V
EL9112IL
PIN FUNCTION
Logic signal for x1/x2 output gain setting
Chip enable logic signal
0V reference for output voltage
Typical Performance Curves
5
GAIN (dB)
X2=LOW
VGAIN=0V
3 VCTRL=0V
RLOAD=150Ω
1
-1
-3
-5
1M
10M
100M 200M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE OF ALL CHANNELS
FIGURE 2. GAIN vs FREQUENCY ALL CHANNELS
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS VCTRL
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS VCTRL &
VGAIN
5
FN7450.1
May 17, 2005
EL9111, EL9112
Typical Performance Curves (Continued)
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS VCTRL &
CABLE LENGTHS
FIGURE 6. CHANNEL MISMATCH
FIGURE 7. GROUP DELAY vs FREQUENCY FOR VARIOUS
VCTRL
FIGURE 8. OUTPUT NOISE
FIGURE 9. OFFSET vs VCTRL
FIGURE 10. DC GAIN vs VGAIN
6
FN7450.1
May 17, 2005
EL9111, EL9112
Typical Performance Curves (Continued)
-10
4
VGAIN=0.35V
(ALL CHANNELS)
2 VCTRL=0V
RLOAD=150Ω
X2=HIGH
GAIN (dB)
CMRR (dB)
VGAIN=0.35V
(ALL CHANNELS)
-20 VCTRL=0V
X2=HIGH
-40
-60
-80
0
-2
-4
-100
100K
1M
10M
-6
100K
100M
1M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
FIGURE 11. COMMON-MODE REJECTION
FIGURE 12. CM AMPLIFIER BANDWIDTH
0
-20
VEE=-5V
VCTRL=0V
-40 VGAIN=0V
(ALL CHANNELS)
INPUTS ON GND
-PSRR (dB)
VCC=5V
VCTRL=0V
-20 VGAIN=0V
(ALL CHANNELS)
INPUTS ON GND
+PSRR (dB)
10M
-40
-60
-80
-60
-80
-100
-100
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
100M
-120
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 13. (+)PSRR vs FREQUENCY
FIGURE 14. (-)PSRR vs FREQUENCY
FIGURE 15. BLUE CROSSTALK
FIGURE 16. BLUE CROSSTALK
7
100M
FN7450.1
May 17, 2005
EL9111, EL9112
Typical Performance Curves (Continued)
FIGURE 17. GREEN CROSSTALK
FIGURE 18. GREEN CROSSTALK
FIGURE 19. RED CROSSTALK
FIGURE 20. RED CROSSTALK
FIGURE 21. RISE TIME AND FALL TIME
8
FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE
LENGTHS
FN7450.1
May 17, 2005
EL9111, EL9112
Typical Performance Curves (Continued)
POWER DISSIPATION (W)
1.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
893mW
0.8
θ
JA =
0.6
QF
N2
14
8
0°
C/
W
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 23. TOTAL HARMONIC DISTORTION
4.5
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
POWER DISSIPATION (W)
4
3.5 3.378W
3
θ
JA
2.5
2
QF
N
=3 28
7°
C/
W
1.5
1
0.5
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
9
FN7450.1
May 17, 2005
EL9111, EL9112
Applications Information
Logic Control
The EL9112 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip will run from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case the logic
reference voltage should be tied to the 0V supply. If the logic
is referenced to the -5V rail, then the logic reference should
be connected to -5V. The logic reference pin sources about
60µA and this will rise to about 200µA if all inputs are true
(positive).
The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs
sink a current dependent on the high level, up to 50µA for a
high level 5V above the reference level.
The logic inputs, if not used, should be tied to the
appropriate voltage in order to define their state.
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range 0V 1V, which are referenced to the control reference pin. It is
expected that the control reference pin will be tied to 0V and
the control voltage will vary from 0V to 1V. It is; however,
acceptable to connect the control reference to any potential
between -5V and 0V to which the control voltages are
referenced.
performance twisted pair cables based on 24awg copper
wire (CAT-5 etc.) these parameters vary only a little between
cable types, and in general cables exhibit the same
frequency dependence of loss. (The lower loss cables can
be compared with somewhat longer lengths of their more
lossy brothers.) This enables a single equalizing law
equation to be built into the EL9112.
With a control voltage applied between pins VCTRL and
VREF, the frequency dependence of the equalization is
shown in Figure 8. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise becomes an increasing issue as
the equalization increases.
Contrast
By varying the voltage between pins VGAIN and VREF, the
gain of the signal path can be changed in the ratio 4:1. The
gain change varies almost linearly with control voltage. For
normal operation it is anticipated the X2 mode will be
selected and the output load will be back matched. A unity
gain to the output load will then be achieved with a gain
control voltage of about 0.35V. This allows the gain to be
trimmed up or down by 6dB to compensate for any gain/loss
errors that affect the contrast of the video signal. Figure 26
shows an example plot of the gain to the load with gain
control voltage.
2
The control voltage pins themselves are high impedance.
The control reference pin will source between 0µA and
200µA depending on the control voltages being applied.
Equalizing
When transmitting a signal across a twisted pair cable, it is
found that the high frequency (above 1MHz) information is
attenuated more significantly than the information at low
frequencies. The attenuation is predominantly due to
resistive skin effect losses and has a loss curve which
depends on the resistivity of the conductor, surface condition
of the wire and the wire diameter. For the range of high
10
1.6
GAIN (V)
The control reference and logic reference effectively remove
the necessity for the 0V rail and operation from ±5V (or 0V
and 10V) only is possible. However we still need a further
reference to define the 0V level of the single ended output
signal. The reference for the output signal is provided by the
0V pin. The output stage cannot pull fully up or down to
either supply so it is important that the reference is
positioned to allow full output swing. The 0V reference
should be tied to a 'quiet ground' as any noise on this pin is
transferred directly to the output. The 0V pin is a high
impedance pin and draws dc bias currents of a few µA and
similar levels of AC current.
1.8
1.4
1.2
1
0.8
0.6
0.4
0
0.2
0.4
0.6
0.8
1
VGAIN
FIGURE 26. VARIATION OF GAIN WITH GAIN CONTROL
VOLTAGE
Common Mode Sync Decoding
The EL9111 features common mode decoding to allow
horizontal and vertical synchronization information, which
has been encoded on the three differential inputs by the
EL4543, to be decoded. The entire RGB video signal can
therefore be transmitted, along with the associated
synchronization information, by using just three twisted
pairs.
FN7450.1
May 17, 2005
EL9111, EL9112
Decoding is based on the EL4543 encoding scheme, as
described in Figure 27 and Table 1. The scheme is a threelevel system, which has been designed such that the sum of
the common mode voltages results in a fixed average DC
level with no AC content. This eliminates the effect of EMI
radiation into the common mode signals along the twisted
pairs of the cable
The common mode voltages are initially extracted by the
EL9111 from the three input pairs. These are then passed to
an internal logic decoding block to provide Horizontal and
Vertical sync output signals (HOUT and VOUT).
VOLTAGE
(0.5V/DIV)
BLUE CM
OUT (CH A)
GREEN CM
OUT (CH B)
RED CM
OUT (CH C)
VOLTAGE
(2.5V/DIV)
VSYNC
HSYNC
TIME (0.5ms/DIV)
FIGURE 27. H & V SYNCS ENCODED
TABLE 1. H AND V SYNC DECODING
RED CM
GREEN CM
BLUE CM
HSYNC
VSYNC
Mid
High
Low
Low
Low
High
Low
Mid
Low
High
Low
High
Mid
High
Low
Mid
Low
High
High
High
NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’
11
FN7450.1
May 17, 2005
EL9111, EL9112
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN7450.1
May 17, 2005
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