AVAGO ACPM-7353-TR1G Cdma dual band 4x5 power amplifier module (cellular/pcs) Datasheet

ACPM-7353
CDMA Dual Band 4x5 Power Amplifier Module
(Cellular/PCS)
Data Sheet
Description
Features
The ACPM-7353 is a dual-band PAM (Power Amplifier
Module) designed for CDMA (code division multiple
access) cellular and PCS. The ACPM-7353 meets stringent
CDMA linearity requirements to and beyond 28dBm
output power in both bands. The 4mmx5mm form factor
14-pin surface mount package is self contained, incorporating 50ohm input and output matching networks
• Dual-Band PA (Cellular and PCS)
The ACPM-7353 features 5th generation of CoolPAM circuit
technology which supports 3 modes – bypass, mid and
high power modes. The CoolPAM is stage bypass technology which enables power amplifier to lower power consumption. Active bypass feature is added to 5th generation
to enhance power added efficiency at low output range
and this technology extends talk time of mobiles more by
further saving power amplifier’s current consumption.
• High Efficiency at max output power
The power amplifier is manufactured on an advanced
InGaP HBT (hetero-junction Bipolar Transistor) MMIC
(microwave monolithic integrated circuit) technology
offering state-of-the-art reliability, temperature stability
and ruggedness
• Digital CDMA Cellular and PCS Dual Band
The Module is housed in a cost effective, small and thin
4x5mm package.
Component Image
• Small Size (4x5mm)
• Thin Package (0.9mm typ)
• Excellent Linearity
• 3-mode power control
Bypass / Mid Power Mode / High Power Mode
• 14-pin surface mounting package
• Internal 50ohm matching networks for both RF input
and output
• Lead-free, RoHS compliant, Green
Applications
Ordering Information
Part Number
Number of Devices
Container
ACPM-7353-TR1G
1000
178mm (7”)
Tape/Reel
ACPM-7353-BLK
100
Bulk
Functional Block Diagram
Absolute Maximum Ratings
No damage assuming only one parameter is set at limit at a time with all other parameters set at or below typical value
Operation of any single parameter outside these conditions with the remaining parameters set at or below typical values
may result in permanent damage.
Description
Min
RF Input Power (high power mode)
Output power (bypass mode, Cell & PCS)
Output power in mid power mode (Cell)
Output power in mid power mode (PCS)
Typ
Max
Unit
Associated Pins
0
10
11
16
18
dBm
RFIn_Cell, RFIn_PCS
RFOut_Cell, RFOut_PCS
RFOut_Cell
RFOut_PCS
DC Supply Voltage
0
3.4
5.0
V
Vcc1, Vcc2
Enable Voltage
0
2.6
3.3
V
Ven
Mode Control Voltage
0
2.6
3.3
V
Vmode
Bypass Control
0
2.6
3.3
V
Vbp
Storage Temperature
-55
25
+125
°C
Recommended Operating Condition
Description
Min
Typ
Max
Unit
DC Supply Voltage
3.2
3.4
4.2
V
Enable Voltage (Ven)
LOW
HIGH
0
1.35
0
2.6
0.5
2.9
V
V
Mode Control Voltage (Vmode)
LOW
HIGH
0
1.35
0
2.6
0.5
2.9
V
V
Bypass Control Voltage (Vbp)
LOW
HIGH
0
1.35
0
2.6
0.5
2.9
V
V
849
1910
MHz
MHz
85
°C
Operating Frequency
Cellular
PCS
824
1850
Ambient Temperature
-30
2
25
Operating Logic Table
Power Mode
Ven
Vbp
Vmode
Cellular Pout
PCS Pout
High Power Mode
HIGH
HIGH
LOW
~28dBm
~28dBm
Mid Power Mode
HIGH
HIGH
HIGH
~16dBm
~18dBm
Bypass Mode
HIGH
LOW
–
~11dBm
~11dBm
Shut Down Mode
LOW
LOW
LOW
–
–
Electrical Characteristics in Cellular Band
- Conditions: Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm
Characteristics
Condition
Min
Typ
Max
Unit
824
–
849
MHz
High Power Mode, Pout=28 dBm
24
27.5
dB
Mid Power Mode, Pout=16 dBm
14
17.5
dB
Bypass Power Mode, Pout=11dBm
8.5
12
dB
High Power Mode, Pout=28 dBm
35.3
38.2
%
Mid Power Mode, Pout=16 dBm
12.8
16.7
%
Bypass Power Mode, Pout=11dBm
8.0
12.0
%
Operating Frequency Range
Gain
Power Added Efficiency
Total Supply Current
Quiescent Current
High Power Mode, Pout=28 dBm
485
525
mA
Mid Power Mode, Pout=16 dBm
69
90
mA
Bypass Power Mode, Pout=11dBm
29
43
mA
High Power Mode
68
91
115
mA
Mid Power Mode
11
23
33
mA
Bypass Mode
1
3
5
mA
Enable Current
100
uA
Mode Control Current
100
uA
Bypass Control Current
100
uA
Total Current in Power-down mode
Ven=0V, Vmode=0V, Vbp=0V
0.2
5
µA
Adjacent Channel
Power Ratio
900 kHz offset
1.98 MHz offset
High Power Mode, Pout=28 dBm
-48
-59
-46
-56
dBc
dBc
900 kHz offset
1.98 MHz offset
Mid Power Mode, Pout=16 dBm
-52
-68
-46
-57
dBc
dBc
900 kHz offset
1.98 MHz offset
Bypass Mode, Pout=11dBm
-58
-68
-46
-57
dBc
dBc
Second
Third
High Power Mode, Pout=28 dBm
-30
-40
dBc
dBc
Harmonic
Suppression
Input VSWR
Stability (Spurious Output)
2:1
In-Band Load VSWR <= 5:1, All Phase
Out of Band Load VSWR <= 10:1,
All Phase
Forwarded power fixed
Noise Power in Rx Band
Ruggedness
3
-136
No Damage
Pout<28dBm, Pin<10dBm, All phase
High Power Mode
2.5:1
-60
dBc
-132
dBm/Hz
10:1
VSWR
Electrical Characteristics in PCS Band
- Conditions: Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm
Characteristics
Condition
Min.
Typ.
Max.
Unit
1850
–
1910
MHz
High Power Mode, Pout=28 dBm
23
26
dB
Mid Power Mode, Pout=18 dBm
13
16.5
dB
Bypass Power Mode, Pout=11dBm
6.5
10.5
dB
High Power Mode, Pout=28 dBm
35.3
38.2
%
Mid Power Mode, Pout=18 dBm
15.1
19.1
%
Bypass Power Mode, Pout=11dBm
7.6
10.6
%
Operating Frequency Range
Gain
Power Added Efficiency
Total Supply Current
Quiescent Current
High Power Mode, Pout=28 dBm
485
535
mA
Mid Power Mode, Pout=18 dBm
95
120
mA
Bypass Power Mode, Pout=11dBm
32
45
mA
High Power Mode
80
105
125
mA
Mid Power Mode
18
28
38
mA
Bypass Mode
1
3
5
mA
Enable Current
100
uA
Mode Control Current
100
uA
Bypass Control Current
100
uA
0.2
5
µA
1.25 MHz offset High Power Mode, Pout=28 dBm
1.98 MHz offset
-48
-56
-46
-53
dBc
dBc
1.25 MHz offset Mid Power Mode, Pout=18 dBm
1.98 MHz offset
-56
-63
-46
-53
dBc
dBc
1.25 MHz offset Bypass Mode, Pout=11 dBm
1.98 MHz offset
-54
-66
-46
-53
dBc
dBc
-30
-40
dBc
dBc
Total Current in Power-down mode
Adjacent Channel
Power Ratio
Harmonic Suppression
Second
Third
Ven=0V, Vmode=0V, Vbp=0V
High Power Mode, Pout=28 dBm
Input VSWR
Stability (Spurious Output)
2:1
In-Band Load VSWR <= 5:1, All Phase
Out of Band Load VSWR <= 10:1,
All Phase
Forwarded power fixed
Noise Power in Rx Band
Ruggedness
4
-138.5
No Damage
Pout<28dBm, Pin<10dBm, All phase
High Power Mode
2.5:1
-60
dBc
-133
dBm/Hz
10:1
VSWR
Characteristics Data of Cell Band
500
450
400
350
300
250
200
150
100
50
0
Current (Cell Band)
824MHz
837MHz
849MHz
20
0
5
10
15
Pout (dBm)
20
25
ACPR1 (Cell Band)
0
5
10
15
Pout (dBm)
20
25
30
824MHz
837MHz
849MHz
-50
25
30
ACPR2 (Cell Band)
-50
824MHz
849MHz
894MHz
-55
ACPR2 (dBc)
ACPR1 (dBc)
0
30
-55
-60
-65
-60
-65
-70
-75
0
5
10
15
Pout (dBm)
20
25
30
Adjacent Channel Power Ratio 1 vs. Output Power
35
824MHz
837MHz
849MHz
30
25
20
15
10
5
0
5
10
15
Pout (dBm)
Power Added Efficiency vs. Output Power
20
-80
0
5
10
15
Pout (dBm)
20
Adjacent Channel Power Ratio 2 vs. Output Power
PAE (Cell Band)
40
PAE (%)
10
Gain vs. Output Power
-45
5
15
5
-40
0
824MHz
849MHz
894MHz
25
Total Current vs. Output Power
-70
Gain (Cell Band)
30
Gain (dB)
Current (mA)
(Vcc=3.4V, Ven=2.6, Vbp, Vmode= 0V or 2.6V, T=25°C, Zin/Zout=50ohm, IS-95 RL)
25
30
Characteristics Data of PCS Band
500
450
400
350
300
250
200
150
100
50
0
Current (PCS Band)
1.85GHz
1.88GHz
1.91GHz
20
15
10
5
0
5
10
15
Pout (dBm)
20
25
10
15
Pout (dBm)
20
25
30
25
30
ACPR2 (PCS Band)
1.85GHz
1.88GHz
1.91GHz
-55
-55
-60
-65
-60
-65
-70
-75
0
5
10
15
Pout (dBm)
20
25
30
Adjacent Channel Power Ratio 1 vs. Output Power
35
1.85GHz
1.88GHz
1.91GHz
30
25
20
15
10
5
0
5
10
15
Pout (dBm)
Power Added Efficiency vs. Output Power
20
-80
0
5
10
15
Pout (dBm)
Adjacent Channel Power Ratio 2 vs. Output Power
PAE (PCS Band)
40
PAE (%)
5
-50
ACPR2 (dBc)
ACPR1 (dBc)
-50
0
Gain vs. Output Power
1.85GHz
1.88GHz
1.91GHz
-45
6
0
30
ACPR1 (PCS Band)
-40
0
1.85GHz
1.88GHz
1.91GHz
25
Total Current vs. Output Power
-70
Gain (PCS Band)
30
Gain (dB)
Current (mA)
(Vcc=3.4V, Ven=2.6, Vbp, Vmode= 0V or 2.6V, T=25°C, Zin/Zout=50ohm, IS-95 RL)
25
30
20
Footprint
X-RAY TOP VIEW
All dimensions are in millimeters
PIN DESCRIPTIONS
Pin #
Name
Description
1
RFIn_Cell
Cellular Band RF Input
2
Vmode
Mode Control
3
Vbp
Bypass Control
4
Vcc1
Supply Voltage
5
Ven_Cell
Cellular Band PA Enable
6
Ven_PCS
PCS Band PA Enable
7
RFIn_PCS
PCS Band RF Input
8
RFOut_PCS
PCS Band RF Output
9
GND
Ground
10
GND
Ground
11
Vcc2
Supply Voltage
12
GND
Ground
13
GND
Ground
14
RFOut_Cell
Cellular Band RF Output
7
Package Dimensions
0.6
Pin 1 Mark
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4 ± 0.1
5 ± 0.1
0.9 ± 0.1
All dimensions are in millimeters
Marking Specification
Pin 1 Mark
AVAGO
ACPM-7353
Manufacturing Part Number
PYYWW
Lot Number
P
Manufacturing info
YY
Manufacturing Year
WW
Work Week
A A A A A Assembly Lot Number
AAAAA
8
Metallization
PCB Design Guidelines
The recommended PCB land pattern is shown in figures
on the left side. The substrate is coated with solder mask
between the I/O and conductive paddle to protect the
gold pads from short circuit that is caused by solder
bleeding/bridging.
0.50
0.60
0.40
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads.
0.73
0.33
0.25
Φ 0.3 Via
on 0.6 pitch
Solder Mask Opening
0.55
0.70
0.50
2.30
0.73
2.40
Solder Paste Stencil Aperture
0.50
0.60
0.40
2.10
0.73
2.00
9
The recommended stencil layout is shown here. Reducing
the stencil opening can potentially generate more voids.
On the other hand, stencil openings larger than 100% will
lead to excessive solder paste smear or bridging across
the I/O pads or conductive paddle to adjacent I/O pads.
Considering the fact that solder paste thickness will
directly affect the quality of the solder joint, a good choice
is to use laser cut stencil composed of 0.100mm(4mils) or
0.127mm(5mils) thick stainless steel which is capable of
producing the required fine stencil outline.
Evaluation Board Schematic
RF In Cell
1 RFIn_Cell
Vmode
Vbp
C6
100 pF
Vcc1
C5
100 pF
C4
Ven_Cell 2.2uF
Ven_PCS
RF In PCS
C3
1000 pF
C2
100 pF
C1
100 pF
Evaluation Board Description
10
RFOut_Cell 14
2 Vmode
GND 13
3 Vbp
GND 12
4 Vcc1
Vcc2 11
5 Ven_Cell
GND 10
6 Ven_PCS
GND 9
Vcc2
C7
1000 pF
C8
2.2uF
RF Out PCS
7 RFIn_PCS
RFOut_PCS 8
Tape and Reel Information
ACPM-7353
PYYWW
AAAAA
Dimension List
Millimeter
Annote
Millimeter
A0
4.40±0.10
P2
2.00±0.05
B0
5.30±0.10
P10
40.00±0.20
K0
1.20±0.10
E
1.75±0.10
D0
1.55±0.05
F
5.50±0.05
D1
1.60±0.10
W
12.00±0.30
P0
4.00±0.10
T
0.30±0.05
Annote
Tape and Reel Format – 4 mm x 5 mm
11
Reel Drawing
BACK VIEW
Shading indicates
thru slots
18.4 max.
178 +0.4
-0.2
50 min.
25
min wide (ref)
Slot for carrier tape
insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
-0.0
FRONT VIEW
1.5 min.
13.0 ± 0.2
21.0 ± 0.8
12
NOTES:
1. Reel shall be labeled with the following
information (as a minimum).
a. manufacturers name or symbol
b. Avago Technologies part number
c. purchase order number
d. date code
e. quantity of units
2. A certificate of compliance (c of c) shall
be issued and accompany each shipment
of product.
3. Reel must not be made with or contain
ozone depleting materials.
4. All dimensions in millimeters (mm)
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of
neutralization or discharge will be sought. If the acquired
discharge route is through a semiconductor device, destructive damage will result.
ESD countermeasure methods should be developed and
used to control potential ESD damage during handling in
a factory environment at each manufacturing site.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sensitive to
damage induced by absorbed moisture and temperature.
Avago Technologies follows JEDEC Standard J-STD 020B.
Each component and package type is classified for
moisture sensitivity by soaking a known dry package at
various temperatures and relative humidity, and times.
After soak, the components are subjected to three consecutive simulated reflows.
The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to the
JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033.
ACPM-7353 is MSL3. Thus, according to the J-STD-033
p.10, the maximum Manufacturers Exposure Time (MET)
for this part is 168 hours. After this time period, the part
would need to be removed from the reel, de-taped and
then re-baked. MSL classification reflow temperature for
the ACPM-7353 is targeted at 260°C +0/-5°C. Figure and
table on next page show typical SMT profile for maximum
temperature of 260 +0/-5°C.
Moisture Classification Level and Floor Life
MSL Level
Floor Life (out of bag) at factory ambient =< 30°C/60% RH or as stated
1
Unlimited at =< 30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note :
1. The MSL Level is marked on the MSL Label on each shipping bag.
13
Reflow Profile Recommendations
tp
Tp
Critical Zone
T L to Tp
Temperature
Ramp-up
TL
tL
Ts max
Ts min
Ramp-down
ts
Preheat
25
t 25oC to Peak
Time
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/ -5°C
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average ramp-up rate (TL to TP)
3°C/sec max
3°C/sec max
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 sec
150°C
200°C
60-120 sec
Tsmax to TL
- Ramp-up Rate
3°C/sec max
Time maintained above:
- Temperature (TL)
- Time (TL)
183°C
60-150 sec
217°C
60-150 sec
Peak temperature (Tp)
240 +0/-5°C
260 +0/-5°C
Time within 5°C of actual Peak Temperature (tp)
10-30 sec
20-40 sec
Ramp-down Rate
6°C/sec max
6°C/sec max
Time 25°C to Peak Temperature
6 min max.
8 min max.
14
Storage Condition
Baking of Populated Boards
Packages described in this document must be stored
in sealed moisture barrier, antistatic bags. Shelf life in a
sealed moisture barrier bag is 12 months at <40°C and
90% relative humidity (RH) J-STD-033 p.6.
Some SMD packages and board materials are not able to
withstand long duration bakes at 125°C. Examples of this
are some FR-4 materials, which cannot withstand a 24 hr
bake at 125°C. Batteries and electrolytic capacitors are
also temperature sensitive. With component and board
temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the
appropriate bake duration based on the component to
be removed. For additional considerations see IPC-7711
andIPC-7721.
Out-of-Bag Time Duration
After unpacking the device must be soldered to the PCB
within 168 hours with factory conditions <30°C and 60%
RH as listed in the Table 5-1 on the J-STD-020D p.6.
Baking
It is not necessary to re-bake the part if both conditions
(storage conditions and out-of bag conditions) have been
satisfied. Baking must be done if at least one of the conditions above has not been satisfied. The baking conditions
are listed in the Table 4-1 on the J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the
temperature described above. If out-of-bag exposure
time is exceeded, parts must be baked for a longer time
at low temperatures, or the parts must be de-reeled,
de-taped, re-baked and then put back on tape and reel.
(See moisture sensitive warning label on each shipping
bag for information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount
component on the board not exceed 200°C. This method
will minimize moisture related component damage. If any
component temperature exceeds 200°C, the board must
be baked dry per 4-2 prior to rework and/or component
removal. Component temperatures shall be measured at
the top center of the package body. Any SMD packages
that have not exceeded their floor life can be exposed to
a maximum body temperature as high as their specified
maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements may cause moisture/
reflow damage that could hinder or completely prevent
the determination of the original failure mechanism.
15
Derating due to Factory Environmental Conditions
Factory floor life exposures for SMD packages removed
from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling
approach is to expose the SMD packages only up to
the maximum time limits for each moisture sensitivity
level as shown in table of Moisture Classification Level
and Floor Life. This approach, however, does not work if
the factory humidity or temperature is greater than the
testing conditions of 30°C/60% RH. A solution for addressing this problem is to derate the exposure times based on
the knowledge of moisture diffusion in the component
package materials ref. JESD22-A120). Recommended
equivalent total floor life exposures can be estimated for
a range of humidities and temperatures based on the
nominal plastic thickness for each device.
Table on follwoing page lists equivalent derated floor lives
for humidities ranging from 20-90% RH for three temperature, 20°C, 25°C, and 30°C.
This table is applicable to SMDs molded with novolac,
biphenyl or multifunctional epoxy mold compounds.
The following assumptions were used in calculating this
table:
1. Activation Energy for diffusion = 0.35eV (smallest
known value).
2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT)
mm2/s (this used smallest known Diffusivity @ 30°C).
3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT)
mm2/s (this used largest known Diffusivity @ 30°C).
Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C, 35°C
For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was
classified) Maximum Percent Relative Humidity
Maximum Percent Relative Humidity
Package Type and
Body Thickness
Moisture
Sensitivity Level
5%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Body Thickness ≥3.1 mm
Including
PQFPs >84 pin,
PLCCs (square)
All MQFPs
or
All BGAs ≥1 mm
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
94
124
167
231
44
60
78
103
32
41
53
69
26
33
42
57
16
28
36
47
7
10
14
19
5
7
10
13
4
6
8
10
35°C
30°C
25°C
20°C
Level 3
∞
∞
∞
∞
∞
∞
∞
∞
8
10
13
17
7
9
11
14
6
8
10
13
6
7
9
12
6
7
9
12
4
5
7
10
3
4
6
8
3
4
5
7
35°C
30°C
25°C
20°C
Level 4
∞
∞
∞
∞
3
5
6
8
3
4
5
7
3
4
5
7
2
4
5
7
2
3
5
7
2
3
4
6
2
3
3
5
1
2
3
4
1
2
3
4
35°C
30°C
25°C
20°C
Level 5
∞
∞
∞
∞
2
4
5
7
2
3
5
7
2
3
4
6
2
2
4
5
1
2
3
5
1
2
3
4
1
2
2
3
1
1
2
3
1
1
2
3
35°C
30°C
25°C
20°C
Level 5a
∞
∞
∞
∞
1
2
3
5
1
1
2
4
1
1
2
3
1
1
2
3
1
1
2
3
1
1
2
2
1
1
1
2
1
1
1
2
1
1
1
2
35°C
30°C
25°C
20°C
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
58
86
148
∞
30
39
51
69
22
28
37
49
3
4
6
8
2
3
4
5
1
2
3
4
35°C
30°C
25°C
20°C
Level 3
∞
∞
∞
∞
∞
∞
∞
∞
12
19
25
32
9
12
15
19
7
9
12
15
6
8
10
13
5
7
9
12
2
3
5
7
2
2
3
5
1
2
3
4
35°C
30°C
25°C
20°C
Level 4
∞
∞
∞
∞
5
7
9
11
4
5
7
9
3
4
5
7
3
4
5
6
2
3
4
6
2
3
4
5
1
2
3
4
1
2
2
3
1
1
2
3
35°C
30°C
25°C
20°C
Level 5
∞
∞
∞
∞
3
4
5
6
2
3
4
5
2
3
3
5
2
2
3
4
2
2
3
4
1
2
3
4
1
1
2
3
1
1
1
3
1
1
1
2
35°C
30°C
25°C
20°C
Level 5a
∞
∞
∞
∞
1
2
2
3
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
0.5
0.5
1
2
0.5
0.5
1
1
35°C
30°C
25°C
20°C
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
17
28
∞
∞
1
1
2
2
0.5
1
1
2
0.5
1
1
1
35°C
30°C
25°C
20°C
Level 3
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
8
11
14
20
5
7
10
13
1
1
2
2
0.5
1
1
2
0.5
1
1
1
35°C
30°C
25°C
20°C
Level 4
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
7
9
12
17
4
5
7
9
3
4
5
7
2
3
4
6
1
1
2
2
0.5
1
1
2
0.5
1
1
1
35°C
30°C
25°C
20°C
Level 5
∞
∞
∞
∞
∞
∞
∞
∞
7
13
18
26
3
5
6
8
2
3
4
6
2
2
3
5
1
2
3
4
1
1
2
2
0.5
1
1
2
0.5
1
1
1
35°C
30°C
25°C
20°C
Level 5a
∞
∞
∞
∞
7
10
13
18
2
3
5
6
1
2
3
4
1
1
2
3
1
1
2
2
1
1
2
2
1
1
1
2
0.5
1
1
2
0.5
0.5
1
1
35°C
30°C
25°C
20°C
Body 2.1 mm ≤ Thickness
<3.1 mm including
PLCCs (rectangular)
18-32 pin
SOICs (wide body)
SOICs ≥20 pins,
PQFPs ≤80 pins
Body Thickness <2.1 mm
including
SOICs <18 pin
All TQFPs, TSOPs
or
All BGAs <1 mm body
thickness
16
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved.
AV02-1611EN - October 20, 2008
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