Eorex EM44DM0888LBA Jedec standard vdd/vddq Datasheet

EM44DM0888LBA
Revision History
Revision 0.1 (Feb. 2011)
-First release.
Revision 0.2 (Jan.2013)
-Add speed 1066.
Feb. 2012
1/29
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EM44DM0888LBA
1Gb (16M×8Bank×8) Double DATA RATE 2 SDRAM
Features
Description
• JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
• All inputs and outputs are compatible with SSTL_18
interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS
• Bust length: 4 and 8.
• Programmable CAS Latency (CL): 6 & 7
• Programmable Additive Latency (AL): 0, 1, 2, 3, 4,
5 & 6.
• Write Latency (WL) =Read Latency (RL) -1.
• Read Data Strobe (RDQS) supported
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available.
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination (ODT)
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• 7.8us at average periodic refresh interval
• RoHS Compliance
• tRAS lockout supported
• High Temperature Self-Refresh rate enable
The EM44DM0888LBA is a high speed Double Date
Feb. 2012
2/29
Rate 2 (DDR2) Synchronous DRAM fabricated with
ultra high performance CMOS process containing
1,073,741,824 bits which organized as 16Mbits x 8
banks by 8 bits. This synchronous device achieves
high speed double-data-rate transfer rates of up to
1066 MT/sec (DDR2-1066) for general applications.
The chip is designed to comply with the following key
DDR2 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
(3) Off-Chip Driver (OCD) impedance adjustment and
On Die Termination (4) normal and weak strength
data output driver. All of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and /CK
falling). All I/Os are synchronized with a pair of
bidirectional strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 1Gb DDR2
devices operates with a single power supply: 1.8V ±
0.1V VDD and VDDQ. Available package:
FBGA-60Ball (with 0.8mm x 0.8mm ball pitch)
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EM44DM0888LBA
Ordering Information
Organization Max. Freq
Part No
Package
Grade
Pb
EM44DM0888LBA-25F
128M X 8
tCK6: DDR2-800
6-6-6
FBGA-60B
Commercial
Free
EM44DM0888LBA-187F
128M X 8
tCK7: DDR2-1066 7-7-7
FBGA-60B
Commercial
Free
Note: Speed ( tCK *) is in order of CL-tRCD-tRP
Parts Naming Rule
* EOREX reserves the right to change products or specification without notice.
Feb. 2012
3/29
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EM44DM0888LBA
Pin Assignment: Top View
1
2
3
7
8
9
VDD
NU/ RDQS
VSS
A
VSSQ
DQS
VDDQ
DQ6
VSSQ
DM/RDQS
B
DQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
C
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
D
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
E
VSSDL
CK
VDD
CKE
WE
F
RAS
CK
ODT
BA0
BA1
G
CAS
CS
A10
A1
H
A2
A0
A3
A5
J
A6
A4
A7
A9
K
A11
A8
A12
NC
L
NC
A13
BA2
VSS
VDD
VDD
VSS
60Ball FBGA
Note: VDDL and VSSDL are power and ground for the DLL.
Feb. 2012
4/29
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EM44DM0888LBA
Pin Description (Simplified)
Pin
Name
Function
(System Clock)
E8,F8
CK,/CK
CK and CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and
negative edge of CK. Output (read) data is referenced to the crossings
of CK and CK (both directions of crossing).
(Chip Select)
G8
/CS
All commands are masked when CS is registered HIGH. CS provides
for external Rank selection on systems with multiple Ranks. CS is
considered part of the command code.
(Clock Enable)
F2
CKE
CKE high activates and CKE low deactivates internal clock signals and
device input buffers and output drivers. Taking CKE low provides
Precharge Power-Down and Self- Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for Self-Refresh entry. CKE is
asynchronous for Self-Refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, /CK,
ODT and CKE are disabled during Power Down. Input buffers,
excluding CKE are disabled during Self-Refresh.
(Address)
H8,H3,H7,J2,
J8,J3,J7,K2,
K8,K3,H2,K7,
A0~A13
L2,L8
Provided the row address (RA0 – RA13) for Active commands and the
column address (CA0-CA9) and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA0, BA1 & BA2. The address inputs also provide the
op-code during Mode Register Set commands.
(Bank Address)
G2,G3,G1
BA0, BA1,BA2
BA0 – BA2 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode
register or extended mode register is to be accessed during a MRS or
EMRS cycle.
(On Die Termination)
F9
ODT
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is applied to each DQ,
UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will
be ignored if the Extended Mode Register (EMRS(1)) is programmed
to disable ODT.
(Command Inputs)
F7, G7, F3
Feb. 2012
/RAS,/CAS,/WE
/RAS, /CAS and /WE (along with /CS) define the command being
entered.
5/29
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EM44DM0888LBA
Pin Description (Continued)
B3,A2,B7,A8
RDQS,/RDQS
, DQS,/DQS
B3
DM
C8,C2,D7,D3,
D1,D9,B1,B9
DQ0~7
A1,L1,E9,H9/
A3,E3,J1,K9
VDD/VSS
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading. DM is
enabled by EMRS command.
(Data Input/Output)
Data inputs and outputs are on the same pin.
(Power Supply/Ground)
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
A9,C1,C3,C7,
C9/A7,B2,B8,
D2,D8
VDDQ/VSSQ
E1/E7
VDDL/VSSDL
E2
VREF
L3,L7
NC
Feb. 2012
(Data Strobe)
Output with read data, input with write data. Edge-aligned with read
data, centered in write data. An RDQS option using DM pin can be
enabled via the EMRS(1) to simplify read timing.
The data strobes DQS and RDQS may be used in single ended mode
or paired with optional complimentary signals /DQS and /RDQS to
provide differential pair signaling to the system during both reads and
writes. An EMRS(1) control bit enables or disables all complementary
data strobe signals.
(Data Mask)
VDDQ and VSSQ are power supply for the output buffers.
(DLL Power Supply/DLL Ground)
VDDL and VSSDL are power supply for DLL circuits
(Reference Voltage)
SSTL_1.8 reference voltage
(No Connection)
No internal electrical connection is present.
6/29
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EM44DM0888LBA
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
VDD
Input, Output Voltage
-0.5 ~ +2.3
V
Power Supply Voltage
-1.0 ~ +2.3
V
VDDQ
Power Supply Voltage
-0.5 ~ +2.3
V
VDDL
DLL Power Supply Voltage
-0.5 ~ +2.3
V
TOP
Operating Temperature Range
TSTG
Storage Temperature Range
PD
Commercial
Power Dissipation
°C
0 ~ +70
-55 ~ +100
°C
1
W
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings
could cause permanent damage. The device is not meant to be operated under conditions
outside the limits described in the operational section of this specification. Exposure to
Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA=-0°C ~+70°C)
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDL
Power Supply for DLL Voltage
1.7
1.8
1.9
V
VDDQ
Power Supply for I/O Voltage
1.7
1.8
1.9
V
VREF
I/O Reference Voltage
0.49 VDDQ
0.50VDDQ
0.51 VDDQ
V
VREF-0.04
VREF
VREF+0.04
V
-0.3
-
VREF-0.15
V
VTT
I/O Termination Voltage
VID
DC Differential Input Voltage
VIH
Input Logic High Voltage
VREF+0.125
-
VDDQ+0.3
V
VIL
Input Logic Low Voltage
-0.3
-
VREF-0.125
V
Feb. 2012
7/29
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EM44DM0888LBA
Recommended DC Operating Conditions
(VDD=1.8V±0.1V)
Symbol
Parameter
Test Conditions
(Note 1)
IDD1
Operating Current
IDD2P
Precharge Standby Current
in Power Down Mode
IDD2N
Precharge Standby Current
in NON-power down mode
All banks idle
IDD3P
IDD3P
IDD3N
IDD4W
Active Standby Current in
Power Down Mode (A12=0)
Active Standby Current in
Power Down Mode (A12=1)
Active Standby Current
in Non-power Down Mode
Operating Current
Mode) (Note 2)
IDD4R
(Note 3)
IDD5
Refresh Current
IDD6
Self Refresh Current
IDD7
Operating Current
(Burst
IOUT = 0mA
BL = 4, CL = CL(IDD), AL = 0
tCK = tCK(IDD), tRC = tRC (IDD)
tRAS = tRASmin(IDD), tRCD = tRCD(IDD)
CKE=HIGH
CS=HIGH between valid commands
Address bus inputs are SWITCHING
Data pattern is same as IDD4W
All banks idle
tCK = tCK(IDD), CKE is LOW
Other control and address bus inputs are
STABLE
Data bus inputs are FLOATING
All banks idle
tCK = tCK(IDD), CKE is HIGH, CS is HIGH
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
All banks open
tCK = tCK(IDD), CKE is LOW
Other control and address bus inputs are
STABLE
Data bus inputs are FLOATING
All banks open
tCK = tCK(IDD), tRAS = tRASmax(IDD)
tRP = tRP(IDD), CKE is HIGH
CS is HIGH between valid commands
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
All banks open, Continuous burst writes
BL = 4, CL = CL(IDD), AL = 0
tCK = tCK(IDD), tRAS = tRASmax(IDD)
tRP = tRP(IDD), CKE is HIGH
CS is HIGH between valid commands
Address bus inputs are SWITCHING
Data bus inputs are SWITCHING
tCK = tCK(IDD)
Refresh command at every tRFC(IDD) interval
CKE is HIGH, CS is HIGH between valid
commands
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
CK and CK at 0 V, CKE 0.2 V
Other control and address bus inputs are
FLOATING, Data bus inputs are FLOATING
All bank interleaving reads
IOUT = 0mA, BL = 4, CL = CL(IDD)
AL = tRCD(IDD) - 1 x tCK(IDD)
tCK = tCK(IDD), tRC = tRC(IDD)
tRRD = tRRD(IDD), tFAW = tFAW(IDD)
tRCD = 1 x tCK(IDD), CKE is HIGH
CS is HIGH between valid commands
Address bus inputs are STABLE during
DESELECTs
Data pattern is same as IDD4R
-187(1066)
-25(800)
Max
Units
102
85
mA
10
10
mA
48
40
mA
36
30
mA
11
10
mA
60
50
mA
144
120
mA
144
120
210
175
mA
9
9
mA
300
250
mA
*All voltages referenced to VSS.
Note 1: IDD1 depends on output loading and cycle rates. (CL=CLmin, AL=0)
Note 2: IDD4 depends on output loading and cycle rates. Input signals SWITCHING
Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.
Feb. 2012
8/29
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EM44DM0888LBA
Recommended DC Operating Conditions (Continued)
Symbol
Parameter
Test Conditions
Min.
IOH
Output Minimum Source Current
*Note2, 4, 5
-13.4
IOL
Output Minimum Sink Current
*Note3, 4, 5
Max.
Units
mA
+13.4
mA
Note1: The VDDQ of the device under test is referenced
Note2: VDDQ=1.7V, VOUT=1.42V
Note3: VDDQ=1.7V, VOUT=0.28V
Note4: The DC value of VREF applied to the receiving device is expected to be set to VTT
Note5: After OCD calibration to 18Ω at TC=25℃, VDD=VDDQ=1.8V
Input/Output Capacitance
Symbol
Parameter
Min
Max
Min
Max
CCK
Input capacitance, CK & /CK
1.0
2.0
1.0
2.0
pF
CDCK
Input capacitance delta, CK & /CK
-
0.25
-
0.25
pF
CI
Input capacitance, all other pins
1.0
1.75
1.0
1.75
pF
CDI
Input capacitance delta, all other pins
-
0.25
-
0.25
pF
CIO
I/O capacitance, DQ,DM,DQS,/DQS
2.5
3.5
2.5
3.5
pF
CDIO
I/O capacitance delta, DQ,DM,DQS,/DQS
-
0.5
-
0.5
pF
Feb. 2012
DDR2-800
9/29
DDR2-1066
Units
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EM44DM0888LBA
Block Diagram
DM
Auto/ Self
Refresh Counter
DQM
Control
A0
CK, /CK
A1
A2
A7
A8
A9
Row Decoder
A6
Address Register
A4
A5
DQS
Generator
Row Add. Buffer
A3
DLL
Memory
Array
Driver
S/ A & I/ O Gating
A10
Write
FIFO
CLK, /CLK
A11
Col. Decoder
A12
A13
BA0
Receiver
Col. Add. Buffer
BA1
BA2
Data In
Mode Register Set
Data Out
Col Add. Counter
Burst Counter
DIO
Timing Register
DQS
/CK
Feb. 2012
CK
CKE
/CS
/ RAS
/ CAS
10/29
/WE
DM
DQS
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EM44DM0888LBA
OCD Default Setting Table
Parameter
Min.
Typ.
Max.
Units
Output Impedance
12.6
18
23.4
Ω
0
-
4
Ω
1.5
-
5.0
V/ns
0
-
1.5
Ω
Pull-up / Pull-down mismatch
Output Slew Rate
Output Impedance Step Size for OCD Calibration
AC Operating Test Conditions
(VDD=1.8V±0.1V)
Symbol
Value
Units
VSWING (max.)
Input Signal Maximum Peak to Peak Swing
Parameter
1.0
V
SLEW
Input Signal Minimum Slew Rate
1.0
V/ns
VREF
Input Reference Level
0.5*VDDQ
V
AC Operating Test Conditions
Symbol
Parameter
Min.
Max.
Units
0.5
VDDQ
V
VID
AC Differential Input Voltage
VIX
AC Differential Cross Point Input Voltage
0.5*VDDQ-0.175
0.5*VDDQ+0.175
V
VOX
AC Differential Cross Point Output Voltage
0.5*VDDQ-0.125
0.5*VDDQ+0.125
V
VIH
Input Logic High Voltage
VREF+0.200
VDDQ+Vpeak
V
VIL
Input Logic High Voltage
VSSQ-Vpeak
VREF-0.200
V
Feb. 2012
11/29
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EM44DM0888LBA
AC Operating Test Characteristics
(VDD=1.8V±0.1V)
-187 (DDR2-1066)
Symbol
Parameter
-25 (DDR2-800)
Units
Min.
Max.
Min.
Max.
DQ output access from CLK,/CLK
-350
350
-400
400
ps
tDQSCK
DQS output access from CLK,/CLK
-350
350
-350
350
ps
tCL,tCH
CL low/high level width
0.48
0.52
0.48
0.52
tCK
tCK
Clock Cycle Time
1.875
8
2.5
8
ns
tDS
DQ and DM setup time
0
-
50
-
ps
tDH
DQ and DM hold time
75
-
125
-
ps
0.35
-
0.35
-
tCK
tAC
tDIPW
tHZ
tLZ (DQ)
tLZ (DQS)
DQ and DM input pulse width for each
input
Data out high impedance time from
CLK,/CLK
DQ low impedance time from CLK,/CLK
DQS,/DQS low impedance time from
CLK,/CLK
-
tAC
-
(max)
tAC
ns
(max)
2*tAC
tAC
2*tAC
tAC
(min)
(max)
(min)
(max)
tAC
tAC
tAC
tAC
(min)
(max)
(min)
(max)
ns
ns
tDQSQ
DQS-DQ skew for associated DQ signal
-
175
-
200
ps
tQHS
Data hold skew factor
-
250
-
300
ps
tDQSS
Write command to first latching DQS
transition
-0.25
0.25
-0.25
0.25
tCK
DQS Low/High input pulse width
0.35
-
0.35
-
tCK
DQS input valid window
0.20
-
0.20
-
tCK
tDQSL,tDQSH
tDSL,tDSH
Mode Register Set command cycle time
2
-
2
-
tCK
tWPRES
tMRD
Write Preamble setup time
0
-
0
-
ns
tWPRE
Write Preamble
0.35
-
0.35
-
tCK
tWPST
Write Postamble
0.4
0.6
0.4
0.6
tCK
Address/control input setup time (fast
slew rate)
125
-
175
-
ps
200
-
250
-
ps
0.9
1.1
0.9
1.1
tCK
tIS
tIH
tRPRE
Feb. 2012
Address/control input hold time
(fast slew rate)
Read Preamble
12/29
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EM44DM0888LBA
AC Operating Test Characteristics (Continued)
(VDD=1.8V±0.1V)
Symbol
-187 (DDR2-1066)
Parameter
Min.
-25 (DDR2-800)
Max.
Min.
Max.
Units
tRPST
Read Postamble
0.4
0.6
0.4
0.6
tCK
tRAS
Active to Precharge command period
45
70k
45
70k
ns
tRC
Active to Active command period
57.5
-
57.5
-
ns
tRFC
Auto Refresh Row Cycle Time
127.5
-
127.5
-
ns
tRCD
Active to Read or Write delay
12.5
-
12.5
-
ns
tRP
Precharge command period
12.5
-
12.5
-
ns
tRRD
Active bank A to B command period
7.5
-
7.5
-
ns
tCCD
Column address to column address delay
2
-
2
-
tCK
tWR
Write recover time
15
-
15
-
ns
tDAL
Auto precharge write recovery + precharge
time
tRP + tWR
-
tRP + tWR
-
ns
tXARD
Exit active power-down mode to read
command (fast exit)
3
-
2
-
tCK
tXARDS
Exit active power-down mode to read
command (slow exit)
10-AL
-
8-AL
-
tCK
3
-
2
-
tCK
tXP
Exit precharge power-down to any non-read
command
tWTR
Internal write to read command delay
7.5
-
7.5
-
ns
tRTP
Internal read to precharge delay
7.5
-
7.5
-
ns
tXSNR
Exit self Refresh to non-read command
tRFC +10
-
tRFC +10
-
ns
tXSRD
Exit self Refresh to read command
200
-
200
-
tCK
tREFI
Average periodic refresh interval
-
7.8
-
7.8
us
3
-
3
-
tCK
tCKE
CKE minimum pulse width
tFAW
Four active to Row active delay (same bank)
tOIT
OCD drive mode output delay
Feb. 2012
35
0
13/29
35
12
0
ns
12
ns
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EM44DM0888LBA
AC Operating Test Characteristics (Continued)
(VDD=1.8V±0.1V)
Symbol
Speed 800
Parameter
Min.
Max.
Units
tAOND
ODT turn-on delay
2
2
tCK
tAOFD
ODT turn-off delay
tAON
ODT turn-on
tAOF
ODT turn-off
2.5
2.5
tCK
(Note1)
tAC(min.)
tAC(max) + 0.7
ns
(Note2)
tAC(min.)
tAC(max) + 0.6
ns
tAONPD
ODT turn-on in power-down mode
tAC(min.) +2
2*tCK + tAC(max) +1
ns
tAOFPD
ODT turn-off in power-down mode
tAC(min.) +2
2.5*tCK + tAC(max) +1
ns
tANPD
ODT to power-down mode entry latency
3
-
tCK
tAXPD
ODT power-down exit latency
8
-
tCK
(VDD=1.8V±0.1V)
Symbol
Speed 1066
Parameter
Min.
Max.
Units
tAOND
ODT turn-on delay
2
2
tCK
tAOFD
ODT turn-off delay
tAON
tAOF
2.5
2.5
tCK
(Note1)
tAC(min.)
tAC(max) + 2.575
ns
(Note2)
tAC(min.)
tAC(max) + 0.6
ns
ODT turn-on
ODT turn-off
tAONPD
ODT turn-on in power-down mode
tAC(min.) +2
2*tCK + tAC(max) +1
ns
tAOFPD
ODT turn-off in power-down mode
tAC(min.) +2
2.5*tCK + tAC(max) +1
ns
tANPD
ODT to power-down mode entry latency
2.5
-
tCK
tAXPD
ODT power-down exit latency
11
-
tCK
Note 1: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to
turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from
tAOND.
Note 2: ODT turn off time min is when the device starts to turn off ODT resistance ODT turn off time max
is when the bus is in high impedance. Both are measured from tAOFD.
Feb. 2012
14/29
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EM44DM0888LBA
Simplified State Diagram
Feb. 2012
15/29
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EM44DM0888LBA
1. Command Truth Table
Device Deselect
DESL
H
X
H
X
X
X
BA0
~
BA2
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
READ
H
H
L
H
L
H
V
L
V
READA
H
H
L
H
L
H
V
H
V
WRIT
H
H
L
H
L
L
V
L
V
WRITA
H
H
L
H
L
L
V
H
V
ACT
H
H
L
L
H
H
V
V
V
PRE
H
H
L
L
H
L
V
L
X
PALL
H
H
L
L
H
L
X
H
X
EMRS
H
H
L
L
L
L
V*
V
V
REF
H
H
L
L
L
H
X
X
X
SELF
H
L
L
L
L
H
X
X
X
H
L
H
X
X
X
X
X
X
H
L
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Command
Symbol
Read
Read with Auto
Pre-charge
Write
Write with Auto
Pre-charge
Bank Activate
Pre-charge Select
Bank
Pre-charge All
Banks
(Ext.) Mode
Register Set
Auto Refresh
Self refresh entry
Power Down Entry
PDEN
Power Down Exit
PDEX
CKE
n-1
N
/CS
/RAS
/CAS
/WE
A10
A12~A0
X
X
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
* Please refers to the MRS, EMRS(1) & EMRS(2) setting
2. CKE Truth Table
Item
Command
Any state
*Note1
All Bank Idle
Self Refresh Entry
Self Refresh
Self Refresh Exit
All Bank Idle
Active or Precharge
Power Down Entry
Power Down
Power Down Exit
Power Down
Maintain power down
Self Refresh
Maintain self refresh
Symbol
CKE
/CS
/RAS
/CAS
/WE
Addr.
H
V
V
V
V
V
H
L
L
L
L
H
X
NOP
L
H
L
H
H
H
X
DESL
L
H
H
X
X
X
X
DESL
H
L
H
X
X
X
X
NOP
H
L
L
H
H
H
X
DESL
L
H
H
X
X
X
X
NOP
L
H
L
H
H
H
X
-
L
L
X
X
X
X
X
-
L
L
X
X
X
X
X
n-1
n
-
H
SELF
H = High level, L = Low level, X = High or Low level (Don't care)
Note1: Must be legal commands as defined in the command truth table. And any state other than list
above.
Feb. 2012
16/29
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EM44DM0888LBA
3. Operative Command Table
Current
State
Idle
Bank
Active
Read
Write
Feb. 2012
/CS
/R
/C
/W
Addr.
Command
H
X
X
X
X
DESL
NOP
L
H
H
H
X
NOP
NOP
L
H
L
H
BA/CA/A10
READ/READA
ILLEGAL (Note 1)
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL (Note 1)
L
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PREA
L
L
L
H
REF/SELF
L
L
L
L
H
L
X
H
X
H
X
H
X
Op-Code,
Mode-Add
X
X
L
H
L
H
BA/CA/A10
READ/READA
L
H
L
L
BA/CA/A10
WRIT/WRITA
L
L
H
H
BA/RA
ACT
L
L
H
L
BA/A10
PRE/PREA
Precharge/Precharge all
L
L
L
H
X
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
H
L
L
L
X
H
H
H
X
H
L
L
X
H
H
L
Op-Code,
Mode-Add
X
X
BA/CA/A10
BA/CA/A10
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL (Note 1)
L
L
L
H
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
H
L
L
X
H
H
X
H
L
X
H
H
X
Op-Code,
Mode-Add
X
X
BA/CA/A10
L
H
L
L
BA/CA/A10
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
X
Op-Code,
PRE/PREA
REF/SELF
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
ILLEGAL (Note 1)
ILLEGAL (Note 1)
MRS/EMRS(1)(2)
DESL
NOP
DESL
NOP
READ/READA
WRIT/WRITA
Action
Bank active,Latch RA
NOP(Note 3)
Auto/Self refresh(Note 4)
Mode register
NOP
NOP
Begin read,Latch CA, Determine
auto-precharge
Begin write,Latch CA, Determine
auto-precharge
ILLEGAL (Note 1)
Row Active(Continue burst to end)
Row Active(Continue burst to end)
Burst Interrupt
ILLEGAL(Note 1)
DESL
NOP
READ/READA
Write recovering (Continue burst to end)
Write recovering (Continue burst to end)
ILLEGAL(Note 1)
WRIT/WRITA
Burst Interrupt
17/29
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EM44DM0888LBA
3. Operative Command Table (Continued)
Current
State
Read with
AP
Write with
AP
Pre-charging
Row
Activating
/CS
/R
/C
/W
Addr.
Command
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
L
H
BA/CA/A10
READ/READA
L
H
L
L
BA/CA/A10
WRIT/WRITA
L
L
H
H
BA/A10
ACT
ILLEGAL (Note 1)
L
L
H
L
BA/A10
PRE/PREA
ILLEGAL (Note 1)
L
L
L
H
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
X
Op-Code,
Mode-Add
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
L
H
BA/CA/A10
READ/READA
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL (Note 1)
Action
Precharging (Continue burst to
end)
Precharging (Continue burst to
end)
ILLEGAL (Note 1)
ILLEGAL (Note 1)
Write recover with auto precharge
(Continue burst to end)
Write recover with auto precharge
(Continue burst to end)
ILLEGAL (Note 1)
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
L
L
H
L
L
H
PRE/PREA
ILLEGAL (Note 1)
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
H
L
L
X
H
H
X
H
L
X
H
H
BA/A10
X
Op-Code,
Mode-Add
X
X
BA/CA/A10
DESL
NOP
READ/READA
NOP(idle after tRP)
NOP(idle after tRP)
ILLEGAL (Note 1)
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL (Note 1)
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
L
L
H
L
L
H
PRE/PREA
NOP(idle after tRP) (Note 3)
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
H
L
L
X
H
H
X
H
L
X
H
H
BA/A10
X
Op-Code,
Mode-Add
X
X
BA/CA/A10
L
H
L
L
BA/CA/A10
WRIT/WRITA
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
H
L
BA/A10
PRE/PREA
ILLEGAL (Note 1)
L
L
L
H
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
X
Op-Code,
Mode-Add
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
DESL
NOP
READ/READA
NOP(Row active after tRCD)
NOP(Row active after tRCD)
ILLEGAL (Note 1)
ILLEGAL (Note 1)
H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Feb. 2012
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EM44DM0888LBA
3. Operative Command Table (Continued)
Current
State
/CS
/R
/C
/W
Addr.
Command
H
X
X
X
X
DESL
NOP (enter bank active
after tWR)
L
H
H
H
X
NOP
NOP (enter bank active
after tWR)
L
H
L
H
BA/CA/A10
READ
ILLEGAL (Note 1)
Write
L
H
L
L
BA/CA/A10
WRIT/WRITA
Recovering
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
H
L
BA/A10
PRE/PREA
ILLEGAL (Note 1)
L
L
L
H
X
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
Op-Code,
Mode-Add
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
H
X
X
X
X
DESL
NOP(idle after tRFC)
L
H
H
H
X
NOP
NOP(idle after tRFC)
L
H
L
H
BA/CA/A10
READ/READA
ILLEGAL (Note 1)
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL (Note 1)
L
L
H
H
BA/RA
ACT
ILLEGAL (Note 1)
L
L
H
L
BA/A10
PRE/PREA
ILLEGAL (Note 1)
L
L
L
H
X
REF/SELF
ILLEGAL (Note 1)
L
L
L
L
Op-Code,
Mode-Add
MRS/EMRS(1)(2)
ILLEGAL (Note 1)
Refreshing
Action
New write, Determine AP
H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Note 1: ILLEGAL to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.
Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA.
Note 4: ILLEGAL of any bank is not idle.
Feb. 2012
19/29
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EM44DM0888LBA
4. Command Truth Table for CKE
Current State
Self Refresh
Both bank
precharge
power down
All Banks Idle
Any state other than
listed above
C
H
KE
X
/CS
X
X
/R
/C
X
/W
X
Addr.
X
Action
INVALID
L
H
H
X
X
X
X
Exist Self-Refresh
L
H
L
H
H
H
X
L
H
L
H
H
L
X
L
H
L
H
L
X
X
Exist Self-Refresh
ILLEGAL
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain self refresh)
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
L
L
L
H
H
H
L
L
L
H
H
H
H
H
L
H
L
X
X
X
X
L
H
L
L
X
X
X
Exist Power down
Exist Power down
ILLEGAL
ILLEGAL
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Power down)
H
H
X
X
X
X
X
Refer to function true table
H
L
H
X
X
X
X
Enter power down mode(Note 3)
H
L
L
H
H
H
X
Enter power down mode(Note 3)
H
L
L
H
H
L
X
H
H
L
L
L
L
H
L
L
H
X
H
X
RA
H
L
L
L
L
H
X
ILLEGAL
ILLEGAL
Row active/Bank active
Enter self-refresh(Note 3)
H
L
L
L
L
L
Op-Code
Mode register access
H
L
L
L
L
L
Op-Code
Special mode register access
L
X
X
X
X
X
X
Refer to current state
H
H
X
X
X
X
X
Refer to command truth table
H = High level, L = Low level, X = High or Low level (Don't care)
Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after
CKE’s low to high transition to issue a new command.
Notes 2: CKE low to high transition is asynchronous as if restarts internal clock.
Notes 3: Power down and self refresh can be entered only from the idle state of all banks.
5. Bank Selection Signal Table
Bank\Signal
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Note: H:VIH, L:VIL
Feb. 2012
BA0
L
H
L
H
L
H
L
H
BA1
L
L
H
H
L
L
H
H
BA2
L
L
L
L
H
H
H
H
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EM44DM0888LBA
Initialization
The following sequence is required for power-up and initialization and is shown in below Figure:
1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be
undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
- VDD, VDDL and VDDQ are driven from a single power converter output, and VTT is limited to 0.95 V max,
and VREF tracks VDDQ/2 or
- Apply VDD before or at the same time as VDDL; Apply VDDL before or at the same time as VDDQ;
- Apply VDDQ before or at the same time as VTT & VREF. at least one of these two sets of conditions must be
met.
2. Start clock (CK, /CK) and maintain stable power and clock condition for a minimum of 200 µs.
3. Apply NOP or Deselect commands & take CKE high.
4. Wait minimum of 400ns, then issue a Precharge-all command.
5. Issue Reserved command EMRS(2) or EMRS(3).
6. Issue EMRS(1) command to enable DLL. (A0=0 and BA0=1 and BA1=0)
7. Issue MRS Command (Mode Register Set) for "DLL reset". (A8=1 and BA0=BA1=0)
8. Issue Precharge-All command.
9. Issue 2 or more Auto-Refresh commands.
10. Issue a MRS command with low on A8 to initialize device operation. (Without resetting the DLL)
11. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD
calibration is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD Calibration
Mode Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1).
12. The DDR2 SDRAM is now initialized and ready for normal operation.
Feb. 2012
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EM44DM0888LBA
Mode Register Definition
Mode Register Set
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM which contains
addressing mode, burst length, /CAS latency, WR (write recovery), test mode, DLL reset and various vendor’s
specific opinions.
The defaults value of the register is not defined, so the mode register must be written after power up for proper
DDR2 SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0/1.
The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0/1 going low is
written in the mode register.
Two clock cycles are requested to complete the write operation in the mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operating as long as
all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A0-A2,
addressing mode uses A3, /CAS latency (read latency from column address) uses A4-A6. A7 is used for test
mode. A8 is used for DDR reset. A9 ~ A11 are used for write recovery time (WR), A7 must be set to low for
normal MRS operation. With address bit A12 two Power-Down modes can be selected, a “standard mode” and
a “low-power” Power-Down mode.
Feb. 2012
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EM44DM0888LBA
Address input for Mode Register Set
Note1. Active power down exit time’s fast exit (A12=0) use tXARD and slow exit (A12=1) use tXARDS.
Note2. A13 is reserved for future use.
Note3. BA2 is reserved for future use
Feb. 2012
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EM44DM0888LBA
Burst Type (A3)
Burst Length
4
8
A2
A1
A0
Sequential Addressing
Interleave Addressing
X
0
0
0123
0123
X
0
1
1230
1032
X
1
0
2301
2301
X
1
1
3012
3210
0
0
0
01234567
01234567
0
0
1
12345670
10325476
0
1
0
23456701
23016745
0
1
1
34567012
32107654
1
0
0
45670123
45670123
1
0
1
56701234
54761032
1
1
0
67012345
67452301
1
1
1
70123456
76543210
*Page length is a function of I/O organization and column addressing
Write Recovery
WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time when the device starts
pre-charge internally. WR must be programmed to match the minimum requirement for the analogue tWR
timing.
Power-Down Mode
Active power-down (PD) mode is defined by bit A12. PD mode allows the user to determine the active
power-down mode, which determines performance vs. power savings. PD mode bit A12 does not apply to
precharge power-down mode. When bit A12 = 0, standard Active Power-down mode or ‘fast-exit’ active
power-down mode is enabled. The tXARD parameter is used for ‘fast-exit’ active power-down exit timing. The
DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower power active
power-down mode or ‘slow-exit’ active power-down mode is enabled. The tXARDS parameter is used for
‘slow-exit’ active power-down exit timing. The DLL can be enabled, but ‘frozen’ during active power-down
mode since the exit-to-READ command timing is relaxed. The power difference expected between PD
‘normal’ and PD ‘low-power’ mode is defined in the IDD table.
Feb. 2012
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EM44DM0888LBA
Extended Mode Register Set EMRS(1 )
The EMRS (1) is written by asserting low on /CS, /RAS, /CAS, /WE,BA1 and high on BA0 ( The DDR2 should
be in all bank pre-charge with CKE already prior to writing into the extended mode register. ) The extended
mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive
latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of
the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after
power-up for proper operation. The mode register set command cycle time (tMRD) must be satisfied to complete
the write operation to the EMRS(1). Mode register contents can be changed using the same command and
clock cycle requirements during normal operation when all banks are in pre-charge state.
BA2
BA1
BA0
A13
A12
A11
A10
0
0
1
0
Qoff
RDQS
/DQS
Qoff (Output Buffer)
A12
Enabled
0
1
Disabled
RDQS
enable
A11
A11
Disable
00
Enable
11
A9
A7
A6
OCD program
A8
Rtt
/DQS
A10
Enable
0
Disable
1
A5
A4
A3
Additive latency
A2
A1
A0
Rtt
DIC
DLL
DLL
A0
A0
Enable
00
Disable
11
Output Driver
Impedance Control
OCD Calibration Program
A9 A8 A8
0
0
0
0
0
0
0
(*1)
Adjust mode (*1) 1
1
OCD Calibration
1
(*2) default (*2)
1
OCD Calibration mode exit
0
Drive (1)
Drive (0)
A7
A7
0
00
0
11
1
00
0
0
00
1
1
11
Normal (100%)
0
Weak (60%)
1
RttRtt
A6
A2
A2
ODT
Disable
ODT
Disable
0
0
75 ohm
75 ohm
0
1
150
ohm
150
ohm
1
0
ohm *
50 50
ohm
1
1
*
*1:
When adjust mode is issued, AL from previously set value must be applied.
*2: After setting to default, OCD mode needs to be exited by setting A9 - A7 to 000.
Refer to the section- Off Chip Driver (OCD) impedance adjustment for detail
information
Additive Latency
A1
A5
A4
A3
0
0
0
MRS Mode
BA1
BA0
0
MRS
0
0
1
0
0
1
0
1
0
EMRS(1)
0
1
2
EMRS(2)
1
0
3
0
1
1
1
1
4
1
0
0
5
1
0
1
6
1
1
0
Reserved
1
1
1
EMRS(3) Reserved
Note1. For DDR2-1066, the “Rtt” must be set to 50 ohm (A2 = 1 & A6 = 1).
Note2. A13 is reserved for future use.
Note3. BA2 is reserved for future use.
Feb. 2012
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EM44DM0888LBA
Output Drive Strength
The output drive strength is defined by bit A1. Normal drive strength outputs are specified to be SSTL_18.
Programming bit A1 = 0 selects normal (100 %) drive strength for all outputs.
Programming bit A1 = 1 will reduce all outputs to approximately 60 % of the SSTL_18 drive strength.
This option is intended for the support of the lighter load and/or point-to-point environments.
Single-ended and Differential Data Strobe Signals
EMRS
Strobe Function Matrix
Signals
A11
(/RDQS Enable)
A10
(/DQS Enable)
RDQS
DM
/RDQS
DQS
/DQS
0 (Disable)
0 (Enable)
DM
Hi-Z
DQS
/DQS
Differential DQS signal
0 (Disable)
1 (Disable)
DM
Hi-Z
DQS
Hi-Z
Single-ended DQS signal
1 (Enable)
0 (Enable)
RDQS
/RDQS
DQS
/DQS
Differential DQS signal
1 (Enable)
1 (Disable)
RDQS
Hi-Z
DQS
Hi-Z
Single-ended DQS signal
Output Disable (Qoff)
Under normal operation, the DRAM outputs are enabled during Read operation for driving data Qoff bit in the
EMRS(1) is set to (0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM
outputs allows users to measure IDD currents during Read operations, without including the output buffer
current.
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EM44DM0888LBA
Address input for Extended Mode Register Set EMRS(2)
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On-Die Termination (ODT)
ODT (On-Die Termination) is a new feature on DDR2 components that allows a DRAM to turn on/off
termination resistance for each UDQ, LDQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via the ODT
control pin for x16 configuration, where UDQS and LDQS are terminated only when enabled in the EMRS(1) by
address bit A10 = 0.
The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM
controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function
can be used for all active and standby modes. ODT is turned off and not supported in Self- Refresh mode.
ODT Function
Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by “Rtt
(nominal)” in EMRS(1) address bits A6 & A2. Target Rtt = 0.5 * Rval1 or 0.5 * Rval2.
The ODT pin will be ignored if the EMRS(1) is programmed to disable ODT.
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Package Description: 60Ball-FBGA
Solder ball: Lead free (Sn-Ag-Cu)
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