TI DS90C401MX Ds90c401 dual low voltage differential signaling (lvds) driver Datasheet

NRND
DS90C401
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SNLS002C – JUNE 1998 – REVISED APRIL 2013
DS90C401 Dual Low Voltage Differential Signaling (LVDS) Driver
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FEATURES
DESCRIPTION
•
•
•
•
•
The DS90C401 is a dual driver device optimized for
high data rate and low power applications. This
device along with the DS90C402 provides a pair chip
solution for a dual high speed point-to-point interface.
The DS90C401 is a current mode driver allowing
power dissipation to remain low even at high
frequency. In addition, the short circuit fault current is
also minimized. The device is in a 8 lead small
outline package. The differential driver outputs
provides low EMI with its low output swings typically
340 mV.
1
2
Ultra Low Power Dissipation
Operates Above 155.5 Mbps
Standard TIA/EIA-644
8 Lead SOIC Package Saves Space
Low Differential Output Swing typical 340 mV
Connection Diagram
See Package Number D (SOIC)
Functional Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
NRND
DS90C401
SNLS002C – JUNE 1998 – REVISED APRIL 2013
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Absolute Maximum Ratings (1) (2)
−0.3V to +6V
Supply Voltage (VCC)
Input Voltage (DIN)
−0.3V to (VCC + 0.3V)
Output Voltage (DOUT+, DOUT−)
−0.3V to (VCC + 0.3V)
Short Circuit Duration
(DOUT+, DOUT−)
Continuous
Maximum Package Power Dissipation @ +25°C
D Package
1068 mW
Derate D Package
8.5 mW/°C above +25°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Junction Temperature
+150°C
ESD Rating
(3)
≥ 3,500V
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0 Ω, 200 pF)
(1)
(2)
(3)
≥ 250V
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
ESD Ratings:
HBM (1.5 kΩ, 100 pF) ≥ 3,500V
EIAJ (0Ω, 200 pF) ≥ 250V
Recommended OperatingConditions
Min
Typ
Max
Supply Voltage (VCC)
+4.5
+5.0
+5.5
Units
V
Operating Free Air Temperature (TA)
−40
+25
+85
°C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2)
Symbol
Parameter
VOD1
Differential Output Voltage
ΔVOD1
Change in Magnitude of VOD1 for
Complementary Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for
Complementary Output States
VOH
Output Voltage High
VOL
Output Voltage Low
Conditions
RL = 100Ω (Figure 1)
VIL
Input Voltage Low
II
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VCL
Input Clamp Voltage
ICL = −18 mA
ICC
No Load Supply Current
DIN = VCC or GND
VOUT = 0V
mV
4
35
|mV|
1.25
1.375
V
5
25
|mV|
1.41
1.60
V
RL = 100Ω All Channels
VIN = VCC or GND (all inputs)
1.07
−3.5
DIN
DIN = 2.5V or 0.4V
2
Units
450
(3)
Input Voltage High
(2)
(3)
Max
340
0.90
Output Short Circuit Current
(1)
Typ
250
RL = 100Ω
VIH
Loaded Supply Current
Min
1.125
IOS
ICCL
Pin
DOUT−,
DOUT+
VCC
V
−5.0
mA
2.0
VCC
V
GND
0.8
V
+10
μA
1.7
3.0
mA
3.5
5.5
mA
8
14.0
mA
−10
±1
−1.5
−0.8
V
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VOD1 and ΔVOD1.
All typicals are given for: VCC = +5.0V, TA = +25°C.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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Switching Characteristics
VCC = +5.0V ±10%, TA = −40°C to +85°C (1) (2) (3) (4) (5)
Symbol
Parameter
Conditions
RL = 100Ω, CL = 5 pF
(Figure 2 and Figure 3)
Min
Typ
Max
Units
0.5
2.0
3.5
ns
0.5
2.1
3.5
ns
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
tSKD
Differential Skew |tPHLD – tPLHD|
0
80
900
ps
tSK1
Channel-to-Channel Skew (2)
0
0.3
1.0
ns
(3)
tSK2
Chip to Chip Skew
3.0
ns
tTLH
Rise Time
0.35
2.0
ns
tTHL
Fall Time
0.35
2.0
ns
(1)
(2)
(3)
(4)
(5)
All typicals are given for: VCC = +5.0V, TA = +25°C.
Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, and tf ≤ 6 ns.
CL includes probe and jig capacitance.
Parameter Measurement Information
Figure 1. Driver VOD and VOS Test Circuit
Figure 2. Driver Propagation Delay and Transition Time Test Circuit
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Figure 3. Driver Propagation Delay and Transition Time Waveforms
4
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TYPICAL APPLICATION
Figure 4. Point-to-Point Application
Applications Information
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 4. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C401 differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The typical
output current is mere 3.4 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as
discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as
shown in Figure 4. AC or unterminated configurations are not allowed. The 3.4 mA loop current will develop a
differential voltage of 340 mV across the 100Ω termination resistor which the receiver detects with a 240 mV
minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (340
mV – 100 mV = 240 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as
shown in Figure 5. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 680 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
Figure 5. Driver Output Levels
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PIN DESCRIPTIONS
Pin No.
Name
Description
4, 8
DIN
3, 7
DOUT+
TTL/CMOS driver input pins
Non-inverting driver output pin
2, 6
DOUT−
Inverting driver output pin
5
GND
Ground pin
1
VCC
Positive power supply pin,
+5.0V ± 10%
Truth Table (1)
(1)
6
DIN
DOUT+
DOUT−
L
L
H
H
H
L
DIN > 0.8V and DIN < 2.0V
X
X
H = Logic high level
L = Logic low level
X = Indeterminant state
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Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
Power Supply Current
vs Temperature
Figure 6.
Figure 7.
Power Supply Current
vs Power Supply Voltage
Power Supply Current
vs Temperature
Figure 8.
Figure 9.
Output Short Circuit Current
vs Power Supply Voltage
Differential Output Voltage
vs Power Supply Voltage
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
8
Differential Output Voltage
vs Ambient Temperature
Output Voltage High vs
Power Supply Voltage
Figure 12.
Figure 13.
Output Voltage High vs
Ambient Temperature
Output Voltage Low vs
Power Supply Voltage
Figure 14.
Figure 15.
Output Voltage Low vs
Ambient Temperature
Offset Voltage vs
Power Supply Voltage
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
Offset Voltage vs
Ambient Temperature
Power Supply Current
vs Frequency
Figure 18.
Figure 19.
Differential Output Voltage
vs Load Resistor
Differential Propagation Delay
vs Power Supply Voltage
Figure 20.
Figure 21.
Differential Propagation Delay
vs Ambient Temperature
Differential Skew vs
Power Supply Voltage
Figure 22.
Figure 23.
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Typical Performance Characteristics (continued)
Differential Skew vs
Ambient Temperature
Differential Transition Time
vs Power Supply Voltage
Figure 24.
Figure 25.
Differential Transition Time
vs Ambient Temperature
Figure 26.
10
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
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10-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
DS90C401M
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
DS90C
401M
DS90C401M/NOPB
NRND
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
DS90C
401M
DS90C401MX
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
DS90C
401M
DS90C401MX/NOPB
NRND
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
DS90C
401M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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10-Sep-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90C401MX
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
DS90C401MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90C401MX
SOIC
D
8
2500
367.0
367.0
35.0
DS90C401MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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