PHILIPS HEF4557B 1-to-64 bit variable length shift register Datasheet

INTEGRATED CIRCUITS
DATA SHEET
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• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4557B
LSI
1-to-64 bit variable length shift
register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
purposes. Information on DA or DB is shifted into the first
register position and all the data in the register is shifted
one position to the right on the LOW to HIGH transition of
CP0 while CP1 is LOW or on the HIGH to LOW transition
of CP1 while CP0 is HIGH. A HIGH on master reset (MR)
resets the register and forces O to LOW and O to HIGH,
independent of the other inputs.
DESCRIPTION
The HEF4557B is a static clocked serial shift register
whose length may be programmed to be any number of
bits between 1 and 64. The number of bits selected is
equal to the sum of the subscripts of the enabled length
control inputs (L1, L2, L4, L8, L16 and L32) plus one. Serial
data may be selected from the DA or DB data inputs with
the A/B select input. This feature is useful for recirculation
Fig.1 Functional diagram.
PINNING
DA, DB
data inputs
A/B
select data input
CP0
clock input
CP1
clock enable input
MR
asynchronous master reset
L1 to L32
bit-length control inputs
O, O
buffered outputs
HEF4557BP(N):
16-lead DIL; plastic
HEF4557BD(F):
16-lead DIL; ceramic (cerdip)
(SOT38-1)
(SOT74)
HEF4557BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
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Philips Semiconductors
3
1-to-64 bit variable length shift register
January 1995
Product specification
HEF4557B
LSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
Notes
FUNCTION TABLE
INPUTS
1. The moment Dn appears at O depends on the
bit-length shown in the table below.
OUTPUT
CP1
O (1)
D2
L
D2
3. L = LOW state (the less positive voltage)
D1
D2
L
D1
4. X = state is immaterial
D1
D2
D2
5.
= positive-going transition
D1
6.
= negative-going transition
L
7. Dn = either HIGH or LOW
MR
A/B
DA
DB
L
L
D1
L
H
L
L
CPO
H
L
H
D1
D2
H
H
X
X
X
X
X
2. H = HIGH state (the more positive voltage)
BIT-LENGTH SELECT FUNCTION TABLE
L32
L16
L8
L4
L2
L1
REGISTER LENGTH
L
L
L
L
L
L
1-bit
L
L
L
L
L
H
2-bits
L
L
L
L
H
L
3-bits
L
L
L
L
H
H
4-bits
L
L
L
H
L
L
5-bits
L
L
L
H
L
H
6-bits
L
L
L
H
H
L
7-bits
L
L
L
H
H
H
8-bits
↓
↓
↓
↓
↓
↓
↓
L
H
H
H
H
H
32-bits
H
L
L
L
L
L
33-bits
H
L
L
L
L
H
34-bits
↓
↓
↓
↓
↓
↓
↓
H
H
H
H
L
L
61-bits
H
H
H
H
L
H
62-bits
H
H
H
H
H
L
63-bits
H
H
H
H
H
H
64-bits
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
3 500 fi + ∑ (foCL) × VDD2
10
15 000 fi + ∑ (foCL) × VDD
2
15
37 000 fi + ∑ (foCL) × VDD
2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
CP0, CP1 → O, O
5
HIGH to LOW
10
240
480
ns
213 ns + (0,55 ns/pF) CL
90
180
ns
79 ns + (0,23 ns/pF) CL
65
130
ns
57 ns + (0,16 ns/pF) CL
240
480
ns
213 ns + (0,55 ns/pF) CL
90
180
ns
79 ns + (0,23 ns/pF) CL
65
130
ns
57 ns + (0,16 ns/pF) CL
tPHL
15
5
LOW to HIGH
10
tPLH
15
MR → O
5
HIGH to LOW
10
170
340
ns
143 ns + (0,55 ns/pF) CL
80
160
ns
69 ns + (0,23 ns/pF) CL
60
120
ns
52 ns + (0,16 ns/pF) CL
140
280
ns
113 ns + (0,55 ns/pF) CL
70
140
ns
59 ns + (0,23 ns/pF) CL
55
110
ns
47 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
tPHL
15
MR → O
5
LOW to HIGH
10
tPLH
15
Output transition times
5
HIGH to LOW
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
10
LOW to HIGH
tTHL
10
tTLH
15
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
Interpolation table (see note next page)
LENGTH CONTROL INPUTS
L1
L2
L4
L8
L16
L32
MINIMUM
NUMBER OF
BITS SELECTED
SET-UP, HOLD,
RECOVERY
TIMES
L
L
L
L
L
L
1
specified
H
L
L
L
L
L
2
X
H
L
L
L
L
3



X
X
H
L
L
L
5
six equal steps
X
X
X
H
L
L
9
X
X
X
X
H
L
17



X
X
X
X
X
H
33
specified
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
5
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
SYMBOL
MIN.
TYP.
Minimum clock
5
tWCPL
180
90 ns
LOW for CP0 or
pulse width;
10
or
60
30 ns
HIGH for CP1
15
tWCPH
40
20 ns
Minimum reset
5
pulse width;
10
150
75 ns
70
35 ns
HIGH
15
50
25 ns
5
360
180 ns
140
70 ns
tWMRH
Set-up times
DA, DB, A/B → CP0,
CP1
10
L1 to L32 = LOW
15
90
45 ns
5
40
−20 ns
35
−10 ns
15
30
−5 ns
5
−40
−110 ns
−10
−45 ns
L32 = HIGH
10
tsu
tsu
Hold times
DA, DB, A/B → CP0,
CP1
10
L1 to L32 = LOW
15
0
−30 ns
5
90
30 ns
60
20 ns
L32 = HIGH
Recovery times for MR
L1 to L32 = LOW
L32 = HIGH
Minimum clock
pulse frequency
10
thold
thold
15
50
15 ns
5
500
250 ns
250
125 ns
10
tRMR
15
150
75 ns
5
110
50 ns
70
30 ns
15
60
25 ns
5
2,5
5 MHz
7
14 MHz
10
20 MHz
10
10
15
tRMR
fmax
see note
Note
1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified
one may interpolate as shown in the table (see previous page).
January 1995
6
Philips Semiconductors
Product specification
1-to-64 bit variable length shift register
Fig.4
HEF4557B
LSI
Waveforms showing recovery time for MR and minimum CP0, CP1 and MR pulse widths, set-up and hold
times for DA, DB and A/B to CP0 and CP1. Set-up and hold times are shown as positive values but may
be specified as negative values.
January 1995
7
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