TI ISO7230A One megabit per second triple digital isolator Datasheet

ISO7230A
ISO7231A
www.ti.com ........................................................................................................................................................................................................ SLLS906 – MAY 2008
One Megabit per Second Triple Digital Isolators
FEATURES
1
•
•
•
•
•
1-Mbps Signaling Rate
– Low Channel-to-Channel Output Skew;
1 ns max
– Low Pulse-Width Distortion (PWD);
2 ns max
– Low Jitter Content; 1 ns Typ at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 10)
4000-Vpeak Isolation, 560-Vpeak VIORM
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IE 61010-1 and CSA Approved
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
•
•
High Electromagnetic Immunity
(see application note SLLA181)
–40°C to 125°C Operating Range
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION
The ISO7230A and ISO7231A are triple-channel digital isolators each with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
The ISO7230 triple-channel device has all three channels in the same direction while the ISO7231 has two
channels in one direction and one channel in opposition. These devices have an active-high output enable that
when driven to a low level, places the output in a high-impedance state and turns off internal bias circuitry to
conserve power.
The ISO7230A and ISO7231A have TTL input thresholds and a noise-filter at the input that prevents transient
pulses of up to 2 ns in duration from being passed to the output of the device.
In each device a periodic update pulse is sent across the isolation barrier to ensure the proper dc level of the
output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven,
and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation
over the ambient temperature range of –40°C to 125°C.
ISO7230
DW PACKAGE
VCC1
GND1
INA
INB
INC
NC
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ISO7231
DW PACKAGE
VCC2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
VCC1
GND1
INA
INB
OUTC
NC
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ISO7230A
ISO7231A
SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
IN
Input
+
Filter
Data MUX
AC Detect
Vref
OUT
Output Buffer
AC Channel
Table 1. Device Function Table ISO723x
VCC1
VCC2
PU
(1)
PU
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
H
PD
PU
X
H or Open
H
PD
PU
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
AVAILABLE OPTIONS
(1)
2
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ISO7230ADW
1 Mbps
~1.5 V (TTL)
(CMOS compatible)
3/0
ISO7230A
ISO7231ADW
1 Mbps
~1.5 V (TTL)
(CMOS compatible)
2/1
ISO7231A
ORDERING
NUMBER (1)
ISO7230ADW (rail)
ISO7230ADWR (reel)
ISO7231ADW (rail)
ISO7231ADWR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ISO7230A
ISO7231A
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ABSOLUTE MAXIMUM RATINGS (1)
(2)
VCC
Supply voltage
VI
Voltage at IN, OUT, EN
, VCC1, VCC2
IO
Output current
ESD
Electrostatic Field-Induced-Charged Device
discharge
Model
TJ
Maximum junction temperature
Human Body Model
JEDEC Standard 22, Test Method A114-C.01
Machine Model
(1)
(2)
JEDEC Standard 22, Test Method C101
VALUE
UNIT
–0.5 to 6
V
–0.5 to 6
V
±15
mA
±4
All pins
ANSI/ESDS5.2-1996
kV
±1
±200
V
170
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
(1)
Supply voltage
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
1
1/tui
Signaling rate
0
VIH
High-level input voltage (IN) (EN on all devices)
2
VCC
VIL
Low-level input voltage (IN) (EN on all devices)
0
0.8
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
(2)
3.15
MAX
VCC
(1)
, VCC1, VCC2
TYP
5.5
4
–4
UNIT
V
mA
mA
µs
1500 (2)
1000
150
1000
kbps
V
°C
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Typical sigalling rate under ideal conditions at 25°C.
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ISO7230A
ISO7231A
SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
1
3
1
3
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
6.5
11
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
15
22
16
22
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
13
20
13
20
UNIT
SUPPLY CURRENT
Quiescent
ISO7230A
1 Mbps
ICC1
Quiescent
ISO7231A
1 Mbps
Quiescent
ISO7230A
1 Mbps
ICC2
Quiescent
ISO7231A
1 Mbps
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, Single channel
VCC – 0.8
IOH = –20 µA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
(1)
µA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
150
mV
10
IN from 0 V to VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
40
95
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
4
See Figure 1
(2)
10
0
See Figure 1
See Figure 2
See Figure 3
2
2
ns
ns
ns
2
12
UNIT
ns
µs
Also referred to as pulse skew.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7230A
ISO7231A
www.ti.com ........................................................................................................................................................................................................ SLLS906 – MAY 2008
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
3
1
3
6.5
11
6.5
11
UNIT
SUPPLY CURRENT
ISO7230A
ICC1
ISO7231A
Quiescent
1 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
Quiescent
ISO7230A
1 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
9
15
9.5
15
8
12
8
12
mA
mA
mA
ICC2
ISO7231A
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at VCC, Single channel
IOH = –4 mA, See Figure 1
VCC – 0.4
ISO7231
(5-V side)
VCC – 0.8
IOH = –20 µA, See Figure 1
V
VCC – 0.1
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
(1)
µA
0
ISO7230
150
mV
10
IN from 0 V to VCC
V
–10
µA
2
pF
25
50
kV/µs
MIN
TYP MAX
40
100
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
(2)
ISO723xA
See Figure 1
ISO723xA/C
11
0
See Figure 1
See Figure 2
See Figure 3
2.5
2
UNIT
ns
ns
ns
2
18
ns
µs
Also known as pulse skew
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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5
ISO7230A
ISO7231A
SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
1
2
4.5
7
4.5
7
15
22
16
22
13
20
13
20
UNIT
SUPPLY CURRENT
Quiescent
ISO7230A
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
1 Mbps
ICC1
Quiescent
ISO7231A
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
1 Mbps
Quiescent
ISO7230A
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
1 Mbps
ICC2
Quiescent
ISO7231A
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
1 Mbps
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, Single channel
VOH
High-level output voltage
ISO7230
VCC – 0.4
ISO7231
(5-V side)
VCC – 0.8
IOH = –20 µA, See Figure 1
V
VCC – 0.1
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
(1)
µA
0
IOH = –4 mA, See Figure 1
150
mV
10
IN from 0 V to VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
6
ISO723xA
(2)
See Figure 1
ISO723xA
40
MAX
tPLH, tPHL
100
11
0
See Figure 1
See Figure 2
See Figure 3
2.5
2
ns
ns
ns
2
12
UNIT
ns
µs
Also known as pulse skew
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7230A
ISO7231A
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
0.5
1
1
2
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
4.5
7
4.5
7
UNIT
SUPPLY CURRENT
Quiescent
ISO7230A
1 Mbps
ICC1
Quiescent
ISO7231A
1 Mbps
Quiescent
ISO7230A
1 Mbps
ICC2
Quiescent
ISO7231A
1 Mbps
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
9
15
9.5
15
8
12
8
12
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, single channel
VCC – 0.4
IOH = –20 µA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
(1)
µA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
150
mV
10
IN from 0 V or VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
(2)
ISO723xA
See Figure 1
ISO723xA
45
MAX
tPLH, tPHL
110
12
0
See Figure 1
See Figure 2
See Figure 3
3
2
UNIT
ns
ns
ns
2
18
ns
µs
Also referred to as pulse skew.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7230A
ISO7231A
SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC1
VI
VCC1/2
VCC1/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
ISOLATION BARRIER
RL = 1 kW ±1%
IN
0V
Input
Generator
VI
OUT
EN
Vcc/2
VI
t PZL
VO
VO
CL
Vcc/2
0V
t PLZ
Vcc
0.5 V
50%
NOTE
B
50 W
VOL
NOTE A
ISOLATION BARRIER
3V
Vcc
IN
Input
Generator
VI
OUT
VO
Vcc/2
VI
Vcc/2
0V
t PZH
EN
50 W
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
8
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ISO7230A
ISO7231A
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC1
0V
or
VCC1
IN
ISOLATION BARRIER
VI
VCC1
VI
OUT
2.7 V
VO
0V
VOH
tfs
CL
NOTE B
VO
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC1
VCC2
S1
ISOLATION BARRIER
C = 0.1 mF± 1%
IN
GND1
C = 0.1 mF± 1%
OUT
Pass-fail criteria:
Output must
remain stable
NOTE B
VOH or VOL
GND2
VCM
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
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ISO7230A
ISO7231A
SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
7.7
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
0.008
mm
Minimum Internal Gap (Internal
Clearance)
RIO
Distance through the insulation
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
>1011
Ω
Ω
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
2
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
pF
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice
Recognized under 1577
Component Recognition
Program (1)
File Number: 40016131
File Number: 1698195
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
DEVICE I/O SCHEMATICS
Enable
VCC2
Output
Input
VCC2
VCC1
VCC2
VCC1
VCC2
1 MW
500 W
IN
EN
8W
500 W
OUT
13 W
1 MW
10
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Product Folder Link(s): ISO7230A ISO7231A
ISO7230A
ISO7231A
www.ti.com ........................................................................................................................................................................................................ SLLS906 – MAY 2008
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Low-K Thermal Resistance (1)
168
High-K Thermal Resistance
96.1
UNIT
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
61
°C/W
θJC
Junction-to-Case Thermal Resistance
48
°C/W
PD
Device Power Dissipation
(1)
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
TYPICAL CHARACTERISTIC CURVES
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
1.4
3
5 V Vth+
2.9
VCC1 - Failsafe Threshold - V
Input Voltage Threshold - V
1.35
1.3
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low-K Board
1.15
5 V Vth1.1
2.8
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
2.7
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
1.05
3.3 V Vth1
-40
-25
-10
2.1
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
2
-40
125
-10
5
20
35
50
65
80
95
110
125
TA - Free-Air Temperature - °C
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
50
VCC = 5 V
Load = 15 pF,
TA = 25°C
Load = 15 pF,
TA = 25°C
45
40
IO - Output Current - mA
40
IO - Output Current - mA
-25
VCC = 3.3 V
30
20
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
10
5
0
0
0
2
4
VO - Output Voltage - V
6
0
1
Figure 7.
2
3
VO - Output Voltage - V
4
5
Figure 8.
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Product Folder Link(s): ISO7230A ISO7231A
11
ISO7230A
ISO7231A
SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
APPLICATION INFORMATION
20 mm
max. from
VCC1
VCC1
20 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
NC
6
11
NC
7
10
8
9
GND2
GND1
NC
EN
GND2
GND1
ISO7230
Figure 9. Typical ISO7230 Application Circuit
LIFE EXPECTANCY vs WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 10. Time Dependant Dielectric Breakdown Testing Results
12
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Product Folder Link(s): ISO7230A ISO7231A
ISO7230A
ISO7231A
www.ti.com ........................................................................................................................................................................................................ SLLS906 – MAY 2008
PRODUCT NOTIFICATION
An ISO723xA anomaly occurs when a negative-going pulse below the specified 1 µs minimum bit width is input
to the device. The output locks in a logic-low condition until the next rising edge occurs after a 1 µs period.
Positive noise edges in pulses of less than the minimum specified 1 µs have no effect on the device, and are
properly filtered.
To prevent noise from interfering with ISO723xA performance, it is recommended that an appropriately sized
capacitor be placed on each input of the device
Figure 11. ISO723xA Anomaly
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13
PACKAGE MATERIALS INFORMATION
www.ti.com
28-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7230ADWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
ISO7231ADWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-May-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7230ADWR
SOIC
DW
16
2000
358.0
335.0
35.0
ISO7231ADWR
SOIC
DW
16
2000
358.0
335.0
35.0
Pack Materials-Page 2
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