Revised November 1999 74ABT2952 Octal Registered Transceiver General Description Features The ABT2952 is an octal registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA. ■ Separate clock, clock enable and 3-STATE output enable provided for each register ■ A and B output sink capability of 64 mA source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability Ordering Code: Order Number 74ABT2952CSC Package Number Package Description M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT2952CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT2952CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names A0–A7 Description A-Register Inputs/B-Register 3-STATE Outputs B0–B7 B-Register Inputs/A-Register 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS010969 OEA Output Enable A-Register CPA A-Register Clock CEA A-Register Clock Enable OEB Output Enable B-Register CPB B-Register Clock CEB B-Register Clock Enable www.fairchildsemi.com 74ABT2952 Octal Registered Transceiver January 1992 74ABT2952 Truth Table Output Control Register Function Table (Applies to A or B Register) Internal Output OE Inputs Function D CP CE Q X H NC Hold Data L L Load Data L H H X Z Disable Outputs X L L L Enable Outputs L L H H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance = LOW-to-HIGH Transition NC = No Change Block Diagram www.fairchildsemi.com Internal Function Q 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input Voltage Applied to Any Output 20 mV/ns Clock Input 100 mV/ns in the Disable or −0.5V to +5.5V Power-Off State −0.5V to VCC in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL Output LOW Voltage VID Input Leakage Test IIH Input HIGH Current VCC V Conditions Recognized HIGH Signal Recognized LOW Signal Min IIN = −18 mA (Non I/O Pins) IOH = −3 mA (An, Bn) 2.5 IOH = −32 mA (An, Bn) 2.0 0.55 4.75 V Min IOL = 64 mA (An, B n) V 0.0 IID = 1.9 µA (Non-I/O Pins) All Other Pins Grounded 1 µA Max 7 µA Max µA Max 1 IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) 100 IIL Input LOW Current −1 −1 µA Max VIN = 2.7V (Non-I/O Pins) (Note 3) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) VIN = 0.5V (Non-I/O Pins) (Note 3) VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current 10 µA 0V–5.5V VOUT = 2.7V (An, Bn); IIL + IOZL Output Leakage Current −10 µA 0V–5.5V VOUT = 0.5V (An, Bn); IOS Output Short-Circuit Current −275 mA ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn) IZZ Bus Drainage Test 100 µA 0.0V VOUT = 5.5V (An, Bn); ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max Outputs 3-STATE; ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V; All Others ICCD Dynamic ICC 0.18 mA/MHz Max Outputs Open OEA or OEB = 2.0V OEA or OEB = 2.0V −100 Max VOUT = 0V (An, Bn) All Others GND All Others GND at VCC or GND No Load OEA or OEB = GND, (Note 4) Non-I/O = GND or VCC One Bit toggling, 50% duty cycle (Note 4) Note 3: Guaranteed, but not tested. Note 4: For 8-bit toggling, ICCD < 1.4 mA/MHz. 3 www.fairchildsemi.com 74ABT2952 Absolute Maximum Ratings(Note 1) 74ABT2952 DC Electrical Characteristics (SOIC Package) Conditions Symbol Parameter Min Typ Max Units VCC 0.6 0.8 V 5.0 CL = 50 pF, RL = 500Ω TA = 25°C (Note 5) VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL −1.2 −1.0 V 5.0 TA = 25°C (Note 5) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA = 25°C (Note 7) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 7) 1.2 0.8 Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Package) Symbol Parameter Min TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Typ Max Min Units Max fMAX Maximum Clock Frequency 200 200 tPLH Propagation Delay 1.5 3.4 5.3 1.5 5.3 MHz tPHL CPA or CPB to 1.5 3.6 5.3 1.5 5.3 ns An or Bn tPZH Output Enable Time 1.5 3.2 5.5 1.5 5.5 tPZL OEA or OEB to 1.5 3.5 5.5 1.5 5.5 ns An or Bn tPHZ Output Disable Time 1.5 3.6 6.0 1.5 6.0 tPLZ OEA or OEB to 1.5 3.2 6.0 1.5 6.0 ns An or Bn AC Operating Requirements Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, HIGH 2.5 2.5 ts(L) or LOW An or Bn 2.5 2.5 Units Max ns to CPA or CPB tH(H) Hold Time, HIGH 1.5 1.5 tH(L) or LOW An or Bn 1.5 1.5 tS(H) Setup Time, HIGH 2.5 2.5 tS(L) or LOW CEA or CEB 2.5 2.5 ns to CPA or CPB ns to CPA or CPB tH(H) Hold Time, HIGH 1.5 1.5 tH(L) or LOW CEA or CEB 1.5 1.5 tW(H) Pulse Width, 3.0 3.0 tW(L) HIGH or LOW 3.0 3.0 ns to CPA or CPB CPA or CPB www.fairchildsemi.com 4 ns (SOIC Package) Symbol Parameter TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching (Note 9) 8 Outputs Switching (Note 8) Units (Note 10) Min Max Min Max Min Max tPLH Propagation Delay 1.5 6.0 2.0 8.0 2.5 10.5 tPHL CPA or CPB to An or Bn 1.5 6.0 2.0 8.0 2.5 10.5 tPZH Output Enable Time 1.5 6.0 2.0 8.0 2.5 11.5 tPZL OEA or OEB to An or Bn 1.5 6.0 2.0 8.0 2.5 11.5 tPHZ Output Disable Time 1.5 6.0 tPZL OEA or OEB to An or Bn 1.5 6.0 (Note 11) ns ns (Note 11) ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Skew (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 12) (Note 13) Max Max 1.0 1.5 ns 1.0 2.0 ns 2.0 4.5 ns 2.1 4.5 ns 2.5 5.0 ns Parameter tOSHL Pin to Pin Skew (Note 14) HL Transitions tOSLH Pin to Pin Skew (Note 14) LH Transitions tPS Duty Cycle (Note 15) LH–HL Skew tOST Pin to Pin Skew (Note 14) LH/HL Transitions tPV Device to Device Skew (Note 16) LH/HL Transitions Units Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-toLOW (tOST ). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5 pF VCC = 0V (Non I/O Pins) CI/O (Note 17) Output Capacitance 11 pF VCC = 5.0V (An, Bn) Note 17: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74ABT2952 Extended AC Electrical Characteristics 74ABT2952 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT2952 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 7 www.fairchildsemi.com 74ABT2952 Octal Registered Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8