TC74ACT299P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT299P,TC74ACT299F 8-Bit PIPO Shift Register with Asynchronous Clear TC74ACT299P The TC74ACT299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TLL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA) controlled by the two selection inputs (S0, S1). When one or both enable ( G1 , G2 ) are high, the eight I/O outputs are forced to the high-impedance state; however, sequential operation or clearing of the register is not affected. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74ACT299F Features (Note 1)(Note 2) • High speed: fmax = 130 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • Compatible with TTL outputs: VIL = 0.8 V (max) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) • Capability of driving 50 Ω transmission lines. Balanced propagation delays: tpLH ∼ − tpHL • Pin and function compatible with 74F299 Weight DIP20-P-300-2.54A SOP20-P-300-1.27A : 1.30 g (typ.) : 0.22 g (typ.) VIH = 2.0 V (min) Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull down resistors. Pin Assignment 1 2007-10-01 TC74ACT299P/F IEC Logic Symbol Truth Table Inputs/ Outputs Inputs Mode CLR Z Function Select Outputs Control S1 S0 G1 (Note) G2 (Note) Outputs Serial CK SL SR A/QA H/QH QA’ QH’ L H H X X X X X Z Z L L L L X L L X X X L L L L L X L L L X X X L L L L Hold H L L L L X X X QA0 QH0 QA0 QH0 Shift H L H L L X H H QGn H QGn Right H L H L L X L L QGn L QGn Shift H H L L L H X QBn H QBn H Left H H L L L L X QBn L QBn L Load H H H X X X X a h a h Clear Note: When one or both output controls are high, the eight input/output terminals are in the high-impedance state; however sequential or clearing of the register is not affected. Z: High impedance Qn0: The level of Qn before the indicated steady-state input conditions were established. Qnn: The level of Qn before the most recent active transition indicated by ↓ or ↑. a, h: The level of the steady-state inputs A, H, respectively. X: Don’t care 2 2007-10-01 TC74ACT299P/F Timing Chart System Diagram (Note) Note: (Note) (Note) (Note) (Note) (Note) Equivalent circuits 3 2007-10-01 TC74ACT299P/F Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to VCC + 0.5 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK ±20 mA Output diode current IOK ±50 mA DC output current IOUT ±50 mA DC VCC/ground current ICC ±250 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW Storage temperature Tstg −65 to 150 °C DC output voltage Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 4.5 to 5.5 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V Operating temperature Topr −40 to 85 °C Input rise and fall time dt/dV 0 to 10 ns/V Output voltage Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 4 2007-10-01 TC74ACT299P/F Electrical Characteristics DC Characteristics Ta = −40 to 85°C Ta = 25°C Test Condition Characteristics Symbol VCC (V) Min Typ. Max Min Max Unit High-level input voltage VIH ⎯ 4.5 to 5.5 2.0 ⎯ ⎯ 2.0 ⎯ V Low-level input voltage VIL ⎯ 4.5 to 5.5 ⎯ ⎯ 0.8 ⎯ 0.8 V 4.5 4.4 4.5 ⎯ 4.4 ⎯ 4.5 3.94 ⎯ ⎯ 3.80 ⎯ High-level output voltage VOH IOH = −50 μA VIN = VIH or IOH = −24 mA VIL IOH = −75 mA (Note) IOL = 50 μA Low-level output voltage VOL VIN = VIH or IOL = 24 mA VIL IOL = 75 mA (Note) VIN = VIH or VIL V 5.5 ⎯ ⎯ ⎯ 3.85 ⎯ 4.5 ⎯ 0.0 0.1 ⎯ 0.1 4.5 ⎯ ⎯ 0.36 ⎯ 0.44 5.5 ⎯ ⎯ ⎯ ⎯ 1.65 5.5 ⎯ ⎯ ±0.5 ⎯ ±5.0 μA V 3-state output off-state current IOZ Input leakage current IIN VIN = VCC or GND 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA ICC VIN = VCC or GND 5.5 ⎯ ⎯ 8.0 ⎯ 80.0 μA 5.5 ⎯ ⎯ 1.35 ⎯ 1.5 mA Ta = −40 to 85°C Unit Quiescent supply current Note: IC VOUT = VCC or GND Per input: VIN = 3.4 V Other input: VCC or GND This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol VCC (V) Typ. Limit Limit ⎯ 5.0 ± 0.5 ⎯ 5.0 5.0 ns tW (L) ⎯ 5.0 ± 0.5 ⎯ 5.0 5.0 ns ts ⎯ 5.0 ± 0.5 ⎯ 3.5 3.5 ns ts ⎯ 5.0 ± 0.5 ⎯ 6.0 6.5 ns th ⎯ 5.0 ± 0.5 ⎯ 2.0 2.0 ns th ⎯ 5.0 ± 0.5 ⎯ 0.0 0.0 ns trem ⎯ 5.0 ± 0.5 ⎯ 2.0 2.0 ns Minimum pulse width tW (L) (CK) tW (H) Minimum pulse width ( CLR ) Minimum set-up time (SL, SR, A~H) Minimum set-up time (S0, S1) Minimum hold time (SL, SR, A~H) Minimum hold time (S0, S1) Minimum removal time ( CLR ) Ta = 25°C Test Condition 5 2007-10-01 TC74ACT299P/F AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns) Characteristics Symbol Propagation delay time tpLH (CK-QA’, QH’) tpHL Propagation delay time tpHL Ta = −40 to 85°C Ta = 25°C Test Condition Unit VCC (V) Min Typ. Max Min Max ⎯ 5.0 ± 0.5 ⎯ 7.2 10.5 1.0 12.0 ns ⎯ 5.0 ± 0.5 ⎯ 6.0 10.0 1.0 11.5 ns ⎯ 5.0 ± 0.5 ⎯ 7.4 11.4 1.0 13.0 ns ⎯ 5.0 ± 0.5 ⎯ 6.3 10.5 1.0 12.0 ns ⎯ 5.0 ± 0.5 ⎯ 7.4 11.4 1.0 13.0 ns ⎯ 5.0 ± 0.5 ⎯ 7.2 9.6 1.0 11.0 ns ⎯ 5.0 ± 0.5 80 120 ⎯ 80 ⎯ MHz ( CLR -QA’, QH’) Propagation delay time tpLH (CK-QA~QH) tpHL Propagation delay time tpHL ( CLR -QA~QH) Output enable time Output disable time tpZL tpZH tpLZ tpHZ Maximum clock frequency fmax Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF Bus input capacitance CI/O ⎯ ⎯ 13 ⎯ ⎯ ⎯ pF Power dissipation capacitance CPD ⎯ ⎯ 160 ⎯ ⎯ ⎯ pF Note: (Note) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC 6 2007-10-01 TC74ACT299P/F Package Dimensions Weight: 1.30 g (typ.) 7 2007-10-01 TC74ACT299P/F Package Dimensions Weight: 0.22 g (typ.) 8 2007-10-01 TC74ACT299P/F RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. 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