Sharp LH28F008SAN-12 8m (1m ã 8) flash memory Datasheet

LH28F008SA
FEATURES
8M (1M × 8) Flash Memory
40-PIN TSOP
TOP VIEW
• Very High-Performance Read
– 85 ns Maximum Access Time
• High-Density Symmetrically Blocked
Architecture
– Sixteen 64K Blocks
• Extended Cycling Capability
– 100,000 Block Erase Cycles
– 1.6 Million Block Erase Cycles per Chip
• Automated Byte Write and Block Erase
– Command User Interface
– Status Register
• System Performance Enhancements
– RY /» BY » Status Output
– Erase Suspend Capability
• Deep-Powerdown Mode
– 0.20 µA ICC Typical
• SRAM-Compatible Write Interface
• Hardware Data Protection Feature
– Erase/Write Lockout during
Power Transitions
• Independent Software Vendor Support
A19
1
40
NC
A18
2
39
NC
A17
3
38
WE
A16
4
37
OE
A15
5
36
RY/BY
A14
6
35
DQ7
A13
7
34
DQ6
A12
8
33
DQ5
CE
9
32
DQ4
VCC
10
31
VCC
VPP
11
30
GND
PWD
12
29
GND
A11
13
28
DQ3
A10
14
27
DQ2
A9
15
26
DQ1
A8
16
25
DQ0
A7
17
24
A0
A6
18
23
A1
A5
19
22
A2
A4
20
21
A3
28F008SA-1
Figure 1. 40-Pin TSOP Configuration
– Microsoft Flash File System™ (FFS)
• ETOX™ Nonvolatile Flash Technology
– 12 V Byte Write/Block Erase
• Industry Standard Packaging
– 40-Pin 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
– 44-Pin 600-mil SOP Package
1
LH28F008SA
8M (1M × 8) Flash Memory
44-PIN SOP
TOP VIEW
VPP
1
44
VCC
RP
2
43
CE
A11
3
42
A12
A10
4
41
A13
A9
5
40
A14
A8
6
39
A15
A7
7
38
A16
A6
8
37
A17
A5
9
36
A18
A4
10
35
A19
NC
11
34
NC
NC
12
33
NC
A3
13
32
NC
A2
14
31
NC
A1
15
30
WE
A0
16
29
OE
DQ0
17
28
RY/BY
DQ1
18
27
DQ7
DQ2
19
26
DQ6
DQ3
20
25
DQ5
GND
21
24
DQ4
GND
22
23
VCC
SHARP’s LH28F008SA employs advanced CMOS
circuitry for systems requiring low power consumption
and noise immunity. Its 85 ns access time provides
superior performance when compared with magnetic
storage media. A deep powerdown mode lowers power
consumption to 1 µW typical through VCC, crucial in portable computing, handheld instrumentation and other
low-power applications. The PWD power control input
also provides absolute data protection during system
power up/down.
DESCRIPTION
28F008SA-16
Figure 2. 44-Pin SOP Configuration
INTRODUCTION
SHARP’S LH28F008SA 8M Flash File™ Memory is
the highest density nonvolatile read/write solution for
solid state storage. The LH28F008SA’s extended
cycling, symmetrically blocked architecture, fast access
time, write automation and low power consumption provide a more reliable, lower power, lighter weight and
higher performance alternative to traditional rotating disk
technology. The LH28F008SA brings new capabilities
to portable computing. Application and operating system software stored in resident flash memory arrays
provide instant-on rapid execute-in-place and protection from obsolescence through in-system software
updates. Resident software also extends system battery life and increases relaibility by reducing disk drive
accesses.
For high density data acquisition applications, the
LH28F008SA offers a more cost-effective and reliable
alternative to SRAM and battery. Traditional high
density embedded applications, such as telecommunications, can take advantage of the LH28F008SA’s
nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software
designs.
2
The LH28F008SA is offered in 40-pin TSOP (standard) package. Pin assignments simplify board layout
when integrating multiple devices in a flash memory
array or subsystem. This device uses an integrated
Command User Interface and state machine for simplified block erasure and byte write. The LH28F008SA
memory map consists of 16 separately erasable
64K blocks.
The LH28F008SA is a high-performance 8M
(8,388,608 bit) memory organized at 1M (1,048,576
bytes) of 8 bits each. Sixteen 64K (65,536 Byte) blocks
are included on the LH28F008SA. A memory map is
shown in Figure 4 of this specification. A block erase
operation erases one of the sixteen blocks of memory
in typically 1.6 seconds, independent of the remaining
blocks. Each block can be independently erased and
written 100,000 cyles. Erase Suspend mode allows system software to suspend block erase to read data or
execute code from any other block of the LH28F008SA.
The LH28F008SA is available in the 40-pin TSOP
(Thin Small Outline Package, 1.2 mm thick) package.
Pinouts are shown in Figure 1 of this specification.
The Command User Interface serves as the interface between the microprocessor or microcontroller and
the internal operation of the LH28F008SA.
Byte Write and Block Erase Automation allow byte
write and block erase operations to be executed using
a two-write command sequence to the Command User
Interface. The internal Write State Machine (WSM)
automatically executes the algorithms and timings necessary for byte write and block erase operations,
including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is
performed in byte increments typically within 9 µs, an
80% improvement over current flash memory products.
IPP byte write and block erase currents are 10 mA typical, 30 mA maximum. VPP byte write and block erase
voltage is 11.4 V to 12.5 V.
The Status Register indicates the status of the WSM
and when the WSM successfully completes the desired
byte write or block erase operation.
8M (1M × 8) Flash Memory
LH28F008SA
DQ0 - DQ7
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
OUTPUT
MULTIPLEXER
STATUS
REGISTER
I/O LOGIC
DATA
REGISTER
DATA
COMPARATOR
A0 - A19
Y-GATING
INPUT
BUFFER
COMMAND
USER
INTERFACE
WRITE STATE
MACHINE
CE
WE
OE
PWD
RY/BY
Y-DECODER
X-DECODER
...
ADDRESS
LATCH
16 64KB BLOCKS
ADDRESS
COUNTER
PROGRAM/
ERASE
VOLTAGE
SWITCH
VPP
VCC
GND
28F008SA-2
Figure 3. LH28F008SA Block Diagram
3
LH28F008SA
8M (1M × 8) Flash Memory
PIN DESCRIPTION
SYMBOL
TYPE
INPUT
ADDRESS INPUTS: For memory addresses. Addresses are internally latched during
a write cycle.
INPUT/OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during Command User Interface
write cycles; outputs data during memory array. Status Register and Identifier read
cycles. The data pins are active high and float to tri-state off when the chip is deselected
or the outputs are disabled. Data is internally latched during a write cycle.
CE »
INPUT
CHIP ENABLE: Activates the device’s control logic input buffers, decoders, and
sense amplifiers. CE » is active low: CE » high deselects the memory device and
reduces power consumption to standby levels.
PWD
INPUT
POWERDOWN: Puts the device in deep powerdown mode. PWD is active low; PWD
high gates normal operation. PWD also locks out block erase or byte write
operations when active low, providing data protection during power transitions.
OE »
INPUT
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
read cycle. OE » is active low.
WE
INPUT
WRITE ENABLE: Controls writes to the Command User Interface and array blocks.
WE is active low. Addresses and data are latched on the rising edge of the
WE Pulse.
RY /» BY »
OUTPUT
READY/BUSY: Indicates the status of the internal Write State Machine. When low, it
indicates that the WSM is performing a block erase or byte write operation. RY/» BY »
high indicates that the WSM is ready for new commands, block erase is suspended or
the device is in deep powerdown mode. RY »/BY i» s always active and does NOT float
to tri-state off when the chip is deselected or data outputs are disabled.
VPP
SUPPLY
BLOCK ERASE/BYTE WRITE POWER SUPPLY: for erasing blocks of the array or
writing bytes of each block.
NOTE: With VPP < VPPLMAX, memory contents cannot be altered.
A0 - A19
DQ0 - DQ7
DEVICE POWER SUPPLY: (5 V ±10%, 5 V ±5%)
VCC
GND
4
NAME AND FUNCTION
SUPPLY
GROUND
8M (1M × 8) Flash Memory
LH28F008SA
The RY »/BY » output gives an additional indicator of
WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for
example). Status polling using RY »/BY » minimizes both
CPU overhead and system power consumption. When
low, RY /» BY » indicates that the WSM is performing a block
erase or byte write operation. RY /» BY » high indicates that
the WSM is ready for new commands, block erase is
suspended or the device is in deep power down mode.
MEMORY MAP
Maximum access time is 85 ns (tACC) over the commercial temperature range (0°C to +70°C) and over VCC
supply voltage range (4.5 V to 5.5 V and 4.75 V to
5.25 V). ICC active current (CMOS Read) is 20 mA typical, 35 mA maximum at 8 MHz.
C0000
BFFFF
When the CE » and PWD pins are at VCC, the ICC
CMOS Standby mode is enabled.
90000
8FFFF
A Deep Powerdown mode is enabled when the PWD
pin is at GND, minimizing power consumption and providing write protection. ICC current in deep power down
is 0.20 µA typical. Reset time of 400 ns is required from
PWD switching high until outputs are valid to read
attempts. Equivalently, the device has a wake time of
1 µs from PWD high until writes to the Command User
Interface are recognized by the LH28F008SA. With PWD
at GND, the WSM is reset and the Status Register is
cleared.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
B0000
AFFFF
A0000
9FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
PRINCIPLES OF OPERATION
20000
1FFFF
The LH28F008SA includes on-chip write automation
to manage write and erase functions. The Write State
Machine allows for 100% TTL-level control inputs; fixed
power supplies during block erasure and byte write; and
minimal processor overhead with SRAM like interface
timings.
10000
0FFFF
After initial device powerup, or after return from deep
powerdown mode (see Bus Operations), the
LH28F008SA functions as a read-only memory. Manipulation of external memory-control pins allow array read,
standby and output disable operations. Both Status
Register and intelligent identifiers can also be accessed
through the Command User Interface when VPP = VPPL.
This same subset of operations is also available when
high voltage is applied to the VPP pin. In addition, high
voltage on VPP enables successful block erasure and
byte writing of the device. All functions associated with
altering memory contents - byte write, block erase,
status and intelligent identifier - are accessed via the
Command User Interface and verified through the
Status Register.
00000
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
28F008SA-4
Figure 4. Memory Map
Commands are written using standard microprocessor write timings. Command User Interface contents
serve as input to the WSM, which controls the block
erase and byte write circuitry. Write cycles also internally latch addresses and data needed for byte write or
block erase operations. With the appropriate command
written to the register, standard microprocessor read
timings output array data, access the intelligent identifier codes, or output byte write and block erase status
for verification.
5
LH28F008SA
8M (1M × 8) Flash Memory
12 V
SA0 - SA16
LA17 - LA20
SA1 - SA16
LA17 - LA20
µPLD
WE
FLSHDCS
RD
OE
PRDY
CS1
VGACS
CS2
CTRL
SD0 - SD15
CS3
XCVR
FD0 - FD7
82360SL
CONTROLLER
VPP
OE
RY/BY
WR
WE
DQ0 - DQ7
80386SL PM/IO
VPP
LH28F008SA
CS
TO OTHER
LH28F008SA's
LH28F008SA
CE
PSTART
PCMD
GPIO
RESET
CE
CSH1
SBHE
PW/R
A0 - A19
PWD
SBHE
CSL1
DQ0 - DQ7
LATCH
A0 - A19
RY/BY
SA0
LA21 - LA22
VPP
SWITCH
INT
FD8 - FD15
RY/BY
RESET
PWRGOOD
RD
WR
RY/BY1
RY/BY2
EPLD(s)
RY/BY
FROM OTHER
LH28F008SA's
PWD
PWD
TO OTHER
LH28F008SA
PAIRS
28F008SA-3
Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus
(Including RY »/BY » Masking and Selective Powerdown), for DRAM
Backup during System SUSPEND, Resident O/S and
Applications and Motherboard Solid-State Disk.
6
8M (1M × 8) Flash Memory
LH28F008SA
Data Protection
Interface software to initiate and poll progress of
internal byte write and block erase can be stored in any
of the LH28F008SA blocks. This code is copied to, and
executed from, system RAM during actual flash memory
update. After successful completion of byte write
and/or block erase, code/data reads from the
LH28F008SA are again possible via the Read Array
command. Erase suspend/resume capability allows
system software to suspend block erase to read data
and execute code from any other block.
Depending on the application, the system designer
may choose to make the VPP power switchable (available only when memory byte writes/block erases are
required) or hardwired to VPPH. When VPP =
VPPL, memory contents cannot be altered. The
LH28F008SA Command User interface architecture provides protection from unwanted byte write or block erase
operations even when high voltage is applied to VPP.
Additionally, all functions are disabled whenever VCC is
below the write lockout voltage VLKO, or when PWD is
at VIL. The LH28F008SA accomodates either design
practice and encourages optimization of the processormemory interface.
Command User Interface and
Write Automation
An on-chip state machine controls block erase and
byte write, freeing the system processor for other tasks.
After receiving the Erase Setup and Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the Status Register
and RY »/BY » output. Byte write is similarly controlled, after destination address and expected data are supplied.
The program and erase algorithms of past standard
Flash memories are now regulated by the state machine, including pulse repetition where required and internal verification and margining of data.
The two-step byte write/block erase Command User
Interface write sequence provides additional software
write protection.
BUS OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Read
The LH28F008SA has three read modes. The
memory can be read from any of its blocks, and information can be read from the intelligent identifier or Status Register. VPP can be at either VPPL or VPPH.
Bus Operations
PWD
CE »
OE »
WE
A0
VPP
DQ0 - DQ7
RY »/BY »
NOTE
Read
VIH
VIL
VIL
VIH
X
X
DOUT
X
1, 2, 3
Output Disable
VIH
VIL
VIH
VIH
X
X
High-Z
X
3
Standby
VIH
VIH
X
X
X
X
High-Z
X
3
Deep Power Down
VIL
X
X
X
X
X
High-Z
VOH
Intelligent Identifier (Mfr)
VIH
VIL
VIL
VIH
VIL
X
89H
VOH
Intelligent Identifier (Device)
VIH
VIL
VIL
VIH
VIH
X
A2H
VOH
Write
VIH
VIL
VIH
VIL
X
X
DIN
X
MODE
3, 4, 5
NOTES:
1. Refer to DC Characteristics. When VPP = VPPL, memory contents can be read but not written or erased.
2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH voltages.
3. RY »/BY » is VOL when the Write State Machine is executing internal block erase or byte write algorithms. It is V OH when the WSM is
not busy, in Erase Suspend mode or deep powerdown mode.
4. Command writes involving block erase or byte write are only successfully executed when VPP = VPPH.
5. Refer to the Command Definitions Table for valid DIN during a write operation.
7
LH28F008SA
8M (1M × 8) Flash Memory
The first task is to write the appropriate read mode
command to the Command User Interface (array, intelligent identifier, or Status Register). The LH28F008SA
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown. The
LH28F008SA has four control pins, two of which must
be logically active to obtain data at the outputs. Chip
Enable (CE ») is the device selection control, and when
active enables the selected memory device. Output
Enable (OE ») is the data input/output (DQ0 - DQ7)
direction control, and when active drives data from the
selected memory onto the I/O bus. PWD and WE » must
also be at VIH. Figure 8 illustrates read bus cycle waveforms.
Output Disable
With OE » at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0 - DQ7) are placed
in a high-impedance state.
Standby
CE » at a logic-high level (VIH) places the LH28F008SA
in standby mode. Standby operation disables much of
the LH28F008SA’s circuitry and substantially reduces
device power consumption. The outputs (DQ0 - DQ7)
are placed in a high-impedance state independent of
the status of OE .» If the LH28F008SA is deselected during block erase or byte write, the device will continue
functioning and consuming normal active power until
the operation completes.
Deep Power-Down
The LH28F008SA offers a deep power-down feature,
entered when PWD is at VIL. Current draw through VCC
is 0.20 µA typical in deep powerdown mode, with current draw through VPP typically 0.1 µA. During read
modes, PWD-low deselects the memory, places output
drivers in a high-impedence state and turns off all internal circuits. The LH28F008SA requires time tPHQV (see
AC Characteristics-Read-Only Operations) after return
from powerdown until initial memory access outputs are
valid. After this wakeup interval, normal operation is restored. The Command User interface is reset to Read
Array, and the upper 5 bits of the Status Register are
cleared to value 100,000, upon return to normal operation.
During block erase or byte write modes, PWD low
will abort either operation. Memory contents of the block
being altered are no longer valid as the data will be partially written or erased. Time tPHWL after PWD goes to
logic-high (VIH) is required before another command can
be written.
Command Definitions
BUS
CYCLES
REQ'D
OPER.
ADDRESS
DATA
Read Array/Reset
1
Write
X
FFH
Intelligent Identifier
3
Write
X
90H
Read
IA
IID
2, 3, 4
Read Status Register
2
Write
X
70H
Read
X
SRD
3
Clear Status Register
1
Write
X
50H
Erase Setup/Erase Confirm
2
Write
BA
20H
Write
BA
D0H
2
Erase Suspend/Erase Resume
2
Write
X
B0H
Write
X
D0H
Byte Write Setup/Write
2
Write
WA
40H
Write
WD
WD
2, 3, 5
Alternate Byte Write Setup/Write
2
Write
WA
10H
Write
WD
WD
2, 3, 5
COMMAND
FIRST BUS CYCLE
SECOND BUS CYCLE
NOTE
OPER.
ADDRESS
DATA
1
NOTES:
1. Bus operations are defined in Bus Operations Table.
2. IA = Identifier Address: D0H for manufacturer code, 01H for device code.
BA = Address within the block being erased.
WA = Address of memory location to be written.
3. SRD = Data read from Status Register. See Status Register Definitions Table for a description of the Status Register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE ».
IID = Data read from intelligent identifiers.
4. Following the intelligent identifier command, two read operations access manufacture and device codes.
5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
6. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
8
8M (1M × 8) Flash Memory
LH28F008SA
Intelligent Identifier Operation
The intelligent identifier operation outputs the manufacturer code 89H; and the device code, A2H for the
LH28F008SA. The system CPU can then automatically
match the device with its proper block erase and byte
write algorithms.
The manufacturer and device-codes are read via the
Command User Interface. Following a write of 90H to
the Command User Interface, a read from address
location 00000H outputs the manufacturer code (89H).
A read from address 00001H outputs the device code
(A2H). It is not necessary to have high voltage applied
to VPP to read the intelligent identifiers from the Command User Interface.
data information needed to execute the command. Erase
Setup and Erase Confirm commands require both
appropriate command data and an address within the
block to be erased. The Byte Write Setup command
requires both appropriate command data and the address of the location to be written, while the Byte Write
command consists of the data to be written and the
address of the location to be written.
The Command User Interface is written by bringing
WE » to a logic-low level (VIL) while CE » is low. Addresses
and data are latched on the rising edge of WE ». Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the AC Waveforms for Write Operations, Figure 9, for specific timing
parameters.
Write
Writes to the Command User Interface enable reading of device data and intelligent identifiers. They also
control inspection and clearing of the Status Register.
Additionally, when VPP = VPPH, the Command User
Interface controls block erasure and byte write. The contents of the interface register serve as input to the internal state machine.
The Command User Interface itself does not occupy
an addressable memory location. The interface register
is a latch used to store the command and address and
COMMAND DEFINITIONS
When VPPL is applied to the VPP pin, read operations
from the Status Register, intelligent identifiers, or array
blocks are enabled. Placing VPPH on VPP enables successful byte write and block erase operations as well.
Device operations are selected by writing specific
commands into the Command User Interface. Command
Definitions Table defines the LH28F008SA commands.
Status Register Definitions
WSMS
ESS
ES
BWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
SR.7
= WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6
= ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
SR.5
= ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4
= BYTE WRITE STATUS (BWS)
1 = Error in Byte Write
0 = Successful Byte Write
SR.3
= VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
NOTES:
1. RY »/BY » or the Write State Machine Status bit must first be
checked to determine byte write or block erase operation,
before the Byte Write or Erase Status bit are checked to
success.
2. If the Byte Write AND Erase Status bits are set to '1's
during a block erase attempt, an improper command sequence was entered. Attempt the operation again.
3. If VPP low status is detected, the Status Register must be
cleared before another byte write or block erase operation
is attempted. The VPP Status bit, unlike an A/D converter,
does not provide continuous indication of VPP level. The
WSM interrogates the VPP level only after the byte write or
block erase command sequences have been entered and
informs the system if VPP has not been switched on. The
VPP Status bit is not gauranteed to report accurate feedback between VPPL and VPPH.
4. SR.2 - SR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the Status Register.
9
LH28F008SA
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the LH28F008SA defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microprocessor
read cycles retrieve array data. The device remains enabled for reads until the Command User Interface contents are altered. Once the internal Write State Machine
has started a block erase or byte write operation, the
device will not recognize the Read Array command, until
the WSM has completed its operation. The Read Array
command is functional when VPP = VPPL or VPPH.
Intelligent Identifier Command
The LH28F008SA contains an intelligent identifier
operation, initiated by writing 90H into the Command
User Interface. Following the command write, a read
cycle from address 00000H retrieves the manufacturer
code of 89H. A read cycle from address 00001H
returns the device code of A2H. To terminate the operation, it is necessary to write another valid command into
the register. Like the Read Array command, the intelligent identifier command is functional when VPP = VPPL
or VPPH.
Read Status Register Command
The LH28F008SA contains a Status Register which
may be read to determine when a byte write or block
erase operation is complete, and whether that operation completed successfully. The Status Register may
be read at any time by writing the Read Status Register
command (70H) to the Command User Interface. After
writing this command, all subsequent read operations
output data from the Status Register, until another valid
command is written to the Command User Interface.
The contents of the Status Register are latched on the
falling edge of OE » or CE », whichever occurs last in the
read cycle. OE » or CE » must to toggled to VIH before
further reads to update the Status Register latch.
The Read Status Register command functions when
VPP = VPPL or VPPH.
Clear Status Register Command
The Erase Status and Byte Write Status bits are set
to '1's by the Write State Machine and can only be reset
by the Clear Status Register Command. These bits
indicate various failure conditions (see Status Register
Definitions). By allowing system software to control the
resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or
erasing multiple blocks in sequence). The Status Register may then be polled to determine if an error
occurred during that sequence. This adds flexibility to
the way the device may be used.
10
8M (1M × 8) Flash Memory
Additionally, the VPP Status bit (SR.3) MUST be reset by system software before further byte writes or block
erases are attempted. To clear the Status Register, the
Clear Status Register command (50H) is written to the
Command User Interface. The Clear Status Register
command is functional when VPP = VPPL or VPPH.
Erase Setup/Erase Confirm Commands
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup command (20H) is first written to the Command User Interface, followed by the Erase Confirm command (D0H).
These commands require both appropriate sequencing and an address within the block to be erased to FFH.
Block preconditioning, erase and verify are all handled
internally by the Write State Machine, invisible to the
system. After the two-command erase sequence is written to it, the LH28F008SA automatically outputs Status
Register data when read (see Block Erase Flowchart).
The CPU can detect the completion of the erase event
by analyzing the output of the RY »/BY » pin, or the WSM
Status bit of the Status Register.
When erase is completed, the Erase Status bit should
be checked. If erase error is detected, the Status Register should be cleared. The Command User Interface
remains in Read Status Register mode until further commands are issued to it.
This two-step sequence of set-up followed by
execution insures that memory contents are not
accidentially erased. Also, reliable block erasure can only
occur when VPP = VPPH. In the absence of this high
voltage, memory contents are protected against erasure. If block erase is attempted while VPP = VPPL, the
VPP Status bit will be set to '1'. Erase attempts while
VPPL < VPP < VPPH produce spurious results and should
not be attempted.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows block erase
interruption in order to read data from another block of
memory. Once the erase process starts, writing the
Erase Suspend command (B0H) to the Command User
Interface requests that the WSM suspend the erase
sequence at a predetermined point in the erase algorithm. The LH28F008SA continues to output Status
Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase
Suspend Status bits will determined when the erase
operation has been suspended (both will be set to '1').
RY »/BY » will also transition to VOH.
8M (1M × 8) Flash Memory
At this point, a Read Array command can be written
to the Command User Interface to read data from blocks
other than that which is suspended. The only other valid
commands at this time are Read Status Register (70H)
and Erase Resume (D0H), at which time the WSM will
continue with the erase process. The Erase Suspend
Status and WSM Status bits of the Status Register will
be automatically cleared and RY »/BY » will return to VOL.
After the Erase Resume command is written to it, the
LH28F008SA automatically outputs Status Register data
when read (see Erase Suspend/Resume
Flowchart). V PP must remain at V PPH while the
LH28F008SA is in Erase Suspend.
Byte Write Setup/Write Commands
Byte write is executed by a two-command sequence.
The Byte Write Setup command (40H) is written to the
Command User Interface, followed by a second write
specifying the address and data (latched on the rising
edge of WE ») to be written. The WSM then takes over,
controlling the byte write and write verify algorithms
internally. After the two-command byte write sequence
is written to it, the LH28F008SA automatically outputs
Status Register data when read (see Byte Write Flowchart). The CPU can detect the completion of the byte
write event by analyzing the output of the RY /» BY » pin, or
the WSM Status bit of the Status Register. Only the Read
Status Register command is valid while byte write is
active.
When byte write is complete, the Byte Write Status
bit should be checked. If byte write error is detected,
the Status Register should be cleared. The internal
WSM verify only detects errors for '1's that do not successfully write to '0's. The Command User Interface remains in Read Status Register mode until further
commands are issued to it. If byte write is attempted
while VPP = VPPL, the VPP Status bit will be set to '1'.
Byte write attempts while VPPL < VPP < VPPH produce
spurious results and should not be attempted.
EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING
The LH28F008SA is designed for 100,000 byte write/
block erase cycles on each of the sixteen 64K blocks.
Low electric fields, advanced oxides and minimal oxide
area per cell subjected to the tunneling electric field
combine to greatly reduce oxide stress and the probability of failure. A 20M solid-state drive using an array
of LH28F008SAs has a MTBF (Mean Time Between
Failure) of 33.3 million hours(1), over 600 times more
reliable than equivalent rotating disk technology.
LH28F008SA
AUTOMATED BYTE WRITE
The LH28F008SA integrates the Quick-Pulse programming algorithm using the Command User Interface,
Status Register and Write State Machine (WSM).
On-chip integration dramatically simplifies system software and provides processor interface timings to the
Command User Interface and Status Register. WSM
operation, internal verifyand V PP high voltage presence
are monitored and reported via the RY »/BY » output and
appropriate Status Register bits. Figure 5 shows a system software flowchart for device byte write. The entire
sequence is performed with VPP at VPPH.
Byte write abort occurs when PWD transitions to VIL,
or VPP drops to VPPL. Although the WSM is halted, byte
data is partially written at the location where byte write
aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value.
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm is now implemented internally, including all preconditioning of block
data. WSM operation, erase success and VPP high voltage presence are monitored and reported through
RY »/BY » and the Status Register. Additionally, if a command other than Erase Confirm is written to the device
following Erase Setup, both the Erase Status and Byte
Write Status bits will be set to '1's. When issuing the
Erase Setup and Erase Confirm commands, they should
be written to an address within the address range of the
block to be erased. Figure 6 shows a system software
flowchart for block erase.
Erase typically takes 1.6 seconds per block.
The Erase Suspend/Erase Resume command
sequence allows suspension of this erase operation to
read data from a block other than that in which erase is
being performed. A system software flowchart is shown
in Figure 7.
The entire sequence is performed with VPP at VPPH.
Abort occurs when PWD transitions to VIL or VPP fails
to VPPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is
required to obtain a fully erased block.
11
LH28F008SA
DESIGN CONSIDERATIONS
Three-Line Output Control
The LH28F008SA will often be used in large memory
arrays. Intel provides three control inputs to accommodate multiple memory connections. Three-line control
provides for:
• Lowest possible memory power dissipation
• Complete assurance that data bus contention will
not occur
To efficiently use these control input, an address decoder should enable CE ,» while OE » should be connected
to all memory devices and the system’s READ control
line. This assures that only selected memory devices
have active outputs while deselected memory devices
are in Standby Mode. Finally, PWD should either be tied
to the system RESET, or connected to VCC if unused.
NOTE:
1. Assumptions: 10K file written every 10 minutes.
(20M array 10K file) = 2,000 file writes before erase required.
(2000 files writes/erase) × (100,000 cycles per LH28F008SA
block) = 200 million file writes. (200 × 106 file writes) × 10
minutes/write) × 1 hr/60 minutes) = 33.3 × 102 MTBF.
RY /» BY » and Byte Write/Block Erase Polling
RY »/BY » is a full CMOS output that provides a hardware method of detecting byte write and block erase
completion. It transitions low time tWHRL after a write or
erase command sequence is written to the
LH28F008SA, and returns to VOH when the WSM has
finished executing the internal algorithm.
RY /» BY » can be connected to the interrupt input of the
system CPU or controller. It is active at all times, not
instated if the LH28F008SA CE» or OE » inputs are brought
to VIH. RY »/BY » is also VOH when the device is in Erase
Suspend or deep powerdown modes.
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System designers are
interested in 3 supply current issues: standby current
levels (ISB), active current levels (ICC) and transient
peaks produced by falling and rising edges of CE .» Transient current magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will supress transient voltage peaks. Each device should have a 0.1 µF
ceramic capacitor connected between each VCC and
GND, and between its VPP and GND. These high frequency, low inherent-inductance capacitors should be
placed as close as possible to package leads. Addition-
12
8M (1M × 8) Flash Memory
ally, for every 8 devices, a 4.7 µF electrolytic capacitor
should be placed at the array’s power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
VPP Trace on Printed Circuit Boards
Writing flash memories, while they reside in the
target system, requires that the printed circuit board
designer pay attention to the VPP power supply trace.
The VPP pin supplies the memory cell current for writing and erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP
Supply traces and decoupling will decrease VPP voltage spikes and overshoots.
VCC, VPP, PWD Transitions and the
Command/Status Registers
Byte write and block erase completion are not guaranteed if VPP drops below VPPH. If the VPP Status bit
of the Status Register (SR.3) is set to '1', a Clear Status
Register command MUST be issued before further byte
write/block erase attempts are allowed by the WSM.
Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to '1's if error is
detected. PWD transitions to VIL during byte write and
block erase also abort the operations. Data is partially
altered in either case, and the command sequence must
be repeated after normal operation is restored. Device
poweroff, or PWD transitions to VIL, clear the Status
Register to initial value 10,000 for the upper 5 bits.
The Command User Interface latches commands as
issued by system software and is not altered by VPP or
CE » transitions or WSM actions. Its state upon power
up, after exit from deep powerdown or after VCC transitions below VLKO, is Read Array Mode.
After byte write or block erase is complete, even
after VPP transitions down to VPPL, the Command User
Interface must be reset to Read Array mode via the Read
Array command if access to the memory array is
desired.
Power Up/Down Protection
The LH28F008SA is designed to offer protection
against accidental block erasure or byte writing during
power transitions. Upon power-up, the LH28F008SA is
indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required.
Internal circuitry in the LH28F008SA ensures that the
Command User Interface is reset to the Read Array
mode on power up.
8M (1M × 8) Flash Memory
LH28F008SA
START
BUS
OPERATION
WRITE 40H (10H),
BYTE ADDRESS
WRITE BYTE
ADDRESS/DATA
COMMAND
COMMENTS
Write
Byte Write
Setup
Data = 40H (10H)
Addr = Byte to be written
Write
Byte Write
Data to be written
Addr = Byte to be written
Check RY/BY
VOH = Ready, VOL = Busy
Standby/Read
or
WSM
READY?
Read Status Register
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to update
Status Register
NO
YES
Repeat for subsequent bytes.
FULL STATUS
CHECK IF DESIRED
Full status check can be done after each byte or after a
sequence of bytes.
BYTE WRITE
COMPLETED
Write FFH after the last byte write operation to reset the
device to Read Array Mode.
FULL STATUS CHECK PROCEDURE
STATUS REGISTER
DATA READ
(see above)
SR.3 = 0
?
NO
BUS
OPERATION
VPP RANGE
ERROR
YES
SR.4 = 0
?
NO
YES
BYTE WRITE
SUCCESSFUL
BYTE WRITE
ERROR
COMMAND
COMMENTS
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = Byte Write Error
SR.3 must be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
28F008SA-5
Figure 5. Automated Byte Write Flowchart
13
LH28F008SA
8M (1M × 8) Flash Memory
BUS
OPERATION
START
COMMAND
Write
Erase
Setup
Data = 20H
Addr = Within block to be
erased
Write
Erase
Data = D0H
Addr = Within block to be
erased
WRITE 20H
BLOCK ADDRESS
WRITE D0H
BLOCK ADDRESS
Standby/Read
NO
WSM
READY?
NO
Check RY/BY
VOH = Ready, VOL = Busy
ERASE SUSPEND
LOOP
SUSPEND
ERASE?
or
Read Status Register
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to update
Status Register
YES
YES
FULL STATUS
CHECK IF DESIRED
COMMENTS
Repeat for subsequent bytes.
Full status check can be done after each block or after a
sequence of blocks.
BLOCK ERASE
COMPLETED
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
FULL STATUS CHECK PROCEDURE
BUS
OPERATION
STATUS REGISTER
DATA READ
(see above)
SR.3 = 0
?
NO
COMMAND
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Block Erase Error
VPP RANGE
ERROR
YES
SR.4, 5 = 1
?
YES
COMMAND
SEQUENCE
ERROR
SR.3 must be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine.
NO
SR.5 = 0
?
COMMENTS
NO
YES
BLOCK ERASE
SUCCESSFUL
BLOCK ERASE
ERROR
SR.5 is only cleared by the Clear Status Register Command,
in cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
28F008SA-6
Figure 6. Automated Block Erase Flowchart
14
8M (1M × 8) Flash Memory
LH28F008SA
START
BUS
OPERATION
WRITE B0H
COMMAND
Write
Erase
Suspend
Data = B0H
Write
Read
Status Register
Data = 70H
WRITE 70H
Check RY/BY
VOH = Ready,
VOL = Busy or Read
Status Register
Standby/Read
READ STATUS
REGISTER
SR.7 = 1
?
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to Update
Status Register
NO
Standby
Check SR.6
1 = Suspended
YES
Write
SR.6 = 1
?
YES
COMMENTS
Read Array
Data = FFH
NO
Read
ERASE HAS
COMPLETED
Write
Read array data from block
other than that being erased.
Erase Resume
Data = D0H
WRITE FFH
DONE
READING
?
NO
YES
WRITE D0H
CONTINUE ERASE
28F008SA-7
Figure 7. Erase Suspend/Erase Resume Flowchart
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is active.
Since both WE » and CE » must be low for a command
write, driving either to VIH will inhibit writes. The Command User Interface architecture provides an added
level of protection since alteration of memory contents
only occurs after successful completion of the two-setup
command sequences.
Finally, the device is disabled until PWD is brought to
VIH, regardless of the state of its control inputs. This
provides an additional level of memory protection.
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases usable
battery life, because the LH28F008SA does not consume any power to retain code or data when the system is off.
In addition, the LH28F008SA’s deep powerdown
mode ensures extremely low power dissipation even
when system power is applied. For example, portable
PCs and other power sensitive applications, using an
array of LH28F008SAs for solid-state storage, can lower
PWD to VIL in standby or sleep modes, producing negligible power consumption. If access to the LH28F008SA
is again needed, the part can again be read, following
the tPHQV and tPHWL wakeup cycles required after PWD
is first raised back to VIH. See AC Characteristics - ReadOnly and Write Operations and Figures 8 and 9 for more
information.
15
LH28F008SA
8M (1M × 8) Flash Memory
*WARNING: Stressing the device beyond
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read ......................................... 0°C to +70°C1
During Block Erase/Byte Write ............... 0°C to +70°C
Temperature Under Bias ..................... -10°C to +80°C
the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Storage Temperature ......................... -65°C to +125°C
Voltage on Any Pin (except VCC and VPP)
with Respect to GND ..................... -2.0 V to +7.0 V2
VPP Program Voltage with Respect to GND during
Block Erase/Byte Write .............-2.0 V to +14.0 V2, 3
VCC Supply Voltage with Respect
to GND ........................................... -2.0 V to +7.0 V2
Output Short Circuit Current .......................... 100 mA4
OPERATING CONDITIONS
SYMBOL
TA
PARAMETER
MIN.
MAX.
UNITS
0
70.0
°C
Operating Temperature
NOTE
VCC
VCC Supply Voltage (10%)
4.50
5.50
V
5
VCC
VCC Supply Voltage (5%)
4.75
5.25
V
5
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns.
Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.
3. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. 5% VCC specification reference the LH28F008SA-85 in its High Speed configuration, 10% V CC specifications reference the
LH28F008SA-85 in its Standard configuration, and the LH28F008SA-12.
DC CHARACTERISTICS
SYMBOL
PARAMETER
TYP.
MAX.
UNITS
TEST CONDITIONS
NOTE
ILI
Input Load Current
±1.0
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±10.0
µA
VCC = VCC MAX., VOUT = VCC or GND
1
1.0
2.0
mA
VCC = VCC MAX., CE » = PWD = VIH
30
100.0
µA
VCC = VCC MAX.,
CE » = PWD = Vcc ±0.2 V
0.20
1.2
µA
PWD = GND ±0.2
IOUT (RY »/BY ») = 0 mA
20
35.0
mA
VCC = VCC MAX., CE » = GND
f = 8 MHz, IOUT = 0 mA
CMOS Inputs
mA
VCC = VCC MAX., CE » = VIL
f = 8 MHz, IOUT = 0 mA
TTL Inputs
ICCS
VCC Standby Current
ICCD
VCC Deep Power Down
Current
ICCR
VCC Read Current
1, 3
1
1
25
16
MIN.
50.0
8M (1M × 8) Flash Memory
LH28F008SA
DC Characteristics (Continued)
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
ICCW
VCC Byte Write Current
10
30
mA
Byte Write in Progress
1
ICCE
VCC Block Erase Current
10
30
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend Current
5
10
mA
Block Erase Suspended
CE » = VIH
1, 2
±1
±10
µA
VPP ≤ VCC
90
200
µA
VPP ≤ VCC
0.10
5.0
µA
PWD = GND ±0.2 V
1
IPPS
VPP Standby Current
1
IPPD
VPP Deep Power Down Current
IPPW
VPP Byte Write Current
10
30
mA
VPP = VPPH
Byte Write in Progress
1
IPPE
VPP Block Erase Current
10
30
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend Current
90
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VCC = VCC MIN.
IOL = 5.8 mA
3
VOH
Output High Voltage
2.4
V
VCC = VCC MIN.
IOL = 2.5 mA
3
VPPL
VPP during Normal Operations
0.0
6.5
V
VPPH
VPP during Write/Erase
Operations
11.4
12.6
V
VLKO
VCC Erase/Write Lock Voltage
12
2.0
4
V
Capacitance5
TA = 25°C, f = 1MHz
SYMBOL
CIN
COUT
PARAMETER
TYP.
MAX.
UNITS
TEST CONDITIONS
Input Capacitance
6
8
pF
VIN = 0 V
Output Capacitance
8
12
pF
VIN = 0 V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25°C.
These currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device deseleted. If the LH28F008SA is read while in Erase Suspend Mode,
current draw is the sum of ICCES and ICCR.
3. Includes RY »/BY ».
4. Block Erases/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between V PPH and VPPL.
5. Sampled, not 100% tested.
17
LH28F008SA
8M (1M × 8) Flash Memory
AC INPUT/OUTPUT
REFERENCE WAVEFORM1
2.4
INPUT
0.45
2.0
0.8
HIGH SPEED AC INPUT/OUTPUT
REFERENCE WAVEFORM2
2.0
TEST POINTS
0.8
3.0
OUTPUT
INPUT
1.5
1.5 OUTPUT
TEST POINTS
0.0
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0.' Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins, and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
28F008SA-9
28F008SA-8
AC TESTING LOAD CIRCUIT1
HIGH SPEED AC TESTING LOAD CIRCUIT2
1.3 V
1.3 V
1N914
1N914
RL
DEVICE
UNDER
TEST
RL
DEVICE
UNDER
TEST
OUT
CL
NOTE:
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 kΩ
CL
28F008SA-10
NOTES:
1. Testing characteristics for LH28F008SA-85 in Standard
configuration, and LH28F008SA-12.
2. Testing characteristics for LH28F008SA-85 in
High Speed configuration
18
OUT
NOTE:
CL = 30 pF
CL Includes Jig Capacitance
RL = 3.3 kΩ
28F008SA-11
8M (1M × 8) Flash Memory
LH28F008SA
AC CHARACTERISTICS - Read Only Operations1
SYMBOL
PARAMETER
LH28F008SA-854 LH28F008SA-855 LH28F008SA-125
VCC ± 5%
VCC ± 10%
VCC ± 10%
MIN.
MAX.
85
MIN.
MAX.
90
MIN.
UNIT NOTE
MAX.
tAVAV
tAC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
85
90
120
ns
tELQV
tCE
CE » to Output Delay
85
90
120
ns
tPHQV
tPWH
PWD High to Output Delay
400
400
400
ns
tGLQV
tOE
OE » to Output Delay
40
45
50
ns
2
tELQX
tLZ
CE » to Output Low Z
ns
3
tEHQZ
tHZ
CE » High to Output High Z
ns
3
tGLQX
tOLZ
OE » to Output Low Z
ns
3
tGHQZ
tDF
OE » High to Output High Z
ns
3
tOH
Output Hold from
Addresses, CE » or OE »
change, whichever is first
ns
3
0
0
55
0
0
55
0
30
0
ns
0
55
30
0
120
30
0
2
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE » may be delayed up to tCE - tOE after the falling edge of CE » without impact on tCE.
3. Sampled, not 100% tested.
4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load circuits for testing characteristics.
5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
19
LH28F008SA
8M (1M × 8) Flash Memory
VCC POWER-UP
ADDRESSES (A)
DEVICE AND
ADDRESS
STANDBY SELECTION
VIH
VIL
OUTPUTS
ENABLED
DATA
VALID
ADDRESSES STABLE
...
VCC
STANDBY POWER-DOWN
...
tAVAV
CE (E)
VIH
...
VIL
tEHQZ
OE (G)
VIH
VIL
...
tGHQZ
WE (W)
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q)
VOH
...
...
HIGH-Z
VALID OUTPUT
VOL
HIGH-Z
tAVQV
VCC
5.0 V
GND
tPHQV
PWD (P)
VIH
VIL
28F008SA-12
Figure 8. AC Waveform for Read Operations
20
8M (1M × 8) Flash Memory
LH28F008SA
AC CHARACTERISTICS - Write Operations1
SYMBOL
PARAMETER
LH28F008SA-857 LH28F008SA-858 LH28F008SA-128
VCC ± 5%
VCC ± 10%
VCC ± 10%
MIN.
MAX.
MIN.
MAX.
MIN.
UNIT
NOTE
MAX.
tAVAV
tWC
Write Cycle Time
85
90
120
ns
tPHWL
tPS
PWD High Recovery to WE
Going Low
1
1
1
µs
tELWL
tCS
CE » Setup to WE Going Low
10
10
10
ns
tWLWH
tWP
WE Pulse Width
40
40
40
ns
tVPWH
tVPS
VPP Setup to WE Going High
100
100
100
ns
2
tAVWH
tAS
Address Setup to WE
Going High
40
40
40
ns
3
tDVWH
tOS
Data Setup to WE
Going High
40
40
40
ns
tWHDX
tDH
Data Hold from WE High
5
5
5
ns
tWHAX
tAH
Address Hold from WE High
5
5
5
ns
tWHEH
tOH
OE » Hold from WE High
10
10
10
ns
30
30
30
ns
tWHWL
tWHP WE Pulse Width High
tWHRL
WE High to RY »/BY » Going
Low
tWHQV1
Duration of Byte Write
Operation
tWHQV2
Duration of Block Erase
Operation
tWHGL
tQVVL
tVPH
100
100
100
2
4
ns
6
6
6
µs
0.3
0.3
0.3
s
Write Recovery before Read
0
0
0
µs
VPP Hold from Valid SRD,
RY »/BY » High
0
0
0
ns
NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations.
Refer to AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Command Definitions Table for Valid AIN for byte write or block erasure.
4. Refer to Command Definitions Table for valid DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash
memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase).
6. Byte write and block erase durations are measure to completion (SR.7 = 1. RY /» BY » = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0).
7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
21
LH28F008SA
8M (1M × 8) Flash Memory
BLOCK ERASE AND BYTE WRITE PERFORMANCE
LH28F008SA-85
PARAMETER
TYP.1
MIN.
LH28F008SA-12
MAX.
TYP.1
MIN.
UNIT
NOTE
MAX.
Block Erase Time
1.6
10
1.6
10
s
2
Block Write Time
0.6
2.1
0.6
2.1
s
2
NOTES:
1. 25°C, 12.0 VPP.
2. Excludes System-Level Overhead.
VCC
POWER-UP
AND STANDBY
ADDRESSES (A)
WRITE BYTE
WRITE OR
ERASE SETUP
COMMAND
WRITE VALID
ADDRESS AND DATA
(BYTE WRITE) OR
ERASE CONFIRM
COMMAND
AIN
AIN
VIH
VIL
tAVAV
CE (E)
tAVWH
AUTOMATED
BYTE WRITE
OR ERASE
DELAY
READ STATUS
REGISTER DATA
WRITE READ
ARRAY COMMAND
tWHAX
VIH
VIL
tELWL
tWHGL
tWHEH
OE (G)
VIH
VIL
tWHWL
WE (W)
tWHQV1, 2
VIH
VIL
tWLWH
tDVWH
tWHDX
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
tPHWL
RY/BY (R)
PWD (P)
VALID
SRD
DIN
DIN
tWHRL
VOH
VOL
VIH
VIL
tVPWH
tQVVL
VPPH
VPPL
VPP (V) V
IH
VIL
28F008SA-13
Figure 9. AC Waveform for Write Operations
22
8M (1M × 8) Flash Memory
LH28F008SA
ALTERNATIVE CE » - CONTROLLED WRITES
SYMBOL
PARAMETER
LH28F008SA-856 LH28F008SA-857 LH28F008SA-127
VCC ± 5%
VCC ± 10%
VCC ± 10%
MIN.
MAX.
MIN.
MAX.
MIN.
UNIT NOTE
MAX.
tAVAV
tWC
Write Cycle Time
85
90
120
ns
tPHEL
tPS
PWD High Recovery to CE »
Going Low
1
1
1
µs
tWLEL
tWS
WE Setup to CE » Going Low
0
0
0
ns
tELEH
tCP
CE » Pulse Width
50
50
50
ns
tVPEH
tVPS VPP Setup to CE » Going High
100
100
100
ns
2
tAVEH
tAS
Address Setup to CE » Going
High
40
40
40
ns
3
tDVEH
tDS
Data Setup to CE » Going High
40
40
40
ns
4
tEHDX
tDH
Data Hold from CE » High
5
5
5
ns
tEHAX
tAH
Address Hold from CE » High
5
5
5
ns
tEHWH
tWH
WE Hold from CE » High
0
0
0
ns
tEHEL
tEPH CE » Pulse Width High
25
25
25
ns
tEHRL
CE » High to RY »/BY »
Going Low
tEHOV1
Duration of Byte Write
Operation
tEHOV2
Duration of Block Erase
Operation
tEHGL
tQVVL
tVPH
100
100
100
2
ns
6
6
6
µs
5
0.3
0.3
0.3
s
5
Write Recovery before Read
0
0
0
µs
VPP Hold from Valid SRD,
RY »/BY » High
0
0
0
ns
2, 5
NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combinations of CE » and WE ». In systems where
CE » defines the write pulsewidth (within a longer WE » timing waveform), all setup, hold and inactive WE » times should be
measured relative to the CE » waveform.
2. Sampled, not 100% tested.
3. Refer to Command Definitions Table for valid AIN for byte write or block erasure.
4. Refer to Command Definitions Table for valid DIN for byte write or block erasure.
5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY »/BY » = VOH). VPP should be held at VPPH until
determination of byte write/block erase success (SR.3/4/5 = 0).
6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
23
LH28F008SA
8M (1M × 8) Flash Memory
VCC
POWER-UP
AND STANDBY
ADDRESSES (A)
WRITE BYTE
WRITE OR
ERASE SETUP
COMMAND
WRITE VALID
ADDRESS AND DATA
(BYTE WRITE) OR
ERASE CONFIRM
COMMAND
AIN
AIN
VIH
VIL
tAVAV
WE (W)
VIH
VIL
tAVEH
AUTOMATED
BYTE WRITE
OR ERASE
DELAY
READ STATUS
REGISTER DATA
WRITE READ
ARRAY COMMAND
tEHAX
tWLEL
tEHGL
tEHWH
OE (G)
VIH
VIL
tEHEL
CE (E)
tEHQV1, 2
VIH
VIL
tELEH
tDVEH
tEHDX
DATA (D/Q)
VIH
HIGH-Z
VIL
DIN
tPHEL
RY/BY (R)
VOH
VOL
PWD (P)
VIH
VIL
VALID
SRD
DIN
DIN
tEHRL
tVPEH
tQVVL
VPPH
VPPL
VPP (V) V
IH
VIL
28F008SA-14
Figure 10. Alternate AC Waveform for Write Operations
24
8M (1M × 8) Flash Memory
LH28F008SA
44SOP (SOP044-P-0600)
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
44
23
13.40 [0.528]
13.00 [0.512]
1
16.40 [0.646]
15.60 [0.614]
14.40 [0.567]
SEE
DETAIL
22
0.20 [0.008]
0.10 [0.004]
28.40 [1.118]
28.00 [1.102]
2.9 [0.114]
2.5 [0.098]
DETAIL
1.275 [0.050]
0.15 [0.006]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
2.9 [0.114]
2.5 [0.098]
3.25 [0.128]
2.45 [0.096]
0.25 [0.010]
0.05 [0.002]
1.275 [0.050]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
0 - 10°
0.80 [0.031]
44SOP
25
LH28F008SA
8M (1M × 8) Flash Memory
40TSOP (TSOP040-P-1020)
40
1
0.50 [0.020]
TYP.
10.20 [0.402]
9.80 [0.386]
0.25 [0.010]
0.15 [0.006]
20
21
1.10 [0.043]
0.90 [0.035]
SEE DETAIL
1.19
[0.047]
MAX.
0.49 [0.019]
0.39 [0.015]
DETAIL
0.125 [0.005]
18.60 [0.732]
18.20 [0.717]
19.30 [0.760]
18.70 [0.736]
20.30 [0.799]
19.70 [0.776]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
0.49 [0.019]
0.39 [0.015]
0.22 [0.009]
0.02 [0.001]
0 - 10°
0.18 [0.007]
0.08 [0.003]
40TSOP
ORDERING INFORMATION
LH28F008SA
Device Type
X
Package
-##
Speed
85 85
12 120 Access Time (ns)
T 40-pin, 1.2 mm x 10 mm x 20 mm TSOP (Type I) (TSOP040-P-1020)
N 44-pin, 600-mil SOP (SOP044-P-0600)
8M (1M x 8) Flash Memory
Example: LH28F008SAT-85 (8M (1M x 8) Flash Memory, 85 ns, 40-pin TSOP)
28F008SA-15
26
8M (1M × 8) Flash Memory
LH28F008SA
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued July 1994
Reference Code SMT96105
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