Fairchild FST3244MTCX 8-bit bus switch Datasheet

FST3244 — 8-Bit Bus Switch
Features
Description
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The FST3244 switch provides eight-bits of high-speed,
CMOS, TTL-compatible bus switching in a standard
’244 pin-out. The low on resistance allows inputs to be
connected to outputs without adding propagation delay
or generating additional ground bounce noise.
4Ω Switch Connection between Two Ports
Minimal Propagation Delay through the Switch
Low ICC
Zero Bounce in Flow-through Mode
The device is organized as two four-bit switches with
separate /OE inputs. When /OE is LOW, the switch is
ON and port A is connected to port B. When /OE is
HIGH, the switch is OPEN and a high-impedance state
exists between the two ports.
Control Inputs Compatible with TTL Level
Ordering Information
Operating
Part Number Temperature
Range
Packing
Method
Package
FST3244WMX
-40 to +85°C
20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300-inch Wide
Tape and
Reel
FST3244QSCX
-40 to +85°C
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137,
0.150-inch Wide
Tape and
Reel
FST3244MTCX
-40 to +85°C
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, Tape and
4.4mm Wide
Reel
All packages are lead free per JEDEC: J-STD-020B standard.
The Fairchild switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Logic Diagram
1A0
1A3
2
18 1B0
8
12 1B
3
/OE1 1
2A0 11
2A3
17
9 2B
0
3
2B3
/OE2 19
Figure 1. Logic Diagram
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
FST3244 — 8-Bit Bus Switch
March 2008
FST3244 — 8-Bit Bus Switch
Pin Configurations
/OE1
1
20
VCC
1A0
2
19
/OE2
2B3
3
18
1B0
1A1
4
17
2A3
2B2
5
16
1B1
1A2
6
15
2A2
2B1
7
14
1B2
1A3
8
13
2A1
2B0
9
12
1B3
GND
10
11
2A0
Figure 2. Pin Configuration
Pin Descriptions
Pin #
Pin Names
Description
1,19
/OE1, /OE2
Bus Switch Enables
2,4,6,8,11,13,15,17
1A, 2A
Bus A
3,5,7,9,12,14, 16,18
1B, 2B
Bus B
20
VCC
Supply Voltage
10
GND
Ground
Truth Table
Inputs
Inputs/Outputs
/OE1
/OE2
1A, 1B
2A, 2B
LOW
LOW
1A = 1B
2A = 2B
LOW
HIGH
1A = 1B
High Impedance
HIGH
LOW
High Impedance
2A = 2B
HIGH
HIGH
High Impedance
High Impedance
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage
Min.
Max.
Unit
-0.5
7.0
V
VS
DC Switch Voltage
-0.5
7.0
V
VIN
DC Input Voltage
(1)
-0.5
7.0
V
IIK
DC Input Diode Current VIN<0V
-50
mA
DC Output Sink Current
128
mA
DC VCC / GND Current
±100
mA
+150
°C
IOUT
ICC / IGND
TSTG
Storage Temperature Range
-65
FST3244 — 8-Bit Bus Switch
Absolute Maximum Ratings
Note:
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
4.0
5.5
V
VCC
Power Supply Operating
VIN
Input Voltage
0
5.5
V
Output Voltage
0
5.5
V
0
5
0
DC
-40
+85
VOUT
Switch Control Input
tr , tf
Input Rise and Fall Time
TA
Operating Temperature, Free Air
(2)
Switch I/O
ns/V
°C
Note:
2. Unused control inputs must be held HIGH or LOW. They may not float.
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
3
Typical values are at VCC = 5.0V and TA = 25°C.
Symbol
VIK
Parameter
Conditions
Clamp Diode Voltage
VCC (V)
IIN = -18mA
TA=-40 to +85°C
Min.
Typ.
Units
Max.
4.5
-1.2
V
VIH
High-Level Input Voltage
4.0 to 5.5
VIL
Low-Level Input Voltage
4.0 to 5.5
0.8
V
IIN
Input Leakage Current
0 ≤ VIN ≤ 5.5V
5.5
±1.0
µA
IOZ
Off-state Leakage
Current
0 ≤ A, B ≤ VCC
5.5
±1.0
µA
VIN = 0V, IIN = 64mA
4.5
4
7
VIN = 0V, IIN = 30mA
4.5
4
7
VIN = 2.4V, IIN = 15mA
4.5
8
15
11
20
RON
ICC
ΔICC
Switch On Resistance
(3)
2.0
V
FST3244 — 8-Bit Bus Switch
DC Electrical Characteristics
Ω
VIN = 2.4V, IIN = 15mA
4.0
Quiescent Supply Current
VIN = VCC or GND,
IOUT = 0
5.5
3
µA
Increase in ICC per Input
One Input at 3.4V, Other
Inputs at VCC or GND
5.5
2.5
mA
Note:
3. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On
resistance is determined by the lower of the voltages on the A or B pins.
AC Electrical Characteristics
TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω.
Symbol
Parameter
Conditions
VCC = 4.5 – 5.5V
Min.
tPHL, tPLH
Propagation Delay
(4)
Bus-to Bus
VIN = Open
tPZH ,tPZL
Output Enable Time
VIN = 7V for tPZL
VIN = Open for
tPZH
tPHZ, tPLZ
Output Disable Time
VIN = 7V for tPLZ
VIN = Open for
tPHZ
Max.
VCC = 4.0V
Min.
Units
Figure
Max.
0.25
0.25
ns
Figure 3
Figure 4
1.0
5.6
6.1
ns
Figure 3
Figure 4
1.0
6.2
5.6
ns
Figure 3
Figure 4
Note:
4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay
other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by
an ideal voltage source (zero output impedance).
Capacitance
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested.
Symbol
Parameter
Conditions
Typ.
Units
CIN
Control Pin Input Capacitance
VCC = 5.0V
3
pF
CI/O
Input/Output Capacitance
VCC, /OE = 5.0V
5
pF
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
4
FST3244 — 8-Bit Bus Switch
AC Loadings and Waveforms
Notes: Input driven by 50Ω source terminated in 50Ω.
CL includes load and stray capacitance.
Input PRR = 1.0MHz, tw = 500ns.
Figure 3. AC Test Circuit
Figure 4. AC Waveforms
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
5
13.00
12.60
A
11.43
20
11
B
9.50
FST3244 — 8-Bit Bus Switch
Physical Dimensions
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.51
0.35
1.27
1.27
0.25
M
0.65
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
X 45°
0.10 C
0.30
0.10
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
GAGE PLANE
(R0.10)
0.25
8°
0°
1.27
0.40
SEATING PLANE
(1.40)
DETAIL A
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 5. 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
6
FST3244 — 8-Bit Bus Switch
Physical Dimensions
LAND PATTERN
RECOMMENDATION
TOP VIEW
END VIEW
SIDE VIEW
DETAIL A
Figure 6. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150-inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
7
FST3244 — 8-Bit Bus Switch
Physical Dimensions
Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
8
FST3244 — 8-Bit Bus Switch
© 1997 Fairchild Semiconductor Corporation
FST3244 • Rev. 1.0.3
www.fairchildsemi.com
9
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