Revised October 1999 74ACT533 Octal Transparent Latch with 3-STATE Outputs General Description Features The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. ■ ICC and IOZ reduced by 50% ■ Eight latches in a single package ■ 3-STATE outputs drive bus lines or buffer memory address registers ■ Outputs source/sink 24 mA ■ Inverted version of the ACT373 ■ TTL-compatible inputs Ordering Code: Order Number 74ACT533SC 74ACT533MTC Package Number M20B MTC20 74ACT533PC N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS500311 www.fairchildsemi.com 74ACT533 Octal Transparent Latch with 3-STATE Outputs August 1999 74ACT533 Functional Description Truth Table The ACT533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE OE Dn X H X Z H L L H H L H L L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com On 2 Recommended Operating Conditions − 0.5V to + 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = − 0.5V − 20 mA VI = VCC + 0.5V + 20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t DC Output Diode Current (IOK) VO = − 0.5V − 20 mA VO = VCC + 0.5V + 20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V − 0.5V to VCC + 0.5V 125 mV/ns DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) − 65°C to + 150°C DC Latchup Source Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ± 300 mA or Sink Current Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current ICCT Maximum V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA ICC/Input Supply Current 5.5 0.6 5.5 4.0 VIN = V CC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT533 Absolute Maximum Ratings(Note 1) 74ACT533 AC Electrical Characteristics Symbol Parameter tPHL Propagation Delay tPLH Dn to On VCC TA = + 25°C (V) CL = 50 pF TA = − 40°C to + 85°C CL = 50 pF Units (Note 4) Min Typ Max Min Max 5.0 2.0 6.0 8.0 2.0 8.5 ns 5.0 2.5 7.0 9.0 2.5 9.5 ns tPHL Propagation Delay tPLH LE to On tPZL, tPZH Output Enable Time 5.0 2.0 7.0 9.0 2.0 9.5 ns tPHZ, tPLZ Output Disable Time 5.0 1.0 8.0 10.0 1.0 10.5 ns Note 4: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements Symbol Parameter Setup Time, HIGH or LOW tS Dn to LE tH Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH tW VCC TA = + 25°C (V) CL = 50 pF TA = − 40°C to + 85°C CL = 50 pF Typ Guaranteed Minimum 5.0 0 3.0 3.0 ns 5.0 0 1.5 1.5 ns 5.0 2.0 4.0 4.0 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 40 pF VCC = 5.0V www.fairchildsemi.com Units (Note 5) 4 Conditions 74ACT533 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body Package Number M20B 5 www.fairchildsemi.com 74ACT533 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 74ACT533 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com