GENESYS GL424-WOGXX Sd/mmc flash card controller Datasheet

Genesys Logic, Inc.
GL424
SD/MMC Flash Card Controller
Datasheet
Revision 1.00
Apr. 18, 2007
GL424 SD/MMC Flash Card Controller
Copyright:
Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC..
GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS,
OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT
OF INTELLECTUAL PROPERTY, INCLUDING, WITHOUT LIMITATION, THE X-D PICTURE CARDTM
LICENSE. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING,
WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS.
PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS.
GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED
THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
Is a registered trademark of Genesys Logic, Inc.
All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http ://www.genesyslogic.com
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 2
GL424 SD/MMC Flash Card Controller
Revision History
Revision
Date
Description
0.90
04/06/2006
First formal release
1.00
04/18/2007
Add Die Pad, 46 PIN LGA, 51PIN LGA
1. Pin Assignment, p.11
2. Package Dimension, p.30
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 3
GL424 SD/MMC Flash Card Controller
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION................................................... 7
1.1 CARD INTERFACE ..................................................................................... 8
1.2 FLASH ACCESS INTERFACE ....................................................................... 8
1.3 EMBEDDED CPU ........................................................................................ 8
CHAPTER 2 FEATURES .............................................................................. 9
2.1 SD HOST INTERFACE ................................................................................. 9
2.2 MMC HOST INTERFACE ............................................................................ 9
2.3 FLASH MEMORY INTERFACE ..................................................................... 9
2.4 MICRO CONTROLLER AND ANALOG SYSTEM ......................................... 10
2.5 8KV-ESD PROTECTION ........................................................................... 10
2.6 DUAL CHANNEL FLASH TO REACH TOP READ/WRITE SPEED .............. 10
2.7 DUAL VOLTAGE APPLICATION ................................................................. 10
2.8 PRODUCT PACKAGES ............................................................................... 10
2.9 TECHNOLOGY........................................................................................... 10
2.10 MANUFACTURE ...................................................................................... 10
CHAPTER 3 PIN ASSIGNMENT .............................................................. 11
3.1 PINOUT ..................................................................................................... 11
3.2 PIN DESCRIPTIONS ................................................................................... 16
3.2.1 Regulator Interface......................................................................... 16
3.2.2 Card Interface ................................................................................. 18
3.2.3 Flash Interface................................................................................. 21
3.2.4 System Interface.............................................................................. 24
3.2.5 Test Interface................................................................................... 27
CHAPTER 4 ELECTRICAL CHARACTERISTICS............................... 28
4.1 ABSOLUTE MAXIMUM RATINGS .............................................................. 28
4.2 BUS OPERATING CONDITIONS ................................................................. 28
4.3 D.C. CHARACTERISTICS .......................................................................... 28
CHAPTER 5 PACKAGE DIMENSION..................................................... 30
CHAPTER 6 ORDERING INFORMATION ............................................ 34
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 4
GL424 SD/MMC Flash Card Controller
LIST OF FIGURES
FIGURE 1. 1 - GL424 BLOCK DIAGRAM .............................................................................. 8
FIGURE 3.1 - 46 PIN LQFN PINOUT .................................................................................. 11
FIGURE 3.2 - 54 PIN VFBGA PINOUT ............................................................................... 12
FIGURE 3.3 – DIE PAD PINOUT .......................................................................................... 13
FIGURE 3.4 – 46 PIN LGA PINOUT .................................................................................... 14
FIGURE 3.5 – 51 PIN LGA PINOUT .................................................................................... 15
FIGURE 5.1- 46 PIN LQFN PACKAGE DIMENSION ........................................................... 30
FIGURE 5.2- 54 PIN VFBGA PACKAGE DIMENSION......................................................... 31
FIGURE 5.3- 46 PIN LGA PACKAGE DIMENSION ............................................................. 32
FIGURE 5.4- 51 PIN LGA PACKAGE DIMENSION ............................................................. 33
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 5
GL424 SD/MMC Flash Card Controller
LIST OF TABLES
TABLE 3.1 - 46 PIN LQFN REGULATOR INTERFACE ....................................................... 16
TABLE 3.2 - 54 PIN VFBGA REGULATOR INTERFACE .................................................... 16
TABLE 3.3 – DIE PAD REGULATOR INTERFACE ................................................................ 16
TABLE 3.4 – 46 PIN LGA REGULATOR INTERFACE ......................................................... 17
TABLE 3.5 – 51 PIN LGA REGULATOR INTERFACE ......................................................... 17
TABLE 3.3 - 46 PIN LQFN CARD INTERFACE .................................................................. 18
TABLE 3.4 - 54 PIN VFBGA CARD INTERFACE ............................................................... 18
TABLE 3.5 – DIE PAD CARD INTERFACE ........................................................................... 19
TABLE 3.6 - 46 PIN LGA CARD INTERFACE ..................................................................... 20
TABLE 3.7 - 51 PIN LGA CARD INTERFACE ..................................................................... 20
TABLE 3.8 - 46 PIN LQFN FLASH INTERFACE ................................................................. 21
TABLE 3.9 - 54 PIN VFBGA FLASH INTERFACE .............................................................. 21
TABLE 3.10 – DIE PAD FLASH INTERFACE ........................................................................ 22
TABLE 3.11 – 46 PIN LGA FLASH INTERFACE ................................................................. 23
TABLE 3.12 – 51 PIN LGA FLASH INTERFACE ................................................................. 23
TABLE 3.13 - 46 PIN LQFN SYSTEM INTERFACE ............................................................ 24
TABLE 3.14 - 54 PIN VFBGA SYSTEM INTERFACE.......................................................... 24
TABLE 3.15 - DIE PAD SYSTEM INTERFACE ...................................................................... 25
TABLE 3.16 - 46 PIN LGA SYSTEM INTERFACE ............................................................... 26
TABLE 3.17 - 51 PIN LGA SYSTEM INTERFACE ............................................................... 26
TABLE 3.18 - 54 PIN VFBGA TEST INTERFACE .............................................................. 27
TABLE 3.19 - DIE PAD TEST INTERFACE ........................................................................... 27
TABLE 4.1 - ABSOLUTE MAXIMUM RATINGS .................................................................... 28
TABLE 4.2 - BUS OPERATING CONDITIONS ....................................................................... 28
TABLE 4.3 - D.C. CHARACTERISTICS ................................................................................ 28
TABLE 6.1- ORDERING INFORMATION .............................................................................. 34
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 6
GL424 SD/MMC Flash Card Controller
CHAPTER 1 GENERAL DESCRIPTION
GL424 is a single-chip controller for SD and MMC memory cards. It is designed based on SD1.0/SD1.1/SD2.0
and MMC3.3/MMC4.0 specification. Its unique RAM based firmware strategy provides flexibility for fast
compatibility and performance improvement, therefore, give customers strong support to win in today’s
fast-changing market. With its simple interface, customers can easily apply it to SD and MMC memory cards
manufacturing at the same time.
GL424 manages interface protocol, data storage and retrieval, error detection and correction, defect handling and
diagnostic, as well as power management. With a built-in flash management algorithm, GL424 is applicable for
most types of flash in the market: SAMSUNG, MICRON, ST, TOSHIBA, HYNIX and RENESAS.
GL424 is packaged LQFN-46 and VFBGA-54. Both die and LQFN/VFBGA package are available and
completely meet SD and MMC memory card mechanical thickness requirement.
The pin assignment that fits to
card sockets provides easy PCB layout.
GL424 is unique in its three advanced features:
(1) Dual-channel solution as well as normal single channel solution with top access speed;
(2) Dual voltage for both 1.8V and 3.3V interface;
(3) 8KV-ESD protecting the whole card.
VFBGA54 packaged GL424 has a dual channel flash access interface, which remarkably speed up read/write
performance. It supports 16-bit flash also.
GL424 provides 8KV ESD (human body mode) and 15KV ESD (mechanical mode) protection. Especially,
GL424 can also provide such high voltage ESD protection to FLASH on the whole SD/MMC card. Therefore,
greatly improved SD/MMC card’s reliability and high quality in unpredictable application environment.
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 7
GL424 SD/MMC Flash Card Controller
Flash1
Interface
HOST
Interface
Host Interface
CARD
Controller
Flash Access
IF
Flash2
Interface
GL424
Figure 1. 1 - GL424 Block Diagram
1.1 CARD Interface
The card controller, complied with SD/MMC specification, explains commands from SD/MMC host and
transfers data between SD/MMC host and flash.
1.2 Flash Access Interface
The flash access interface communicates with CPU. It also manages two channels of flash, based on flash
commands. Moreover, it implements defect processing, ECC, and address mapping, etc.
1.3 Embedded CPU
Embedded CPU performs arithmetic and logical operations. In addition, it extracts instruction from ROM and
SRAM, decodes and executes them. It also manages control and status signals between flash access interface and
itself.
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 8
GL424 SD/MMC Flash Card Controller
CHAPTER 2 FEATURES
2.1 SD Host Interface
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
Complies with SD Specification, Version 2.0
Complies with SD Specification, Version 1.1
Complies with SD Specification, Version 1.0
Supports SPI mode and CPRM functions
Supports clock rate up to 25 MHz for SD1.0
Supports clock rate up to 52 MHz for SD1.1 and SD2.0
Buffers for multi-block flash memory programming
DMA operation between buffers and flash memory
Supports automatic CRC16 generation and verification on DATA3-0
Supports SD card exceed 4Gbytes capacity
2.2 MMC Host Interface
‧
‧
‧
‧
‧
‧
‧
‧
Complies with MultiMediaCard System Specification, Version 4.0
Complies with MultiMediaCard System Specification, Version 3.3
Supports SPI mode and CPRM functions
Supports clock rate up to 20 MHz for MMC3.3
Supports clock rate up to 52 MHz for MMC4.0
Buffers for multi-block flash memory programming
DMA operation between buffers and flash memory
Supports automatic CRC16 generation and verification on DATA7-0
2.3 Flash Memory Interface
‧
‧
‧
‧
‧
‧
‧
Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS /
MICRON / ST / HYNIX)
Supports dual-channel, 16 bits flash (VFBGA54 package and die)
Drives up to 4 flash memory chips, respectively (VFBGA54 package and die)
Supports 64M / 128M / 256M / 512M / 1G / 2G / 4G / 8G bits flash chips
Embedded firmware support for flash file system (FTL)
Built-in flash management algorithm
Powerful ECC for error detection and correction up to 6 bytes per 512bytes
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 9
GL424 SD/MMC Flash Card Controller
2.4 Micro Controller and Analog System
‧
‧
‧
RISC core with fast speed and less code size
Flexibility to update system code
Ability to add customers’ own feature
2.5 8KV-ESD protection
‧ 8KV human body ESD protection (contact discharge mode) for the whole card (not only controller
chip itself)
‧ 15KV mechanical mode ESD protection (air discharge mode) for the whole card (not only
controller chip itself)
2.6 Dual Channel FLASH to reach top Read/Write Speed
‧
GL424 provides dual channel flash access solution. This can reach the read/write speed almost
doubled compared with single channel solution.
2.7 Dual voltage application
‧
GL424 provides the solution for dual voltage application. This means MMC4.0 card with GL424
can work with either 1.8V or 3.3V host interface.
2.8 Product Packages
‧
‧
‧
‧
46-pin LQFN package
54-pin VFBGA package
46-pin LGA package
51-pin LGA package
2.9 Technology
‧
0.18um process
2.10 Manufacture
‧
‧
Easy firmware development environment
Supports firmware upgrade tool via PC
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 10
GL424 SD/MMC Flash Card Controller
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinout
Figure 3.1 - 46 Pin LQFN Pinout
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 11
GL424 SD/MMC Flash Card Controller
Figure 3.2 - 54 Pin VFBGA Pinout
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 12
©2000-2007 Genesys Logic Inc. - All rights reserved.
PAD4
PAD4
5
PAD4
6
PAD4
7
PAD4
8
PAD5
9
PAD5
0
PAD5
1
PAD5
2
PAD5
3
PAD5
4
PAD5
5
PAD5
6
PAD5
7
PAD5
8
PAD6
9
PAD6
0
1
PAD1
PAD1
5
PAD1
6
PAD1
7
PAD1
8
PAD2
9
PAD2
0
PAD2
1
PAD2
2
PAD2
3
PAD2
4
PAD2
5
PAD2
6
PAD2
7
PAD2
8
PAD3
9
PAD3
0
PAD3
1
PAD3
2
PAD3
3
PAD3
4
PAD3
5
PAD3
6
PAD3
7
PAD3
8
PAD4
9
PAD4
0
PAD4
1
PAD4
2
PAD4
3
4
PAD_DETECT
PAD_DETECT
PAD_HDATA2
PAD_HDATA2
PAD_HDATA3
PAD_HDATA3
PAD_HCMD
PAD_HCMD
VCC
PAD_HCLK
PAD_HCLK
GND
GND
PAD_HDATA0
PAD_HDATA0
PAD_HDATA1
PAD_HDATA1
PAD_OSCO
PAD_T0
PAD_T1
PAD_T2
PAD_T3
PAD_T4
PAD_T5
PAD_T6
VDDIN
PAD_T7
PAD_CE0_B
PAD_CE1_B
PAD_ALE
PAD_CLE
PAD_WP_B
PAD_RE_B
PAD_WE_B
PAD_BUSY_B
PAD_DA7
PAD_DA6
PAD_DA5
V18IN
VDDIN
PAD_DA4
GNDIN
PAD_DA3
PAD_DA2
PAD_DA1
PAD_DA0
PAD_Prt_B
GL424 SD/MMC Flash Card Controller
Figure 3.3 – Die Pad Pinout
Page 13
GL424 SD/MMC Flash Card Controller
GL424
46
PIN LGA
Figure 3.4 – 46 Pin LGA Pinout
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 14
GL424 SD/MMC Flash Card Controller
GL424
51 PIN LGA
Figure 3.5 – 51 Pin LGA Pinout
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 15
GL424 SD/MMC Flash Card Controller
3.2 Pin Descriptions
3.2.1 Regulator Interface
Table 3.1 - 46 PIN LQFN Regulator Interface
Pin No.
Pin Name
Type
Description
1
R1
A
External Resistor pad
2
R2
A
External Resistor pad
3
V18OUT
O
1.8V output (Max.100mA)
4
VIN
P
3.3V power
5
GND
P
Ground
6
GNDOUT
P
Ground output
Table 3.2 - 54 PIN VFBGA Regulator Interface
Pin No.
Pin Name
Type
Description
A6
R1
A
External Resistor pad
A5
R2
A
External Resistor pad
B5
V18OUT
O
1.8V output (Max.100mA)
C4
V18Fsh
O
1.8V output (Max.30mA)
A4
VIN
P
3.3V power
B4
GND
P
Ground
G5
GNDX
P
Ground
Table 3.3 – Die Pad Regulator Interface
Pad No.
Pad Name
Type
PAD1
R1
A
External Resistor pad
PAD2
R2
A
External Resistor pad
PAD3
V18-out2
O
PAD4
V18-out2
O
PAD5
V18-out1
O
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
1.8V output (Max.100mA)
(Double Bonding)
Regulator 1.8V output
(Double Bonding)
1.8V output (Max.40mA)
Page 16
GL424 SD/MMC Flash Card Controller
PAD6
VIN
P
PAD7
VIN
P
PAD8
VIN
P
PAD9
GND
P
PAD10
GND
P
PAD11
GNDOUT
P
3.3V power
(Tri-bonding )
3.3V power
(Tri-bonding )
3.3V power
(Tri-bonding )
Ground
(Double Bonding)
Ground
(Double Bonding)
Ground output when enhanced 8KV-ESD protected
Table 3.4 – 46 PIN LGA Regulator Interface
Pin No.
Pin Name
Type
Description
16
R1
A
External Resistor pad
17
R2
A
External Resistor pad
18
V18OUT
O
1.8V output (Max.100mA)
19
VIN
P
3.3V power
20
GND
P
Ground
21
GNDOUT
P
Ground
Table 3.5 – 51 PIN LGA Regulator Interface
Pin No.
Pin Name
Type
17
R1
A
External Resistor pad
18
R2
A
External Resistor pad
19
V18
O
1.8V output (Max.100mA)
48
V18Fsh
O
1.8V output (Max.30mA)
20
VIN
P
3.3V power
21
GND
P
Ground
22
GNDX
P
Ground
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Page 17
GL424 SD/MMC Flash Card Controller
Note :
A: Analog
I: Input
O: Output
P: Power supply
B: Bi-direction
3.2.2 Card Interface
Table 3.3 - 46 PIN LQFN Card Interface
Pin No.
Pin Name
Type
Description
20
HCLK
I
18
HCMD
B
22
HDATA0
B
23
HDATA1
B
16
HDATA2
B
17
HDATA3
B
25
HDATA4
B
MMC mode: HDATA4 from/to HOST.
26
HDATA5
B
MMC mode: HDATA5 from/to HOST.
27
HDATA6
B
MMC mode: HDATA6 from/to HOST.
28
HDATA7
B
MMC mode: HDATA7 from/to HOST.
HCLK from HOST
SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
Table 3.4 - 54 PIN VFBGA Card Interface
Pin No.
Pin Name
Type
H1
HCLK
I
F2
HCMD
B
J2
HDATA0
B
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
HCLK from HOST
SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
Page 18
GL424 SD/MMC Flash Card Controller
SD/MMC mode: HDATA1 from/to HOST.
J1
HDATA1
B
E1
HDATA2
B
F1
HDATA3
B
J3
HDATA4
B
MMC mode: HDATA4 from/to HOST.
H2
HDATA5
B
MMC mode: HDATA5 from/to HOST.
H4
HDATA6
B
MMC mode: HDATA6 from/to HOST.
H3
HDATA7
B
MMC mode: HDATA7 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
Table 3.5 – Die Pad Card Interface
Pad No.
Pad Name
Type
PAD54
PAD_HCLK
B
PAD55
PAD_HCLK
B
PAD51
PAD_HCMD
B
PAD52
PAD_HCMD
B
PAD59
PAD_HDATA0
B
PAD58
PAD_HDATA0
B
PAD61
PAD_HDATA1
B
PAD60
PAD_HDATA1
B
PAD47
PAD_HDATA2
B
PAD48
PAD_HDATA2
B
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
HCLK from HOST
Backup PAD
(No Bonding)
SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
Backup PAD
(No Bonding)
SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
Backup PAD
(No Bonding)
SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
Backup PAD
(No Bonding)
SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
Backup PAD
(No Bonding)
Page 19
GL424 SD/MMC Flash Card Controller
Table 3.6 - 46 PIN LGA Card Interface
Pin No.
Pin Name
Type
Description
37
HCLK
I
35
HCMD
B
39
HDATA0
B
40
HDATA1
B
33
HDATA2
B
34
HDATA3
B
42
HDATA4
B
MMC mode: HDATA4 from/to HOST.
43
HDATA5
B
MMC mode: HDATA5 from/to HOST.
44
HDATA6
B
MMC mode: HDATA6 from/to HOST.
45
HDATA7
B
MMC mode: HDATA7 from/to HOST.
HCLK from HOST
SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
Table 3.7 - 51 PIN LGA Card Interface
Pin No.
Pin Name
Type
38
HCLK
I
36
HCMD
B
40
HDATA0
B
41
HDATA1
B
34
HDATA2
B
35
HDATA3
B
42
HDATA4
B
MMC mode: HDATA4 from/to HOST.
43
HDATA5
B
MMC mode: HDATA5 from/to HOST.
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
HCLK from HOST
SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
Page 20
GL424 SD/MMC Flash Card Controller
44
HDATA6
B
MMC mode: HDATA6 from/to HOST.
45
HDATA7
B
MMC mode: HDATA7 from/to HOST.
3.2.3 Flash Interface
Table 3.8 - 46 PIN LQFN Flash Interface
Pin No.
Pin Name
Type
Description
11
CE0_
B
‘0’ for FLASH chip 0 to select active (low-active).
12
CE1_
B
‘0’ for FLASH chip 1 to select active (low-active).
14
CLE
B
FLASH command latch enable
13
ALE
B
FLASH address latch enable
46
RE_
B
FLASH read enable (low active)
45
WE_
B
FLASH write enable (low active)
44
BUSY_
B
FLASH ready when high, busy when low.
15
WP_
B
FLASH write protect (low active)
33
DA0
B
FLASH bus bit0
34
DA1
B
FLASH bus bit1
35
DA2
B
FLASH bus bit2
36
DA3
B
FLASH bus bit3
38
DA4
B
FLASH bus bit4
41
DA5
B
FLASH bus bit5
42
DA6
B
FLASH bus bit6
43
DA7
B
FLASH bus bit7
Table 3.9 - 54 PIN VFBGA Flash Interface
Pin No.
Pin Name
Type
B6
CE0_
B
‘0’ for FLASH chip 0 to select active (low-active).
C5
CE1_
B
‘0’ for FLASH chip 1 to select active (low-active).
C6
ALE
B
FLASH address latch enable
D5
CLE
B
FLASH command latch enable
D6
RE_
B
FLASH read enable (low active)
E6
WE_
B
FLASH write enable (low active)
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Page 21
GL424 SD/MMC Flash Card Controller
E5
BUSY_
B
FLASH ready when high, busy when low.
D4
WP_
B
FLASH write protect (low active)
J5
DA0
B
FLASH bus bit0
J6
DA1
B
FLASH bus bit1
H5
DA2
B
FLASH bus bit2
H6
DA3
B
FLASH bus bit3
G6
DA4
B
FLASH bus bit4
F5
DA5
B
FLASH bus bit5
F6
DA6
B
FLASH bus bit6
E4
DA7
B
FLASH bus bit7
Table 3.10 – Die Pad Flash Interface
Pad No.
Pad Name
Type
PAD25
PAD_CE0_B
B
‘0’ for FLASH chip 0 to select active (low-active).
PAD26
PAD_CE1_B
B
‘0’ for FLASH chip 1 to select active (low-active).
PAD28
PAD_CLE
B
FLASH command latch enable
PAD27
PAD_ALE
B
FLASH address latch enable
PAD30
PAD_RE_B
B
FLASH read enable (low active)
PAD31
PAD_WE_B
B
FLASH write enable (low active)
PAD32
PAD_BUSY_B
B
FLASH ready when high, busy when low.
PAD29
PAD_WP_B
B
FLASH write protect (low active)
PAD43
PAD_DA0
B
FLASH bus bit0
PAD42
PAD_DA1
B
FLASH bus bit1
PAD41
PAD_DA2
B
FLASH bus bit2
PAD40
PAD_DA3
B
FLASH bus bit3
PAD38
PAD_DA4
B
FLASH bus bit4
PAD35
PAD_DA5
B
FLASH bus bit5
PAD34
PAD_DA6
B
FLASH bus bit6
PAD33
PAD_DA7
B
FLASH bus bit7
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Page 22
GL424 SD/MMC Flash Card Controller
Table 3.11 – 46 PIN LGA Flash Interface
Pin No.
Pin Name
Type
Description
26
CE0_
B
‘0’ for FLASH chip 0 to select active (low-active).
27
CE1_
B
‘0’ for FLASH chip 1 to select active (low-active).
28
ALE
B
FLASH address latch enable
29
CLE
B
FLASH command latch enable
31
RE_
B
FLASH read enable (low active)
32
WE_
B
FLASH write enable (low active)
15
BUSY_
B
FLASH ready when high, busy when low.
30
WP_
B
FLASH write protect (low active)
4
DA0
B
FLASH bus bit0
5
DA1
B
FLASH bus bit1
6
DA2
B
FLASH bus bit2
7
DA3
B
FLASH bus bit3
9
DA4
B
FLASH bus bit4
12
DA5
B
FLASH bus bit5
13
DA6
B
FLASH bus bit6
14
DA7
B
FLASH bus bit7
Table 3.12 – 51 PIN LGA Flash Interface
Pin No.
Pin Name
Type
11
CE0_
B
‘0’ for FLASH chip 0 to select active (low-active).
12
CE1_
B
‘0’ for FLASH chip 1 to select active (low-active).
14
ALE
B
FLASH address latch enable
13
CLE
B
FLASH command latch enable
10
RE_
B
FLASH read enable (low active)
15
WE_
B
FLASH write enable (low active)
9
BUSY_
B
FLASH ready when high, busy when low.
16
WP_
B
FLASH write protect (low active)
1
DA0
B
FLASH bus bit0
2
DA1
B
FLASH bus bit1
3
DA2
B
FLASH bus bit2
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Page 23
GL424 SD/MMC Flash Card Controller
4
DA3
B
FLASH bus bit3
5
DA4
B
FLASH bus bit4
6
DA5
B
FLASH bus bit5
7
DA6
B
FLASH bus bit6
8
DA7
B
FLASH bus bit7
3.2.4 System Interface
Table 3.13 - 46 PIN LQFN System Interface
Pin No.
Pin Name
Type
Description
7
MCLK
I
Main clock input.
8
Rst_
I
Power-on reset, low active
9
OSCO
O
Main clock output
31
OSC_E
I
Oscillator enable
10
VDDIN
P
Power supply for IO
39
VDDIN
P
Power supply for IO
40
V18IN
P
Digital 1.8V power supply
37
GNDIN
P
Digital GND
19
VCC
P
3.3V power supply
29
VCC
P
3.3V power supply
21
GND
P
Ground
32
GND
P
Ground
24
CVDD18
P
1.8V power supply
30
VDDOUT
P
3.3V power output
Table 3.14 - 54 PIN VFBGA System Interface
Pin No.
Pin Name
Type
B3
MCLK
I
Main clock input.
A3
Rst_
I
Power-on reset, low active
C3
OSCO
O
Main clock output
E2
OSC_E
I
Oscillator enable
D2
VDDIN
P
Power supply for flash interface IO
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Page 24
GL424 SD/MMC Flash Card Controller
F4
V18IN
P
Digital 1.8V power supply
F3
VCC
P
3.3V power supply
G3
VCC
P
3.3V power supply
G4
GND
P
Ground
G2
CVDD18
P
1.8V power supply
J4
VDDOUT
P
3.3V power output
E3
Prt_
B
Protect
G1
DETECT
O
Power detect
Table 3.15 - Die Pad System Interface
Pad No.
Pad Name
Type
PAD13
PAD_rst_B
I
Power-on reset input, low active
PAD14
PAD_rst_o
O
Power-on reset output
PAD44
PAD_Prt_B
B
Protect
PAD15
PAD_OSCO
O
Clock output for test
PAD12
PAD_MCLK
I
Main clock input.
PAD45
PAD_DETECT
B
Card detect
PAD46
PAD_DETECT
B
PAD74
PAD_OSC_E
I
PAD73
PAD_OSC_E
I
PAD23
VDDIN
P
Power supply for flash interface IO
PAD37
VDDIN
P
Power supply for flash interface IO
PAD36
V18IN
P
Digital 1.8V power supply
PAD39
GNDIN
P
Ground input
PAD53
VCC
P
3.3V power supply
PAD56
GND
P
Ground
PAD57
GND
P
Ground
PAD62
CVDD18
P
1.8V power supply
PAD71
VCC
P
3.3V power supply
PAD72
V33OUT
P
3.3V power output when enhanced 8KV-ESD protected
PAD75
GND
P
Ground
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Backup PAD
(No Bonding)
Oscillator enable
Backup PAD
(No Bonding)
Page 25
GL424 SD/MMC Flash Card Controller
Table 3.16 - 46 PIN LGA System Interface
Pin No.
Pin Name
Type
Description
22
MCLK
I
Main clock input.
23
Rst_
I
Power-on reset, low active
24
OSCO
O
Main clock output
2
OSC_E
I
Oscillator enable
10
VDDIN
P
Power supply for flash interface IO
25
VDDIN
P
Power supply for flash interface IO
1
VDDOUT
P
3.3V power output
36
VCC
P
3.3V power supply
46
VCC
P
3.3V power supply
3
GND
P
Ground
38
GND
P
Ground
8
GNDIN
P
Ground
11
V18IN
P
1.8V power supply
41
CVDD18
P
1.8V power supply
Table 3.17 - 51 PIN LGA System Interface
Pin No.
Pin Name
Type
51
MCLK
I
Main clock input.
23
Rst_
I
Power-on reset, low active
49
OSCO
O
Main clock output
47
OSC_E
I
Oscillator enable
32
VDDIN
P
Power supply for flash interface IO
37
VCC
P
3.3V power supply
39
GND
P
Ground
46
VDDOUT
P
3.3V power output
33
Prt_
B
Protect
50
DETECT
O
Power detect
©2000-2007 Genesys Logic Inc. - All rights reserved.
Description
Page 26
GL424 SD/MMC Flash Card Controller
3.2.5 Test Interface
Table 3.18 - 54 PIN VFBGA Test Interface
Pin No.
Pin Name
Type
Description
A1
T0
B
Flash2 bus bit0 to bit7 when dual channel mode;
A2
T1
B
Flash bus bit8 to bit15 when 16-bit flash mode;
B2
T2
B
Test mode input when testing mode.
B1
T3
B
(On-chip pulled-up).
C2
T4
B
C1
T5
B
D3
T6
B
D1
T7
B
Table 3.19 - Die Pad Test Interface
Pad No.
Pad Name
Type
PAD16
PAD_T0
B
PAD17
PAD_T1
B
PAD18
PAD_T2
B
PAD19
PAD_T3
B
PAD20
PAD_T4
B
PAD21
PAD_T5
B
PAD22
PAD_T6
B
PAD24
PAD_T7
B
Description
Flash2 bus bit0 to bit7 when dual channel mode;
Flash bus bit8 to bit15 when 16-bit flash mode;
©2000-2007 Genesys Logic Inc. - All rights reserved.
Test mode input when testing mode.
(On-chip pulled-up).
Page 27
GL424 SD/MMC Flash Card Controller
CHAPTER 4 ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings
Table 4.1 - Absolute Maximum Ratings
Parameter
Symbol
Min
Max.
Unit
VDD
2.0
3.6
V
Supply Voltage Differentials (Vss1, Vss2)
-0.3
0.3
V
Storage Temperature
-40
85
o
C
95
o
C
Supply Voltage
Junction Temperature
Remark
CMD0, 15,55, ACMD41
4.2 Bus Operating Conditions
Table 4.2 - Bus Operating Conditions
Parameter
Symbol
Min
Max.
Unit
VDD
2.6
3.6
V
85
o
Peak Voltage on all Lines
Ground Voltage
0
Operation Temperature
-25
Operation Moisture and Corrosion
Remark
V
C
95%
Rel. humidity
4.3 D.C. Characteristics
Table 4.3 - D.C. Characteristics
Parameter
Supply voltage
Symbol
Condition
VCC
Min
Typ.
Max
Unit
2.0
3.3
3.6
V
Input Leakage Current
(HCLK, HCMD and HDATA2-0 to
II
0< VIN < VCC
0.2
-
0.3
µA
II
0< VIN < VCC
0.2
-
0.3
µA
II
0< VIN < VCC
-
-
0.43
µA
Ground)
Input Leakage Current
(HCLK, HCMD and HDATA2-0 to VDD)
Input Leakage Current at HDATA3 to
Ground
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 28
GL424 SD/MMC Flash Card Controller
Output High Voltage at HCMD
VOH
Clock = 20MHz
-
-
3588
mV
Output High Voltage at HDATA
VOH
Clock = 20MHz
-
-
3586
mV
Output Low Voltage at HCMD
VOL
Clock = 20MHz
39
-
-
mV
Output Low Voltage at HDATA
VOL
Clock = 20MHz
39
-
-
mV
Read/Write Current
ICC
-
-
©2000-2007 Genesys Logic Inc. - All rights reserved.
mA
Page 29
GL424 SD/MMC Flash Card Controller
CHAPTER 5 PACKAGE DIMENSION
Figure 5.1- 46 Pin LQFN Package Dimension
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 30
GL424 SD/MMC Flash Card Controller
Figure 5.2- 54 Pin VFBGA Package Dimension
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 31
GL424 SD/MMC Flash Card Controller
Figure 5.3- 46 PIN LGA Package Dimension
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 32
GL424 SD/MMC Flash Card Controller
Figure 5.4- 51 PIN LGA Package Dimension
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 33
GL424 SD/MMC Flash Card Controller
CHAPTER 6 ORDERING INFORMATION
Table 6.1- Ordering Information
Part Number
Package
Normal/Green
Version
Status
GL424-PMGXX
46-Pin LQFN
Green Package
XX
Available
GL424-PMGXX
54-Pin VFBGA
Green Package
XX
Available
GL424-WMGXX
46-Pin LGA
Green Package
XX
Available
GL424-WOGXX
51-Pin LGA
Green Package
XX
Available
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 34
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