NXP CBT16212DL 24-bit bus exchange switch with 12-bit output enable Datasheet

CBT16212
24-bit bus exchange switch with 12-bit output enables
Rev. 02 — 3 November 2008
Product data sheet
1. General description
The CBT16212 provides 24 bits of high-speed TTL-compatible bus switching or
exchanging. The low ON resistance of the switch allows connections to be made with
minimal propagation delay.
The CBT16212 operates either as a 24-bit bus switch or as a 12-bit bus exchanger,
providing data exchange between four signal ports using the port select inputs (S0, S1
and S2).
The CBT16212 is characterized for operation from –40 °C to +85 °C.
2. Features
n 5 Ω switch connection between two ports
n TTL compatible input levels
n ESD protection:
u HBM JESD22-A114E Class 1C exceeds 1500 V
u CDM JESD22-C101C exceeds 1000 V
n Latch-up performance:
u JESD78 exceeds 100 mA
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
CBT16212DGG
−40 °C to 85 °C
TSSOP56
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
CBT16212DL
−40 °C to 85 °C
SSOP56
plastic shrink small outline package; 56 leads; body
width 7.5 mm
SOT371-1
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
4. Functional diagram
1B1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
18
20
21
22
23
24
25
26
27
28
1
56
55
1A1
54
1A2
1B2
2B1
2A1
53
52
2A2
2B2
3B1
3A1
51
50
3A2
3B2
4B1
4A1
48
47
4A2
4B2
5B1
5A1
46
45
5A2
5B2
6B1
6A1
44
43
6A2
6B2
7B1
7A1
42
41
7A2
7B2
8B1
8A1
40
39
8A2
8B2
9B1
9A1
37
36
9A2
9B2
10B1
10A1
1A1
2
1 of 12 channels
10B2
11B1
11A1
33
32
11A2
11B2
12B1
12A1
1A2
31
30
3
53
1B2
FLOW CONTROL
12A2
12B2
S0
29
S0
S1
S1
S2
S2
Functional diagram
1
56
55
001aai357
Fig 2.
Logic diagram
CBT16212_2
Product data sheet
1B1
10A2
001aai356
Fig 1.
54
35
34
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
2 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
5. Pinning information
5.1 Pinning
S0
1
56 S1
1A1
2
55 S2
1A2
3
54 1B1
2A1
4
53 1B2
2A2
5
52 2B1
3A1
6
51 2B2
3A2
7
50 3B1
GND
8
49 GND
4A1
9
48 3B2
4A2 10
47 4B1
5A1 11
46 4B2
5A2 12
45 5B1
6A1 13
44 5B2
6A2 14
7A1 15
43 6B1
CBT16212
42 6B2
7A2 16
41 7B1
VCC 17
40 7B2
8A1 18
39 8B1
GND 19
38 GND
8A2 20
37 8B2
9A1 21
36 9B1
9A2 22
35 9B2
10A1 23
34 10B1
10A2 24
33 10B2
11A1 25
32 11B1
11A2 26
31 11B2
12A1 27
30 12B1
12A2 28
29 12B2
001aai358
Fig 3.
Pin configuration SOT364-1 (TSSOP56) and SOT371-1 (SSOP56)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
S0, S1, S2
1, 56, 55
port select input
1A1 to 12A1
2, 4, 6, 9, 11, 13, 15, 18, 21, 23, 25, 27
A1 port
1A2 to 12A2
3, 5, 7, 10, 12, 14, 16, 20, 22, 24, 26, 28
A2 port
GND
8, 19, 38, 49
ground (0 V)
VCC
17
supply voltage
1B1 to 12B1
54, 52, 50, 47, 45, 43, 41, 39, 36, 34, 32, 30
B1 port
1B2 to 12B2
53, 51, 48, 46, 44, 42, 40, 37, 35, 33, 31, 29
B2 port
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
3 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
6. Functional description
Table 3.
Function selection[1]
Port select input
Input/output
Function
S2
S1
S0
nA1
nA2
L
L
L
Z
Z
disconnect
L
L
H
nB1
Z
nA1 = nB1
L
H
L
nB2
Z
nA1 = nB2
L
H
H
Z
nB1
nA2 = nB1
H
L
L
Z
nB2
nA2 = nB2
H
L
H
Z
Z
disconnect
H
H
L
nB1
nB2
nA1 = nB1 and nA2 = nB2
H
H
H
nB2
nB1
nA1 = nB2 and nA2 = nB1
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
−0.5
+7.0
V
−0.5
+7.0
V
VCC
supply voltage
VI
input voltage
IIK
input clamping current
VI < 0 V
−50
-
mA
VO
output voltage
output at HIGH level or OFF-state
−0.5
+5.5
V
output at LOW level
IO
output current
Tstg
storage temperature
Ptot
total power dissipation
[1]
-
128
mA
−65
+150
°C
Tamb = −40 °C to +125 °C
SSOP56 package
[3]
-
850
mW
TSSOP56 package
[4]
-
600
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
[3]
Above 55 °C the value of Ptot derates linearly with 11.3 mW/K.
[4]
Above 55 °C the value of Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
4.0
5.5
V
VIH
HIGH-level input voltage
2.0
-
V
VIL
LOW-level input voltage
-
0.8
V
Tamb
ambient temperature
−40
+85
°C
operating in free-air
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
4 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
9. Static characteristics
Table 6.
Static characteristics
Tamb = −40 °C to +85 °C.
Min
Typ[1]
Max
Unit
VCC = 4.5 V; II = −18 mA
-
-
−1.2
V
Symbol
Parameter
Conditions
VIK
input clamping voltage
II
input leakage current
VCC = 0 V; VI = 5.5 V
-
-
10
µA
VCC = 5.5 V; VI = VCC or GND
-
-
±1
µA
-
-
3
µA
-
-
2.5
mA
-
4.7
-
pF
-
11.5
-
pF
-
-
21
Ω
VI = 0 V; II = 64 mA
-
4
7
Ω
VI = 0 V; II = 30 mA
-
4
7
Ω
VI = 2.4 V; II = 15 mA
-
6
12
Ω
ICC
supply current
VCC = 5.5 V; IO = 0 A;
VI = VCC or GND
∆ICC
additional supply current
per port select input pin; VCC = 5.5 V;
one input at 3.4 V, other inputs at VCC
or GND
CI
input capacitance
port select input pins; VI = 3 V or 0 V;
VCC = 5.0 V;
Cio(off)
off-state input/output capacitance VO = 3 V or 0 V; VCC = 0 V
RON
ON resistance
VCC = 4.0 V
[2]
[3]
VI = 2.4 V; II = 15 mA
VCC = 4.5 V
[3]
[1]
All typical values are measured at Tamb = 25 °C.
[2]
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3]
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (A or B) terminals.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = −40 °C to +85 °C; VCC = 4.5 V to 5.5 V; for test circuit see Figure 6.
Symbol
Parameter
propagation delay
tpd
Conditions
Min
Max
Unit
input A or B to output B or A; see Figure 4
[1][2]
-
0.25
ns
2.4
8.0
ns
2.4
8.0
ns
ten
enable time
port select input to output A or B; Figure 5
[3]
tdis
disable time
port select input to output A or B; Figure 5
[4]
[1]
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical
ON resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
[2]
tpd is the same as tPLH and tPHL.
[3]
ten is the same as tPZL and tPZH.
[4]
tdis is the same as tPLZ and tPHZ.
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
5 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
11. Waveforms
VI
input
GND
VM
VM
tPLH
tPHL
VOH
output
VM
VOL
VM
001aah986
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
Input to output propagation delays
VI
Sn input
GND
3.5 V
output
OFF to LOW
LOW to OFF V
OL
output
OFF to HIGH
HIGH to OFF
VM
VM
tPZL
tPLZ
VM
VOL + 0.3 V
tPZH
tPHZ
VOH
VOH − 0.3 V
VM
GND
001aaj055
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Table 8.
Enable and disable times
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
4.5 V to 5.5 V
1.5 V
1.5 V
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
6 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6.
Test circuit
Table 9.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr = tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
4.5 V to 5.5 V
GND to 3.0 V
≤ 2.5 ns
50 pF
500 Ω
open
open
7.0 V
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
7 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
12. Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
28
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
Fig 7.
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT364-1 (TSSOP56)
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
8 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
D
E
A
X
c
y
HE
v M A
Z
29
56
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
28
1
bp
e
0
detail X
w M
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
18.55
18.30
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT371-1
Fig 8.
REFERENCES
IEC
JEDEC
JEITA
MO-118
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Package outline SOT371-1 (SSOP56)
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
9 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBT16212_2
03112008
Product data sheet
-
CBT16212_1
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 7 “Dynamic characteristics”:
– Enable time: min value changed from 3.6 into 2.4.
– Disable time: min value changed from 4.5 into 2.4.
CBT16212_1
20010928
Product data
CBT16212_2
Product data sheet
-
-
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
10 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
CBT16212_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 3 November 2008
11 of 12
CBT16212
NXP Semiconductors
24-bit bus exchange switch with 12-bit output enables
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 November 2008
Document identifier: CBT16212_2
Similar pages