Fairchild ML6553CS-1 Bus termination regulator Datasheet

www.fairchildsemi.com
ML6553
Bus Termination Regulator
Features
General Description
• Can source and sink up to 1A
• Generates termination voltages for DDR SDRAM,
SSTL_2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for GTL+, DDR, Rambus™, VME, LV-TTL,
PECL and other high speed logic
• VL regulated to within 3% at 800mA
• Minimum external components. Requires no feedback
compensation
• Fixed frequency operation for easier system integration
• Lower power consumption than passive, resistor divider
termination, reducing heat by as much as 50%
• Separate voltages for VCCQ and PVDD
The ML6553 switching regulator is designed to convert
voltage supplies ranging from 2.0V to 3.6V into a desired
output voltage or termination voltage for various applications. The ML6553 can be implemented to produce
regulated output voltages in two different modes. In the
default mode, the output is 50% of voltage applied to VCCQ.
The switching regulator is capable of sourcing or sinking up
to 1A of current.
The ML6553, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be
used as a termination voltage for other bus interface
standards such as SSTL, DDR, Rambus™, GTL+, VME,
LV-CMOS, LV-TTL, P-ECL, and CMOS.
Block Diagram
1
4
VCCQ
5
PVDD
AVCC
CLK
190kΩ
OSCILLATOR/
RAMP GENERATOR
VL
RAMP
BUFFER
VCCQ/2
–
–
+
+
2
+
190kΩ
VINTEG
6
Q1
S
Q
R
Q
PWM
COMPARATOR
VL
7
Q2
DGND
8
–
AGND
3
REV. 1.0.2 3/21/01
ML6553
PRODUCT SPECIFICATION
Pin Configuration
ML6553
8-Pin SOIC (S08)
VCCQ
1
8
DGND
VCCQ/2
2
7
VL
AGND
3
6
VL
AVCC
4
5
PVDD
TOP VIEW
Pin Description
Pin
Name
Function
1
VCCQ
Voltage supply for internal reference voltage divider
2
VCCQ/2
VREF output is VCCQ/2
3
AGND
Analog signal ground
4
AVCC
Voltage supply for the noise sensitive analog control section.
5
PVDD
Voltage supply for the internal power transistors.
6
VL
Output inductor connection
7
VL
Output inductor connection
8
DGND
Return for the internal power transistors.
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
Min.
Max.
Unit
5
V
VIN + 0.3
V
1
A
300
mA
150
°C
150
°C
Lead Temperature (Soldering, 10 sec)
150
°C
Thermal Resistance (θJA)
160
°C/W
1
A
VIN
Voltage on Any Other Pin
GND – 0.3
Peak Switch Current (IPEAK)
Average Switch Current (IAVG)
Junction Temperature
Storage Temperature Range
–65
Output Current, Source or Sink
Operating Conditions
2
Temperature Range
0°C to 70°C
AVCC, PVDD Operating Range
2.0V to 3.6V
REV. 1.0.2 3/21/01
PRODUCT SPECIFICATION
ML6553
Electrical Characteristics
AVCC = PVDD = 3.3V ±10%. Unless otherwise specified, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max Units
VCCQ = 2.3V
1.12
1.15
1.18
Switching Regulator
VTT
VCCQ/2
IREF
Output Voltage, VTT
IOUT = 0,
(See Figure 2)
VREF = open
V
VCCQ = 2.5V
1.22
1.25
1.28
V
VCCQ = 2.7V
1.32
1.35
1.38
V
IOUT = ±1A,
VCCQ = 2.3V
1.09
1.15
1.21
V
VREF = open
VCCQ = 2.5V
1.19
1.25
1.31
V
Note 2
VCCQ = 2.7V
1.28
1.35
1.42
V
Output Voltage, VCCQ/2
VCCQ = 2.3V 1.139
1.15 1.162
V
VCCQ = 2.5V 1.238 1.25 1.263
V
VCCQ = 2.7V 1.337
V
1.35 1.364
Source Resistance from VL
20
mΩ
Switching Frequency
650
kHz
3
mA
10
µA
Output Load Current for VCCQ/2
Pin
Supply
IQ
Quiescent Current
IOUT = 0, no load
IVCCQ
IAVCC
500
µA
IPVDD
4.5
mA
Notes:
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Specifications are taken from the application circuit in Figure 2 using the recommended component values.
REV. 1.0.2 3/21/01
3
ML6553
PRODUCT SPECIFICATION
Functional Description
The ML6553 switching regulator is designed to sink and
source 1A load current and maintain a tight output voltage
regulation without the need for external feedback. Feedback
is accomplished internally by setting the average value of VL
equal to VCCQ/2 through a high gain error amp. The
ML6553 implements an open loop design that does not
require external loop compensation, providing a simplified
regulator design that can be used in cost sensitive applications.
Regulator Operation
Refer to the block diagram on the first page of this datasheet.
The oscillator/ramp block generates a 650kHz clock pulse
that is used to set the flip-flop. It also generates a 650kHz
ramp that the PWM comparator uses to reset the flip-flop.
When the flip-flop is set, the high side switch (Q1) is turned
on and the low side switch (Q2) is held off. In this state, the
voltage at VL is pulled up to PVDD, which the error amp,
integrates and inverts. The resulting output voltage of the
error amp will decline until it intersects the rising voltage of
the ramp. When this occurs the flip-flop is reset. In the reset
state, the high side switch is off, the low side switch is on
and VL is pulled to DGND. The flip-flop will remain in the
reset state until the next clock pulse. A timing diagram is
shown in Figure 1.
In the absence of a load, the duty cycle will be 50% if the
PVDD and VCCQ are the same. The average voltage at VL
will be half the voltage applied to VCCQ, and the net current
change will be zero. If the ML6553 needs to source current,
the duty cycle will increase, resulting in more current being
supplied to the load. If the ML6553 needs to sink current, the
duty will decrease, resulting in current being pulled from the
load and returned back to the PVDD supply.
VL
RAMP
VINTEG
PWMCMP
CLK
Q
Figure 1. Timing Diagram
4
REV. 1.0.2 3/21/01
PRODUCT SPECIFICATION
ML6553
Design Consideration
Input Capacitor
Inductor Selection
The ML6553 requires the selection of an external inductor.
A value of 4.7µH is a good choice, but any value between
2.2µH and 10µH is acceptable. Choosing an inductance
value of less than 2.2µH will reduce the component’s footprint or the DC resistance, but the output voltage ripple will
increase. Conversely, inductance values greater than 10µH
will reduce the output ripple, but component size and output
regulation become issues.
It is important to use an inductor that is rated to handle 1.5A
peak currents without saturating. Also look for an inductor
with low winding resistance. An inductor with low winding
resistance leads to better regulation and higher output current
capability. A good rule of thumb is to use inductors with
20mΩ or less of winding resistance.
The final selection of the inductor will be based on trade-offs
between size, cost and performance. Make your selections
carefully. Inductor tolerance, core and copper loss will vary
with the type of inductor selected and should be evaluated
with the ML6553 under worst case conditions to determine
its suitability.
Suggested inductor for L1:
Manufacturer
Coiltronics
Coiltronics
Part No.
UP3-4R7
DC
Inductance Resistance
4.7µH
0.011Ω
(561) 241-7876
Output Capacitor
The output capacitor filters the pulses of current from the bus
terminator regulator as well as lowers the AC output impedance. For the best performance, one 330µF OS-CON decoupling capacitor is recommended.
Note that data transitions on the bus cause fast changes in
output current. These fast current changes cause high
frequency spikes to appear on the output. To minimize these
effects, choose an output capacitor with a combined ESR of
less than 50mΩ and use good layout practices to minimize
trace inductance from the output capacitors to the termination resistors. In addition, it is also recommended to bypass
the termination resistors with 0.01µF ceramic capacitors.
It is recommended to de-couple the PVDD input with a 47µF
to 100µF capacitor. This provides the benefits of preventing
the input ripple from affecting the ML6553 control circuitry,
as well as improves the efficiency by reducing the I squared
R losses during the charge cycle of the inductor. Again, a low
ESR capacitor (such as tantalum) is recommended.
The AVCC input should be de-coupled with at least a
ceramic capacitor but a low pass RC filter is recommended if
the supply is particularly noisy. If a RC filter is used, the
series resistor value needs to low enough to prevent excessive voltage drops and high enough to provide effective
filtering. Resistor values on the order of 100Ω are acceptable.
The VCCQ pin can also be bypassed with a ceramic capacitor
if noise is present. The VCCQ pin can be de-coupled with a
low pass RC filter if there is significant noise pickup on its
input. If a RC filter is used, resistor values on the order of
1,000Ω are acceptable.
Layout
Good layout practices will ensure the proper operation of the
ML6553. Some layout guidelines follow:
• Use adequate ground and power traces or planes.
• Keep the 47µF-100µF input capacitor as close to PVDD
and DGND as possible.
• Use short trace lengths from the inductor to the VL pins
and from the inductor to the output capacitors.
• Use a separate trace from AGND to DGND, and use
DGND as the ground point for all the power components.
• Use additional bypass capacitors at each termination
resistor pack.
A typical application circuit schematic is shown in Figure 2,
and a sample layout is shown in Figure 3.
( DESIRED OVA – OUTPUT OVA ) × V TT
I OUT ( MAX ) = ------------------------------------------------------------------------------------------------------L DCR + 0.020
(1)
Where LDCR is the DC resistance of the output inductor, L1
in Figure 2, and 0.020 is the source resistance of the output
VL. Both LDCR and 0.020 are in Ohms.
Suitable capacitors can be obtained from the following
vendors:
AVX
Sanyo
(207) 282-5111
(619) 661-6835
REV. 1.0.2 3/21/01
TPS Series
OS-CON Series
5
ML6553
PRODUCT SPECIFICATION
Output Current Capability
The maximum current available at the output of the regulator
is related to the DC resistance of the inductor, the source
impedance of the ML6553, and the desired regulation. The
source impedance of the ML6553 can be estimated at 20mΩ
with an initial output voltage accuracy of ±1%. So the maximum output current can be estimated using:
( DESIRED OVA – INITIAL OVA )
I OUT ( MAX ) ≈ ----------------------------------------------------------------------------------- × V TT
L DCR + 0.020
So, for an inductor with 11mΩ DC resistance, a termination
voltage of 1.25V, and a desired output voltage accuracy of
3%:
( 3% – 1% ) × 1.25
I OUT ( MAX ) = --------------------------------------------------------- = 0.806A
( 0.011 + 0.020 ) × 100
VCCQ
2.5V
R1
1kΩ
VCCQ/2
PVDD
3.3V
C1
0.1µF
C2
0.1µF
R2
100Ω
C3
0.1µF
This is enough current capability to terminate 50 bus lines,
assuming 16mA of drive current per line.
Since the feedback loop is closed internally on the ML6553
the total series resistance of the L/C output filter contributes
to increased deviation from no load to full load. The output
source impedance of the ML6553 is approximately 20mΩ.
A 1A load current yields 11mV (from L1) in output
deviation +20mV from the ML6553. Be sure to factor in the
component ESR values when constrained to a particular
maximum output deviation. Adequately bypass the VTT
output with SMD film capacitors to reduce transients
generated by stray lead inductance.
(2)
U1
1
DGND
VCCQ
2
VL
VCCQ/2
3
VL
AGND
4
PVDD
AVCC
ML6553
8
7
6
5
L1
4.7µH
C5
330µF
OS-CON
VTT
C6
0.1µF
C4
100µF
GND
Figure 2. Application Schematic
Figure 3. ML6553 Board Layout
6
REV. 1.0.2 3/21/01
ML6553
PRODUCT SPECIFICATION
Mechanical Dimensions Inches (Millimeters)
S08 8-Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
PIN 1 ID
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0º - 8º
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
SEATING PLANE
Ordering Information
Part Number
Temperature Range
Package
ML6553CS-1
0°C to 70°C
8-Pin SOIC (S08)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
3/21/01 0.0m 003
Stock#DS30001584
2001 Fairchild Semiconductor Corporation
Similar pages