Microchip MCP3906A-I/SS Energy metering ics with active real power pulse output Datasheet

MCP3905A/05L/06A
Energy Metering ICs with Active Real Power Pulse Output
Features
Description
• Supplies active (real) power measurement for
single-phase, residential energy metering
• Supports IEC 62053 International Energy
Metering Specification and legacy IEC
1036/61036/687 Specifications
• Two multi-bit, DAC, second-order, 16-bit, DeltaSigma Analog-to-Digital Converters (ADCs)
• Reduced pulse-width of calibration output
frequency and mechanical counter drive for low
power meter designs (MCP3905L)
• Increased output frequency constant options for
meter design (MCP3905L)
• 0.1% typical measurement error over 500:1
dynamic range (MCP3905A / MCP3905L)
• 0.1% typical measurement error over 1000:1
dynamic range (MCP3906A)
• Programmable Gain Amplifier (PGA) for small
signal inputs supports low value shunt current
sensor:
- 16:1 PGA - MCP3905A / MCP3905L
- 32:1 PGA - MCP3906A
• Ultra-low drift on-chip reference:
15 ppm/°C (typical)
• Direct drive for electromagnetic mechanical
counter and two-phase stepper motors
• Low IDD of 4 mA (typical)
• Tamper output pin for negative power indication
• Industrial Temperature Range: -40°C to +85°C
• Extended Temperature Range: -40°C to +125°C
• Supplies instantaneous real power on HFOUT for
meter calibration
The MCP3905A/05L/06A devices are energy-metering
ICs designed to support the IEC 62053 international
metering standard specification. They supply a
frequency output proportional to the average active real
power, as well as a higher-frequency output
proportional to the instantaneous power for meter
calibration. The MCP3905L offers reduced pulse width
of calibration output frequency and mechanical counter
drive for lower power meter designs. They include two
16-bit, Delta-Sigma ADCs for a wide range of IB and
IMAX currents and/or small shunt (<200 µOhms) meter
designs. It includes an ultra-low drift voltage reference
with < 15 ppm/°C through a specially designed band
gap temperature curve for the minimum gradient
across the industrial temperature range. A fixedfunction DSP block is on-chip for active real-power
calculation. A no-load threshold block prevents any
current creep measurements. A Power-On Reset
(POR) block restricts meter performance during lowvoltage situations. These accurate energy metering ICs
with high field reliability are available in the industry
standard pinout.
Package Type
DVDD
HPF
AVDD
NC
CH0+
CH0CH1CH1+
MCLR
REFIN/OUT
AGND
F2
24-Pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FOUT0
FOUT1
HFOUT
DGND
NEG
NC
OSC2
OSC1
G0
G1
F0
F1
Functional Block Diagram
G0 G1
HPF
OSC1 OSC2
HFOUT
CH0+
CH0-
+
PGA
–
16-bit
Multi-level
ΔΣ ADC
REFIN/
OUT
X
2.4V
Reference
CH1+
+
CH1-
–
F2
HPF1
16-bit
Multi-level
ΔΣ ADC
© 2006-2011 Microchip Technology Inc.
HPF1
F1
F0
FOUT0
FOUT1
NEG
E-to-F
conversion
LPF1
POR
MCLR
DS22011B-page 1
MCP3905A/05L/06A
NOTES:
DS22011B-page 2
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Absolute Maximum Ratings †
VDD...................................................................................7.0V
Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V
Analog input w.r.t. AGND ..................................... ....-6V to +6V
VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) ................. 5.0 kV, 500V
ESD on all other pins (HBM,MM) ........................ 5.0 kV, 500V
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ
Max
Units
Comment
E
—
0.1
—
% FOUT Channel 0 swings 1:500 range,
MCP3905A, MCP3905L only
(Note 1, Note 4)
—
0.1
—
% FOUT Channel 0 swings 1:1000 range,
MCP3906A only (Note 1, Note 4)
—
0.0015
—
% FOUT Disabled when F2, F1, F0 = 0, 1, 1
Max
(Note 5, Note 6)
—
—
1/MCLK
Overall Measurement Accuracy
Energy Measurement Error
No-Load Threshold/
Minimum Load
NLT
Phase Delay Between
Channels
s
HPF = 0 and 1, < 1 MCLK
(Note 4, Note 6, Note 7)
AC Power Supply Rejection
(output frequency variation)
AC PSRR
—
0.01
—
% FOUT F2, F1, F0 = 0, 1, 1 (Note 3)
DC Power Supply Rejection
DC PSRR
—
0.01
—
% FOUT HPF = 1, Gain = 1 (Note 3)
—
3
10
% FOUT (Note 2, Note 5)
(output frequency
variation)
System Gain Error
ADC/PGA Specifications
Offset Error
VOS
Gain Error Match
—
2
5
—
0.5
—
—
2.4
—
mV
Referred to Input
% FOUT (Note 5)
Internal Voltage Reference
Voltage
V
Tolerance
—
±2
—
%
Tempco
—
15
—
ppm/°C
Note 1:
2:
3:
4:
5:
6:
7:
Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz.
See typical performance curves for higher frequencies and increased dynamic range.
Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @
50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV
Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).
Refer to Section 4.0 “Device Overview” for complete description.
Specified by characterization, not production tested.
1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.
© 2006-2011 Microchip Technology Inc.
DS22011B-page 3
MCP3905A/05L/06A
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ
Max
Units
Comment
Reference Input
Input Range
2.2
—
2.6
V
Input Impedance
3.2
—
—
kΩ
Input Capacitance
—
—
10
pF
Analog Inputs
Maximum Signal Level
—
—
±1
V
Differential Input Voltage
Range Channel 0
—
—
±470/G
mV
Differential Input Voltage
Range Channel 1
—
—
±660
mV
390
—
—
kΩ
Proportional to 1/MCLK frequency
—
14
—
kHz
Proportional to MCLK frequency,
MCLK/256
1
—
4
MHz
4.5
—
5.5
V
Input Impedance
Bandwidth
(Notch Frequency)
CH0+,CH0-,CH1+,CH1- to AGND
G = PGA Gain on Channel 0
Oscillator Input
Frequency Range
MCLK
Power Specifications
Operating Voltage
AVDD, DVDD
IDD,A
IDD,A
—
2.7
3.0
mA
AVDD pin only
IDD,D
IDD,D
—
1.2
2.0
mA
DVDD pin only
Note 1:
2:
3:
4:
5:
6:
7:
Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz.
See typical performance curves for higher frequencies and increased dynamic range.
Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @
50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV
Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).
Refer to Section 4.0 “Device Overview” for complete description.
Specified by characterization, not production tested.
1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 4.5V – 5.5V, AGND, DGND = 0V.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Note:
(Note)
The MCP3905A/05L/06A operate over this extended temperature range, but with reduced performance. In
any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
DS22011B-page 4
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,
AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ
Max
Units
Comment
FOUT0 and FOUT1 Pulse Width
(Logic Low) for MCP3905A, MCP3906A
devices
tFW
—
275
—
ms
984376 MCLK periods
(Note 1)
HFOUT Pulse Width for MCP3905A,
MCP3906A devices
tHW
—
90
—
ms
322160 MCLK periods
(Note 2)
FOUT0 and FOUT1 Pulse Width
(Logic Low) for MCP3905L device
tFW
—
130
—
ms
465344 MCLK periods
(Note 1)
HFOUT Pulse Width for MCP3905L
device
tHW
—
65
—
ms
232672 MCLK periods
(Note 2)
FOUT0 and FOUT1 Pulse Period
tFP
Refer to Equation 4-1
s
HFOUT Pulse Period
tHP
Refer to Equation 4-2
s
Frequency Output
FOUT0 to FOUT1 Falling-Edge Time
tFS2
—
0.5 tFP
—
FOUT0 to FOUT1 Min Separation
tFS
—
4/MCLK
—
FOUT0 and FOUT1 Output High Voltage
VOH
4.5
—
—
V
IOH = 10 mA, DVDD = 5.0V
FOUT0 and FOUT1 Output Low Voltage
VOL
—
—
0.5
V
IOL = 10 mA, DVDD = 5.0V
HFOUT Output High Voltage
VOH
4.0
—
—
V
IOH = 5 mA, DVDD = 5.0V
HFOUT Output Low Voltage
VOL
—
—
0.5
V
IOL = 5 mA, DVDD = 5.0V
High-Level Input Voltage
(All Digital Input Pins)
VIH
2.4
—
—
V
DVDD = 5.0V
Low Level Input Voltage
(All Digital Input Pins)
VIL
—
—
0.85
V
DVDD = 5.0V
Input Leakage Current
—
—
±3
µA
VIN = 0, VIN = DVDD
Pin Capacitance
—
—
10
pF
Note 3
Note 1:
2:
3:
If output pulse period (tFP) falls below 984376*2 MCLK periods for MCP3905A/6A and 465344*2 MCLK
periods for MCP3905L, then tFW = 1/2 tFP.
If output pulse period (tHP) falls below 322160*2 MCLK periods for MCP3905A/6A and 232672*2 MCLK
periods for MCP3905L, then tHW = 1/2 tHP. When F2, F1,F0 = 011, tHW is fixed to 18 µs (64 MCLK
periods).
Specified by characterization, not production tested.
© 2006-2011 Microchip Technology Inc.
DS22011B-page 5
MCP3905A/05L/06A
tFP
tFW
FOUT0
tFS
tFS2
FOUT1
tHW
HFOUT
tHP
NEG
FIGURE 1-1:
DS22011B-page 6
Output Timings for Pulse Outputs and Negative Power Pin.
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0000
Measurement Error
Measurement Error
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
+85°C
+25°C
`
-40°C
0.0001
0.0010
0.0100
0.1000
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0000
CH1 Vp-p Amplitude (V)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0000
Measurement Error,
+25°C
- 40°C
0.0010
0.0100
0.1000
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0000
FIGURE 2-2:
Measurement Error,
Gain = 16, PF = 1.
0.25
+25°C
- 40°C
-0.25
0.0001
0.0010
0.0100
CH1 Vp-p Amplitude (V)
FIGURE 2-3:
Measurement Error,
Gain = 32, PF = 1.
© 2006-2011 Microchip Technology Inc.
0.1000
Measurement Error
Measurement Error
+85°C
0.5
-0.5
0.0000
0.0010
0.0100
0.1000
+85°C
+25°C
-40°C
0.0001
0.0010
0.0100
0.1000
FIGURE 2-5:
Measurement Error,
Gain = 16, PF = 0.5.
1
0
0.0001
CH1 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
0.75
-40°C
FIGURE 2-4:
Measurement Error,
Gain = 8, PF = 0.5.
+85°C
0.0001
+25°C
CH1 Vp-p Amplitude (V)
Measurement Error
Measurement Error
FIGURE 2-1:
Gain = 8 PF = 1.
+85°C
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
+85°C
+25°C
-40°C
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
FIGURE 2-6:
Measurement Error,
Gain =32, PF = 0.5.
DS22011B-page 7
MCP3905A/05L/06A
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0001
Measurement Error
Measurement Error
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
+85°C
+25°C
- 40°C
0.0010
0.0100
0.1000
1.0000
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0001
Measurement Error,
+85°C
+25°C
- 40°C
0.0010
0.0100
0.1000
CH0 Vp-p Amplitude (V)
FIGURE 2-8:
Gain = 2, PF = 1.
DS22011B-page 8
Measurement Error,
-40°C
0.0010
0.0100
0.1000
1.0000
FIGURE 2-9:
Measurement Error,
Gain = 1, PF = + 0.5.
1.0000
Measurement Error
Measurement Error
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0001
+25°C
CH1 Vp-p Amplitude (V)
CH0 Vp-p Amplitude (V)
FIGURE 2-7:
Gain = 1, PF = 1.
+85°C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0001
+85°C
+25°C
-40°C
0.0010
0.0100
0.1000
1.0000
CH1 Vp-p Amplitude (V)
FIGURE 2-10:
Measurement Error,
Gain = 2, PF = + 0.5.
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
+25°C; PF = 1
Measurement Error (%)
Measurement Error (%)
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
+25°C; PF = 0.5
+125°C; PF = 0.5
+125°C; PF = 1
0.001
0.01
0.1
CH1 Vp-p Amplitude (V)
1
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
+25°C; PF = 1
+25°C; PF = 0.5
+125°C; PF = 0.5
+125°C; PF = 1
0.001
0.01
0.1
CH1 Vp-p Amplitude (V)
FIGURE 2-12:
Measurement Error,
Temperature = +125°C, Gain = 2.
© 2006-2011 Microchip Technology Inc.
1
FIGURE 2-13:
Measurement Error,
Temperature = +125°C, Gain = 8.
Measurement Error (%)
Measurement Error (%)
FIGURE 2-11:
Measurement Error,
Temperature = +125°C, Gain = 1.
1
0.8
0.6
+25°C; PF = 1
0.4
+25°C; PF = 0.5
0.2
0
+125°C; PF = 0.5
-0.2
-0.4
-0.6
+125°C; PF = 1
-0.8
-1
0.0001
0.001
0.01
0.1
CH1 Vp-p Amplitude (V)
1
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
+25°C; PF = 1
+25°C; PF = 0.5
+125°C; PF = 0.5
+125°C; PF = 1
0.001
0.01
0.1
CH1 Vp-p Amplitude (V)
1
FIGURE 2-14:
Measurement Error,
Temperature = +125°C, Gain = 16.
DS22011B-page 9
MCP3905A/05L/06A
2500
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
2000
PF = 0.5
Occurance
16384 Samples
Mean = - 234.7 µV
Std. dev = - 6.91 µV
1500
1000
500
PF = 1
Measurement Error vs.
2000
1500
1000
500
VDD=4.5V
0.05
0
-0.05
0.0010
FIGURE 2-19:
(G = 16).
16384 Samples
Mean = -470.2 µV
Std. Dev = 13.8 µV
2500
2000
1500
1000
500
Channel 0 Offset (V)
FIGURE 2-17:
Channel 0 Offset Error
(DC Mode, HPF off), G = 8.
-434.6E-6
-440.1E-6
-445.6E-6
-450.6E-6
-456.1E-6
-461.6E-6
-467.1E-6
-472.6E-6
-477.6E-6
-483.1E-6
0
-488.6E-6
-217.5E-6
-220.5E-6
-223.5E-6
VDD=5.5V
-0.15
0.0001
0.0100
0.1000
1.0000
Measurement Error vs. VDD
0.25
Measurement Error
3000
VDD=4.75V
VDD=5.25V
CH0 Vp-p Amplitude (V)
FIGURE 2-16:
Channel 0 Offset Error
(DC Mode, HPF off), G = 1.
-494.1E-6
-226.5E-6
VDD=5.0V
0.1
Channel 0 Offset (V)
-499.6E-6
-229.5E-6
0.2
0.15
-0.1
-3.45E-3
-3.50E-3
-3.55E-3
-3.60E-3
-3.65E-3
-3.70E-3
-3.75E-3
-3.80E-3
-3.85E-3
-3.90E-3
-3.95E-3
-4.00E-3
0
Occurance
-231.5E-6
0.3
0.25
Measurement Error
2500
Occurance
FIGURE 2-18:
Channel 0 Offset Error
(DC Mode, HPF Off), G = 16.
16384 Samples
Mean = -3.76 mV
Std. Dev = 110.4 µV
3000
DS22011B-page 10
-234.5E-6
Channel 0 Offset (V)
Frequency (Hz)
FIGURE 2-15:
Input Frequency.
-237.5E-6
80
-240.5E-6
70
-243.5E-6
60
-246.5E-6
50
-248.5E-6
40
-249.5E-6
0
-251.5E-6
Measurement Error (%)
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
0.2
0.15
VDD=4.75V
0.1
0.05
VDD=4.5V
VDD=5.0V
0
VDD=5.25V
-0.05
-0.1
0.0001
VDD=5.5V
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
FIGURE 2-20:
Measurement Error vs. VDD,
G = 16, External VREF .
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
0.3
0.3
0.2
0.2
0.1
+85°C
0
+25°C
- 40°C
-0.1
-0.2
-0.3
0.0001
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
Measurement Error
Measurement Error
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
+85°C
+25°C
0.1
0
- 40°C
-0.1
-0.2
-0.3
0.0000
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
FIGURE 2-21:
Measurement Error
w/ External VREF, (G = 1).
FIGURE 2-23:
Measurement Error
w/ External VREF (G = 16).
Measurement Error
0.3
0.2
+85°C
0.1
+25°C
0
-40°C
-0.1
-0.2
-0.3
0.0000
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
FIGURE 2-22:
Measurement Error
w/ External VREF (G = 8).
© 2006-2011 Microchip Technology Inc.
DS22011B-page 11
MCP3905A/05L/06A
NOTES:
DS22011B-page 12
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
PIN FUNCTION TABLE
Pin No.
Symbol
1
DVDD
Function
Digital Power Supply Pin
2
HPF
High-Pass Filters Control Logic Pin
3
AVDD
Analog Power Supply Pin
4
NC
5
CH0+
Non-Inverting Analog Input Pin for Channel 0 (Current Channel)
No Connect
6
CH0-
Inverting Analog Input Pin for Channel 0 (Current Channel)
7
CH1-
Inverting Analog Input Pin for Channel 1 (Voltage Channel)
8
CH1+
Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)
9
MCLR
Master Clear Logic Input Pin
10
REFIN/OUT
11
AGND
Voltage Reference Input/Output Pin
Analog Ground Pin, Return Path for internal analog circuitry
12
F2
Frequency Control for HFOUT Logic Input Pin
13
F1
Frequency Control for FOUT0/1 Logic Input Pin
14
F0
Frequency Control for FOUT0/1 Logic Input Pin
15
G1
Gain Control Logic Input Pin
16
G0
Gain Control Logic Input Pin
17
OSC1
Oscillator Crystal Connection Pin or Clock Input Pin
18
OSC2
Oscillator Crystal Connection Pin or Clock Output Pin
19
NC
No Connect
20
NEG
Negative Power Logic Output Pin
21
DGND
Digital Ground Pin, Return Path for Internal Digital Circuitry
22
HFOUT
High-Frequency Logic Output Pin (Intended for Calibration)
23
FOUT1
Differential Mechanical Counter Logic Output Pin
24
FOUT0
Differential Mechanical Counter Logic Output Pin
Digital VDD (DVDD)
DVDD is the power supply pin for the digital circuitry
within the MCP3905A/05L/06A devices.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation. Refer to Section 5.0 “Applications
Information”.
3.2
High-Pass Filter Input Logic Pin
(HPF)
HPF controls the state of the high-pass filter in both
input channels. A logic ‘1’ enables both filters,
removing any DC offset coming from the system or the
device. A logic ‘0’ disables both filters, allowing DC
voltages to be measured.
3.3
Analog VDD (AVDD)
AVDD is the power supply pin for the analog circuitry
within the MCP3905A/05L/06A devices.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation. Refer to Section 5.0 “Applications
Information”.
3.4
Current Channel (CH0-, CH0+)
CH0- and CH0+ are the fully differential analog voltage
input channels for the current measurement, containing
a PGA for small-signal input, such as shunt current
sensing. The linear and specified region of this channel
is dependant on the PGA gain. This corresponds to a
maximum differential voltage of ±470 mV/GAIN and
maximum absolute voltage, with respect to AGND, of
±1V. Up to ±6V can be applied to these pins without the
risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
© 2006-2011 Microchip Technology Inc.
DS22011B-page 13
MCP3905A/05L/06A
3.5
Voltage Channel (CH1-,CH1+)
CH1- and CH1+ are the fully differential analog voltage
input channels for voltage measurement. The linear
and specified region of these channels have a
maximum differential voltage of ±660 mV and a
maximum absolute voltage of ±1V, with respect to
AGND. Up to ±6V can be applied to these pins without
the risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
3.6
Master Clear (MCLR)
MCLR controls the reset for both delta-sigma ADCs, all
digital registers, the SINC filters for each channel and
all accumulators post multiplier. A logic ‘0’ resets all
registers and holds both ADCs in a Reset condition.
The charge stored in both ADCs is flushed and their
output is maintained to 0x0000h. The only block
consuming power on the digital power supply during
Reset is the oscillator circuit.
3.7
Reference (REFIN/OUT)
REFIN/OUT is the output for the internal 2.4V
reference. This reference has a typical temperature
coefficient of 15 ppm/°C and a tolerance of ±2%. In
addition, an external reference can also be used by
applying voltage to this pin within the specified range.
This pin requires appropriate bypass capacitors to
AGND, even when using the internal reference only.
Refer to Section 5.0 “Applications Information”.
3.8
Analog Ground (AGND)
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, band gap reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this device be tied to
this plane of the PCB. This plane should also reference
all other analog circuitry in the system.
3.9
Frequency Control Logic Pins
(F2, F1, F0)
F2, F1 and F0 select the high-frequency output and
low-frequency output pin ranges by changing the
value of the constants FC and HFC used in the device
transfer function. FC and HFC are the frequency
constants that define the period of the output pulses
for the device.
3.10
Gain Control Logic Pins (G1, G0)
G1 and G0 select the PGA gain on Channel 0 from
three different values: 1, 8 and 16.
DS22011B-page 14
3.11
Oscillator (OSC1, OSC2)
OSC1 and OSC2 provide the master clock for the
device. A resonant crystal or clock source with a similar
sinusoidal waveform must be placed across these pins
to ensure proper operation. The typical clock frequency
specified is 3.579545 MHz. However, the clock
frequency can be with the range of 1 MHz to 4 MHz
without disturbing measurement error. Appropriate
load capacitance should be connected to these pins for
proper operation.
A full-swing, single-ended clock source may be
connected to OSC1 with proper resistors in series to
ensure no ringing of the clock source due to fast
transient edges.
3.12
Negative Power Output Logic Pin
(NEG)
NEG detects the phase difference between the two
channels and will go to a logic ‘1’ state when the phase
difference is greater than 90° (i.e., when the measured
real power is negative). The output state is synchronous with the rising-edge of HFOUT and maintains the
logic ‘1’ until the real power becomes positive again
and HFOUT shows a pulse.
3.13
Ground Connection (DGND)
DGND is the ground connection to internal digital
circuitry (SINC filters, multiplier, HPF, LPF, digital-tofrequency converter and oscillator). To ensure
accuracy and noise cancellation, DGND must be
connected to the same ground as AGND, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this device be tied to
this plane of the Printed Circuit Board (PCB). This
plane should also reference all other digital circuitry in
the system.
3.14
High-Frequency Output (HFOUT)
HFOUT is the high-frequency output of the device and
supplies the instantaneous real-power information. The
output is a periodic pulse output, with its period
proportional to the measured real power, and to the
HFC constant defined by F0, F1 and F2 pin logic states.
This output is the preferred output for calibration due to
faster output frequencies, giving smaller calibration
times. Since this output gives instantaneous real
power, the 2ω ripple on the output should be noted.
However, the average period will show minimal drift.
3.15
Frequency Output (FOUT0, FOUT1)
FOUT0 and FOUT1 are the frequency outputs of the
device that supply the average real-power information.
The outputs are periodic pulse outputs, with its period
proportional to the measured real power, and to the Fc
constant, defined by F0 and F1 pin logic states. These
pins include high-output drive capability for direct use
of electromechanical counters and 2-phase stepper
motors. Since this output supplies average real power,
any 2ω ripple on the output pulse period is minimal.
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
4.0
DEVICE OVERVIEW
The instantaneous power signal contains the realpower information; it is the DC component of the
instantaneous power. The averaging technique can be
used with both sinusoidal and non-sinusoidal
waveforms, as well as for all power factors. The
instantaneous power is thus low-pass filtered in order
to produce the instantaneous real-power signal.
The MCP3905A/05L/06A devices are energy metering
ICs that supply a frequency output proportional to
active (real) power, and higher frequency output
proportional to the instantaneous power for meter
calibration. Both channels use 16-bit, second-order,
delta-sigma ADCs that oversample the input at a
frequency equal to MCLK/4, allowing for wide dynamic
range input signals. A Programmable Gain Amplifier
(PGA) increases the usable range on the current input
channel (Channel 0). The calculation of the active
power, and the filtering associated with this calculation
is performed in the digital domain, ensuring better
stability and drift performance. Figure 4-1 represents
the
simplified
block
diagram
of
the
MCP3905A/05L/06A, detailing its main signal
processing blocks.
A digital-to-frequency converter accumulates the
instantaneous active real power information to produce
output pulses with a frequency proportional to the
average real power. The low-frequency pulses present
at the FOUT0 and FOUT1 outputs are designed to drive
electromechanical counters and two-phase stepper
motors displaying the real-power energy consumed.
Each pulse corresponds to a fixed quantity of real
energy, selected by the F2, F1 and F0 logic settings.
The HFOUT output has a higher frequency setting and
less integration period such that it can represent the
instantaneous real-power signal. Due to the shorter
accumulation time, it enables the user to proceed to
faster calibration under steady load conditions (see
and
HFOUT
Output
Section 4.7
“FOUT0/1
Frequencies”).
Two digital high-pass filters cancel the system offset on
both channels such that the real-power calculation
does not include any circuit or system offset. After
being high-pass filtered, the voltage and current signals
are multiplied to give the instantaneous power signal.
This signal does not contain the DC offset components,
such that the averaging technique can be efficiently
used to give the desired active-power output.
MCP3905
MCP390X
CH0+
+
CH0-
–
PGA
ADC
ANALOG
HPF
X
DIGITAL
LPF
CH1+
+
CH1-
–
ADC
F OUT0
FOUT1
HF OUT
..0101...
DTF
HPF
Frequency
Content
0
Input Signal with
System Offset and
Line Frequency
FIGURE 4-1:
0
ADC Output Code
Contains System
and ADC Offset
0
DC Offset
Removed by HPF
0
0
Instantaneous
Power
Instantaneous
Real Power
Simplified MCP3905A/05L/06A Block Diagram with Frequency Contents.
© 2006-2011 Microchip Technology Inc.
DS22011B-page 15
MCP3905A/05L/06A
Analog Inputs
4.2
The MCP3905A/05L/06A analog inputs can be
connected directly to the current and voltage
transducers (such as shunts or current transformers).
Each input pin is protected by specialized ESD
structures that are certified to pass 5 kV HBM and
500V MM contact charge. These structures also allow
up to ±6V continuous voltage to be present at their
inputs without the risk of permanent damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to AGND should be maintained in the ±1V
range during operation in order to ensure the
measurement error performance. The common-mode
signals should be adapted to respect both the previous
conditions and the differential input voltage range. For
best performance, the common-mode signals should
be referenced to AGND.
The current channel comprises a PGA on the front-end
to allow for smaller signals to be measured without
additional signal conditioning. The maximum differential voltage specified on Channel 0 is equal to
±470 mV/Gain (see Table 4-1). The maximum peak
voltage specified on Channel 1 is equal to ±660 mV.
.
TABLE 4-1:
MCP3905A/MCP3905L GAIN
SELECTIONS
G1
G0
CH0 Gain
Maximum
CH0 Voltage
0
0
1
1
0
1
0
1
1
2
8
16
±470 mV
±235 mV
±60 mV
±30 mV
TABLE 4-2:
MCP3906A GAIN
SELECTIONS
G1
G0
CH0 Gain
Maximum
CH0 Voltage
0
0
1
1
0
1
0
1
1
32
8
16
±470 mV
±15 mV
±60 mV
±30 mV
16-Bit Delta-Sigma A/D Converters
The ADCs used in the MCP3905A/05L/06A for both
current and voltage channel measurements are deltasigma ADCs. They comprise a second-order, deltasigma modulator using a multi-bit DAC and a thirdorder SINC filter. The delta-sigma architecture is very
appropriate for the applications targeted by the
MCP3905A/05L/06A because it is a waveform-oriented
converter architecture that can offer both high linearity
and low distortion performance throughout a wide input
dynamic range. It also creates minimal requirements
for the anti-aliasing filter design. The multi-bit
architecture used in the ADC minimizes quantization
noise at the output of the converters without disturbing
the linearity.
Both ADCs have a 16-bit resolution, allowing wide input
dynamic range sensing. The oversampling ratio of both
converters is 64. Both converters are continuously
converting during normal operation. When the MCLR
pin is low, both converters will be in Reset and output
code 0x0000h. If the voltage at the inputs of the ADC is
larger than the specified range, the linearity is no longer
specified. However, the converters will continue to
produce output codes until their saturation point is
reached. The DC saturation point is around 700 mV for
Channel 0 and 1V for Channel 1, using internal voltage
reference.
The clocking signals for the ADCs are equally
distributed between the two channels in order to
minimize phase delays to less than 1 MCLK period
(see Section 3.2 “High-Pass Filter Input Logic Pin
(HPF)”). The SINC filter’s main notch is positioned at
MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing
the user to be able to measure wide harmonic content
on either channel. The magnitude response of the
SINC filter is shown in Figure 4-2.
Normal Mode Rejection (dB)
4.1
0
-20
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
Frequency (kHz)
FIGURE 4-2:
SINC Filter Magnitude
Response (MCLK = 3.58 MHz).
DS22011B-page 16
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
Ultra-Low Drift VREF
The MCP3905A/05L/06A devices contain an internal
voltage reference source specially designed to minimize drift over temperature. This internal VREF supplies
reference voltage to both current and voltage channel
ADCs. The typical value of this voltage reference is
2.4V ±100 mV. The internal reference has a very low
typical temperature coefficient of ±15 ppm/°C, allowing
the output frequencies to have minimal variation with
respect to temperature since they are proportional to
(1/VREF)².
The output pin for the voltage reference is REFIN/OUT.
Appropriate bypass capacitors must be connected to
the REFIN/OUT pin for proper operation (see
Section 5.0 “Applications Information”). The
voltage reference source impedance is typically 4 kΩ,
which enables this voltage reference to be overdriven
by an external voltage reference source.
If an external voltage reference source is connected to
the REFIN/OUT pin, the external voltage will be used
as the reference for both current and voltage channel
ADCs. The voltage across the source resistor will then
be the difference between the internal and external
voltage. The allowed input range for the external
voltage source goes from 2.2V to 2.6V for accurate
measurement error. A VREF value outside of this range
will cause additional heating and power consumption
due to the source resistor, which might affect measurement error.
4.4
Power-On Reset (POR)
The MCP3905A/05L/06A devices contain an internal
POR circuit that monitors analog supply voltage AVDD
during operation. This circuit ensures correct device
startup at system power-up and system power-down
events. The POR circuit has built-in hysteresis and a
timer to give a high degree of immunity to potential
ripple and noise on the power supplies, allowing proper
settling of the power supply during power-up. A 0.1 µF
decoupling capacitor should be mounted as close as
possible to the AVDD pin, providing additional transient
immunity
(see
Section 5.0
“Applications
Information”).
The threshold voltage is typically set at 4V, with a
tolerance of about ±5%. If the supply voltage falls below
this threshold, the MCP3905A/05L/06A devices will be
held in a Reset condition (equivalent to applying logic
‘0’ on the MCLR pin). The typical hysteresis value is
approximately 200 mV in order to prevent glitches on
the power supply.
Once a power-up event has occurred, an internal timer
prevents the part from outputting any pulse for
approximately 1s (with MCLK = 3.58 MHz), thereby
preventing potential metastability due to intermittent
resets caused by an unsettled regulated power supply.
© 2006-2011 Microchip Technology Inc.
Figure 4-3 illustrates the different conditions for a
power-up and a power-down event in the typical
conditions.
AVDD
5V
4.2V
4V
1s
0V
DEVICE
MODE
RESET
NO
PULSE
OUT
FIGURE 4-3:
4.5
Time
PROPER
OPERATION
RESET
Power-on Reset Operation.
High-Pass Filters and Multiplier
The active real-power value is extracted from the DC
instantaneous power. Therefore, any DC offset
component present on Channel 0 and Channel 1
affects the DC component of the instantaneous power
and will cause the real-power calculation to be
erroneous. In order to remove DC offset components
from the instantaneous power signal, a high-pass filter
has been introduced on each channel. Since the highpass filtering introduces phase delay, identical highpass filters are implemented on both channels. The
filters are clocked by the same digital signal, ensuring
a phase difference between the two channels of less
than one MCLK period. Under typical conditions
(MCLK = 3.58 MHz), this phase difference is less than
0.005°, with a line frequency of 50 Hz. The cut-off
frequency of the filter (4.45 Hz) has been chosen to
induce minimal gain error at typical line frequencies,
allowing sufficient settling time for the desired
applications. The two high-pass filters can be disabled
by applying logic ‘0’ to the HPF pin.
Normal Mode Rejection (dB)
4.3
0
-5
-10
-15
-20
-25
-30
-35
-40
0.1
1
10
100
1000
Frequency (Hz)
FIGURE 4-4:
HPF Magnitude Response
(MCLK = 3.58 MHz).
DS22011B-page 17
MCP3905A/05L/06A
The multiplier output gives the product of the two highpass filtered channels, corresponding to instantaneous
real power. Multiplying two sine wave signals by the
same ω frequency gives a DC component and a 2ω
component. The instantaneous power signal contains
the real power of its DC component, while also containing 2ω components coming from the line frequency
multiplication. These 2ω components come for the line
frequency (and its harmonics) and must be removed in
order to extract the real-power information. This is
accomplished using the low-pass filter and DTF
converter.
The equivalent quantity of real energy required to
output a pulse is much larger for the FOUT0/1 outputs
than the HFOUT. This is such that the integration period
for the FOUT0/1 outputs is much larger. This larger
integration period acts as another low-pass filter so that
the output ripple due to the 2ω components is minimal.
However, these components are not totally removed,
since realized low-pass filters are never ideal. This will
create a small jitter in the output frequency. Averaging
the output pulses with a counter or a MCU in the
application will then remove the small sinusoidal
content of the output frequency and filter out the
remaining 2ω ripple.
4.6
HFOUT is intended to be used for calibration purposes
due to its instantaneous power content. The shorter
integration period of HFOUT demands that the 2ω
component be given more attention. Since a sinusoidal
signal average is zero, averaging the HFOUT signal in
steady-state conditions will give the proper real energy
value.
Low-Pass Filter and DTF
Converter
The MCP3905A/05L/06A low-pass filter is a first-order
IIR filter that extracts the active real-power information
(DC component) from the instantaneous power signal.
The magnitude response of this filter is detailed in
Figure 4-5. Due to the fact that the instantaneous power
signal has harmonic content (coming from the 2ω
components of the inputs), and since the filter is not
ideal, there will be some ripple at the output of the lowpass filter at the harmonics of the line frequency.
Normal Mode Rejection (dB)
The cut-off frequency of the filter (8.9 Hz) has been
chosen to have sufficient rejection for commonly-used
line frequencies (50 Hz and 60 Hz). With a standard
input clock (MCLK = 3.58 MHz) and a 50 Hz line
frequency, the rejection of the 2ω component (100 Hz)
will be more than 20 dB. This equates to a 2ω
component containing 10 times less power than the
main DC component (i.e., the average active real
power).
4.7
FOUT0/1 and HFOUT Output
Frequencies
The thresholds for the accumulated energy are
different for FOUT0/1 and HFOUT (i.e., they have
different transfer functions). The FOUT0/1 allowed
output frequencies are quite low in order to allow
superior integration time (see Section 4.6 “Low-Pass
Filter and DTF Converter”). The FOUT0/1 output
frequency can be calculated with the following
equation:
EQUATION 4-1:
FOUT FREQUENCY
OUTPUT EQUATION
8.06 × V 0 × V1 × G × F C
F OUT ( Hz ) = ---------------------------------------------------------2
( VREF )
0
-5
-10
Where:
-15
V0 is the RMS differential voltage on Channel 0
V1 is the RMS differential voltage on Channel 1
G is the PGA gain on Channel 0 (current channel)
FC is the frequency constant selected
VREF is the voltage reference
-20
-25
-30
-35
-40
0.1
1
10
100
1000
Frequency (Hz)
FIGURE 4-5:
LPF Magnitude Response
(MCLK = 3.58 MHz).
The output of the low-pass filter is accumulated in the
digital-to-frequency converter. This accumulation is
compared to a different digital threshold for FOUT0/1
and HFOUT, representing a quantity of real energy measured by the part. Every time the digital threshold on
FOUT0/1 or HFOUT is crossed, the part will output a
pulse (See Section 4.7 “FOUT0/1 and HFOUT Output
Frequencies”).
DS22011B-page 18
For a given DC input V, the DC and RMS values are
equivalent. For a given AC input signal with peak-topeak amplitude of V, the equivalent RMS value is
V/sqrt(2), assuming purely sinusoidal signals. Note
that since the real power is the product of two RMS
inputs, the output frequencies of AC signals are half of
the DC inputs ones, again assuming purely sinusoidal
AC signals. The constant FC depends on the FOUT0
and FOUT1 digital settings. Table 4-3 shows FOUT0/1
output frequencies for the different logic settings.
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
The high-frequency output HFOUT has lower
integration times and, thus, higher frequencies. The
output frequency value can be calculated with the
following equation:
EQUATION 4-2:
HFOUT FREQUENCY
OUTPUT EQUATION
8.06 × V 0 × V 1 × G × HFC
HF OUT ( Hz ) = --------------------------------------------------------------2
( VREF )
Where:
V0 is the RMS differential voltage on channel 0
V1 is the RMS differential voltage on channel 1
G is the PGA gain on channel 0 (current channel)
HFC is the frequency constant selected
VREF is the voltage reference
The constant HFC depends on the FOUT0 and FOUT1
digital settings with the Table 4-4.
The detailed timings of the output pulses are described
in the Timing Characteristics table (see Section 1.0
“Electrical Characteristics” and Figure 1-1).
TABLE 4-3:
4.7.1
MINIMAL OUTPUT FREQUENCY
FOR
NO-LOAD THRESHOLD
The MCP3905A/05L/06A devices also include, on
each output frequency, a no-load threshold circuit that
will eliminate any creep effects in the meter. The
outputs will not show any pulse if the output frequency
falls below the no-load threshold. The minimum output
frequency on FOUT0/1 and HFOUT is equal to 0.0015%
of the maximum output frequency (respectively FC and
HFC) for each of the F2, F1 and F0 selections (see
Table 4-3 and Table 4-4); except when F2, F1,
F0 = 011. In this last configuration, the no-load
threshold feature is disabled. The selection of FC will
determine the start-up current load. In order to respect
the IEC standards requirements, the meter will have to
be designed to allow start-up currents compatible with
the standards by choosing the FC value matching
these requirements. For additional applications
information on no-load threshold, startup current and
other meter design points, refer to AN994, "IEC
Compliant Active Energy Meter Design Using The
MCP3905/6”, (DS00994).
MCP3905L OUTPUT FREQUENCY SETTINGS
F2
F1
F0
HFC
HFC (Hz)
HFC (Hz),
MCLK=3.58 MHz
HFOUT (Hz),
w/ full scale
AC inputs
FC (Hz)
FC (Hz),
MCLK=3.58 MHz
0
0
0
64XFC
MCLK/215
109.25
23.71
MCLK/221
1.71
32XFC
MCLK/215
109.25
23.71
MCLK/220
3.41
6.83
0
0
1
0
1
0
16XFC
MCLK/215
109.25
23.71
MCLK/219
0
1
1
2048XFC
MCLK/27
27968.75
6070.12
MCLK/218
13.66
1
0
0
8XFC
MCLK/216
54.62
11.85
MCLK/219
6.83
64XFC
MCLK/216
11.85
MCLK/222
0.85
54.62
11.85
MCLK/221
1.71
54.62
11.85
MCLK/220
3.41
1
0
1
1
1
0
32XFC
MCLK/216
1
1
1
16XFC
MCLK/216
TABLE 4-4:
54.62
MCP3905A/06A OUTPUT FREQUENCY SETTINGS
F2
F1
F0
HFC
HFC (Hz)
HFC (Hz),
MCLK=3.58 MHz
HFOUT (Hz),
w/ full scale
AC inputs
FC (Hz)
FC (Hz),
MCLK=3.58 MHz
0
0
0
64XFC
MCLK/215
109.25
23.71
MCLK/221
1.71
32XFC
MCLK/215
109.25
23.71
MCLK/220
3.41
6.83
0
0
1
0
1
0
16XFC
MCLK/215
109.25
23.71
MCLK/219
0
1
1
2048XFC
MCLK/27
27968.75
6070.12
MCLK/218
13.66
1
0
0
128XFC
MCLK/214
219.51
47.42
MCLK/221
1.71
64XFC
MCLK/214
219.51
47.42
MCLK/220
3.41
14
219.51
47.42
MCLK/2
19
219.51
47.42
MCLK/218
1
0
1
1
1
0
32XFC
MCLK/2
1
1
1
16XFC
MCLK/214
© 2006-2011 Microchip Technology Inc.
6.83
13.66
DS22011B-page 19
MCP3905A/05L/06A
NOTES:
DS22011B-page 20
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
5.0
APPLICATIONS INFORMATION
5.1
Meter Design using the
MCP3905A/05L/06A
For all applications information, refer to AN994, "IEC
Compliant Active Energy Meter Design Using The
MCP3905/6” (DS00994). This application note
includes all required energy meter design information,
including the following:
•
•
•
•
•
•
•
•
•
•
•
•
Meter rating and current sense choices
Shunt design
PGA selection
F2, F1, F0 selection
Meter calibration
Anti-aliasing filter design
Compensation for parasitic shunt inductance
EMC design
Power supply design
No-Load threshold
Start-up current
Accuracy Testing Results from MCP3905-based
meter
• EMC Testing Results from MCP3905-based meter
© 2006-2011 Microchip Technology Inc.
DS22011B-page 21
MCP3905A/05L/06A
NOTES:
DS22011B-page 22
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
24-Lead SSOP
Examples:
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
MCP3905A
e3
E/SS^^
1120256
MCP3905L
e3
E/SS^^
1120256
MCP3906A
e3
E/SS^^
1120256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006-2011 Microchip Technology Inc.
DS22011B-page 23
MCP3905A/05L/06A
/HDG3ODVWLF6KULQN6PDOO2XWOLQH 66 ±PP%RG\>6623@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D
N
E
E1
1 2
NOTE 1
b
e
c
φ
A2
A
A1
L
L1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI3LQV
0,//,0(7(56
0,1
1
120
0$;
3LWFK
H
2YHUDOO+HLJKW
$
±
%6&
±
0ROGHG3DFNDJH7KLFNQHVV
$
6WDQGRII
$
±
±
2YHUDOO:LGWK
(
0ROGHG3DFNDJH:LGWK
(
2YHUDOO/HQJWK
'
)RRW/HQJWK
/
)RRWSULQW
/
5()
/HDG7KLFNQHVV
F
±
)RRW$QJOH
ƒ
ƒ
ƒ
/HDG:LGWK
E
±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
DS22011B-page 24
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2006-2011 Microchip Technology Inc.
DS22011B-page 25
MCP3905A/05L/06A
NOTES:
DS22011B-page 26
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
APPENDIX A:
REVISION HISTORY
Revision B (July 2011)
The following is the list of modifications:
1.
2.
3.
4.
Added Extended Temperature item to the
Features list.
Updated Section 2.0, Typical Performance
Curves with new extended temperature
graphics (Figures 2-11 to 2-14).
Updated Section 6.0, Packaging Information to
show the Land Pattern drawings.
Updated the Product Identification System
section with the Extended Temperature
characteristic and examples.
Revision A (September 2006)
• Original Release of this Document.
© 2006-2011 Microchip Technology Inc.
DS22011B-page 27
MCP3905A/05L/06A
NOTES:
DS22011B-page 28
© 2006-2011 Microchip Technology Inc.
MCP3905A/05L/06A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XX
Device
Temperature
Range
Package
Device:
Temperature Range:
MCP3905A: Energy Metering IC
MCP3905AT: Energy Metering IC (Tape and Reel)
MCP3905L: Energy Metering IC
MCP3905LT: Energy Metering IC (Tape and Reel)
MCP3906A: Energy Metering IC
MCP3906AT: Energy Metering IC (Tape and Reel)
E
= -40°C to +125°C
I
= -40°C to +85°C
Examples:
a)
b)
c)
d)
a)
b)
Package:
SS = Plastic Shrink Small Outline (209 mil Body), 24-lead
c)
d)
a)
b)
c)
d)
© 2006-2011 Microchip Technology Inc.
MCP3905A-E/SS: Extended Temperature,
24LD SSOP.
MCP3905AT-E/SS: Tape and Reel,
Extended Temperature,
24LD SSOP.
MCP3905A-I/SS: Industrial Temperature,
24LD SSOP.
MCP3905AT-I/SS: Tape and Reel,
Industrial Temperature,
24LD SSOP
MCP3905L-E/SS:
Extended Temperature,
24LD SSOP.
MCP3905LT-E/SS: Tape and Reel,
Extended Temperature,
24LD SSOP.
MCP3905L-I/SS:
Industrial Temperature,
24LD SSOP.
MCP3905LT-I/SS: Tape and Reel,
Industrial Temperature,
24LD SSOP.
MCP3906A-E/SS: Extended Temperature,
24LD SSOP.
MCP3906AT-E/SS: Tape and Reel,
Extended Temperature,
24LD SSOP.
MCP3906A-I/SS: Industrial Temperature,
24LD SSOP.
MCP3906AT-I/SS: Tape and Reel,
Industrial Temperature,
24LD SSOP.
DS22011B-page 29
MCP3905A/05L/06A
NOTES:
DS22011B-page 30
© 2006-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-410-1
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2011 Microchip Technology Inc.
DS22011B-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS22011B-page 32
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
05/02/11
© 2006-2011 Microchip Technology Inc.
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