INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT32 Quad 2-input OR gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Quad 2-input OR gate 74HC/HCT32 FEATURES GENERAL DESCRIPTION • Output capability: standard The 74HC/HCT32 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • ICC category: SSI The 74HC/HCT32 provide the 2-input OR function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay nA, nB to nY CL = 15 pF; VCC = 5 V CI input capacitance CPD power dissipation capacitance per gate notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 HCT 6 9 ns 3.5 3.5 pF 16 28 pF Philips Semiconductors Product specification Quad 2-input OR gate 74HC/HCT32 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 4, 9, 12 1A to 4A data inputs 2, 5, 10, 13 1B to 4B data inputs 3, 6, 8, 11 1Y to 4Y data outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Quad 2-input OR gate 74HC/HCT32 FUNCTION TABLE INPUTS OUTPUT nA nB nY L L H H L H L H L H H H Notes 1. H = HIGH voltage level L = LOW voltage level Fig.4 Functional diagram. Fig.5 Logic diagram 74HC (one gate). December 1990 Fig.6 Logic diagram 74HCT (one gate). 4 Philips Semiconductors Product specification Quad 2-input OR gate 74HC/HCT32 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 −40 to +125 min. min. WAVEFORMS typ. max. tPHL/ tPLH propagation delay nA, nB to nY 22 8 6 90 18 15 115 23 20 135 27 23 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 output transition time max. UNIT V CC (V) max. DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nA, nB 1.20 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 −40 to +125 min. min. VCC WAVEFORMS (V) typ. max. tPHL/ tPLH propagation delay nA, nB to nY 11 24 30 36 ns 4.5 Fig.7 tTHL/ tTLH 7 15 19 22 ns 4.5 Fig.7 output transition time December 1990 5 max. UNIT max. Philips Semiconductors Product specification Quad 2-input OR gate 74HC/HCT32 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 6