INTEGRATED CIRCUITS DATA SHEET 74AHC259; 74AHCT259 8-bit addressable latch Product specification File under Integrated Circuits, IC06 2000 Mar 14 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. • Balanced propagation delays The 74AHC/AHCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in digital systems. The ‘259’ are multifunctional devices capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. • All inputs have Schmitt-trigger actions • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Output from each storage bit available • Random (addressable) data entry The ‘259’ also incorporates an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). • Easily expandable • Common reset input • Useful as a 3-to-8 active HIGH decoder The ‘259’ has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and from −40 to +125 °C. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the ‘259’ as an address latch, changing more than one bit of the address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the ‘259’. 2000 Mar 14 2 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC tPHL/tPLH propagation delay D to Qn CL = 15 pF; VCC = 5 V 4.1 4.1 ns An to Qn 5.3 5.5 ns LE to Qn 4.3 4.3 ns MR to Qn 3.9 3.9 ns 3.0 3.0 pF 4.0 4.0 pF 13 17 pF CI input capacitance CO output capacitance CPD power dissipation capacitance VI = VCC or GND CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 2000 Mar 14 AHCT 3 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch FUNCTION TABLE See note 1. INPUTS OUTPUTS OPERATING MODE reset demultiplexer (active HIGH 8-channel) decoder (when D = H) memory (do nothing) addressable latch MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X X L L L L L L L L d L L L Q=d L L L L L L L d H L L L Q=d L L L L L L d L H L L L Q=d L L L L L d H H L L L L Q=d L L L L d L L H L L L L Q=d L L L d H L H L L L L L Q=d L L d L H H L L L L L L Q=d L L H H L H L d H H H L L L L L L L Q=d X X X X q0 q1 q2 q3 q4 q5 q6 q7 d L L L Q=d q1 q2 q3 q4 q5 q6 q7 d H L L q0 Q=d q2 q3 q4 q5 q6 q7 d L H L q0 q1 Q=d q3 q4 q5 q6 q7 d H H L q0 q1 q2 Q=d q4 q5 q6 q7 d L L H q0 q1 q2 q3 Q=d q5 q6 q7 d H L H q0 q1 q2 q3 q4 Q=d q6 q7 d L H H q0 q1 q2 q3 q4 q5 Q=d q7 H H H H q0 q1 q2 q3 q4 q5 q6 Q=d Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. ORDERING INFORMATION PACKAGES TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +125 °C 16 SO plastic SOT109-1 74AHC259PW 16 TSSOP plastic SOT403-1 74AHCT259D 16 SO plastic SOT109-1 74AHCT259PW 16 TSSOP plastic SOT403-1 74AHC259D 2000 Mar 14 4 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch PINNING PIN SYMBOL DESCRIPTION 1, 2 and 3 A0, A1 and A2 address input 4, 5, 6, 7, 9, 10, 11 and 12 Q0 to Q7 latch outputs 8 GND ground (0 V) 13 D data input 14 LE latch enable input (active LOW) 15 MR conditional reset input (active LOW) 16 VCC DC supply voltage handbook, halfpage A0 1 16 VCC A1 2 15 MR A2 3 14 LE 14 handbook, halfpage LE Q0 13 D Q1 Q2 13 D Q0 4 259 Q1 5 Q2 6 Q3 12 Q7 1 11 Q6 2 Q3 7 10 Q5 GND 8 9 Q4 3 Q4 A1 Q5 A2 Q6 Q7 5 6 7 9 10 11 12 MR 15 MNA574 Fig.1 Pin configuration. 2000 Mar 14 A0 4 MNA573 Fig.2 Logic symbol. 5 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch 13 handbook, halfpage Z9 15 G8 14 G10 9,10D DX 0 1 handbook, halfpage 1 C10 8R 0 2 G 3 0 7 2 4 5 1 A0 Q1 5 2 A1 Q2 6 3 A2 Q3 7 Q4 9 1-of-8 DECODER 8 LATCHES 7 3 9 4 4 1 6 2 Q0 14 LE Q5 10 15 MR Q6 11 13 D Q7 12 10 5 11 MNA571 6 12 7 MNA572 Fig.3 IEC logic symbol. Fig.4 Functional diagram. OPERATING MODE SELECT TABLE LE MR MODE L H addressable latch H H memory L L active HIGH 8-channel demultiplexer H L reset Note 1. H = HIGH voltage level; L = LOW voltage level. 2000 Mar 14 6 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature see DC and AC characteristics per device −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C VCC = 3.3 ±0.3 V − − 100 − − − ns/V VCC = 5 ±0.5 V − − 20 − − 20 ns/V tr, tf input rise and fall ratios (∆t/∆f) LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current − −20 mA VI < −0.5 V; note 1 IOK DC output clamping diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 IO DC output sink current ICC DC VCC or GND current Tstg storage temperature PD power dissipation per package −0.5 V < VO < VCC + 0.5 V for temperature range: −40 to +125 °C; note 2 − ±20 mA − ±25 mA − ±75 mA −65 +150 °C − 500 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. 2000 Mar 14 7 mW Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch DC CHARACTERISTICS 74AHC family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − V 3.0 2.1 − − 2.1 − 2.1 − V 5.5 3.85 − − 3.85 − 3.85 − V 2.0 − − 0.5 − 0.5 − 0.5 V 3.0 − − 0.9 − 0.9 − 0.9 V 5.5 − − 1.65 − 1.65 − 1.65 V 2.0 1.9 2.0 − 1.9 − 1.9 − V 3.0 2.9 3.0 − 2.9 − 2.9 − V 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 V 3.0 − 0 0.1 − 0.1 − 0.1 V 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA LOW-level input voltage LOW-level output voltage VCC (V) MIN. HIGH-level input voltage HIGH-level output voltage −40 to +85 25 PARAMETER VI = VIH or VIL; IO = −50 µA II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 − 40 − 80 µA CI input capacitance − − 3 10 − 10 − 10 pF 2000 Mar 14 8 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch 74AHCT family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA VOL LOW-level output voltage II input leakage current VI = VIH or VIL 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 4.0 − 40 − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF 2000 Mar 14 − 9 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch AC CHARACTERISTICS Type 74AHC259 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. propagation delay see Figs 5 and 11 15 pF − D to Qn 5.8 11.5 1.0 13.5 1.0 15.0 ns propagation delay see Figs 6 and 11 An to Qn − 7.5 14.5 1.0 17.0 1.0 18.5 ns propagation delay see Figs 7 and 11 LE to Qn − 6.2 12.0 1.0 14.0 1.0 15.2 ns tPHL propagation delay see Figs 8 and 11 MR to Qn − 5.4 10.5 1.0 12.5 1.0 13.5 ns tPHL/tPLH propagation delay see Figs 5 and 11 50 pF − D to Qn 7.3 14.5 1.0 17.0 1.0 18.5 ns propagation delay see Figs 6 and 11 An to Qn − 9.1 18.0 1.0 21.0 1.0 23.0 ns propagation delay see Figs 7 and 11 LE to Qn − 7.7 15.5 1.0 17.5 1.0 19.0 ns tPHL propagation delay see Figs 8 and 11 MR to Qn − 7.0 13.5 1.0 15.5 1.0 17.0 ns tW LE pulse width HIGH or LOW see Figs 7 and 11 5.0 − − 5.0 − 5.0 − ns MR pulse width LOW see Figs 8 and 11 5.0 − − 5.0 − 5.0 − ns tsu set-up time D to LE, An to LE see Figs 9, 10 and 11 4.0 − − 4.0 − 4.0 − ns th hold time D to LE, see Figs 9 and 11 An to LE 1.0 − − 1.0 − 1.0 − ns VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH 2000 Mar 14 10 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. propagation delay see Figs 5 and 11 15 pF − D to Qn 4.1 7.5 1.0 9.0 1.0 10.0 ns propagation delay see Figs 6 and 11 An to Qn − 5.3 9.5 1.0 11.5 1.0 12.5 ns propagation delay see Figs 7 and 11 LE to Qn − 4.3 8.0 1.0 9.5 1.0 10.5 ns tPHL propagation delay see Figs 8 and 11 MR to Qn − 3.9 7.0 1.0 8.5 1.0 9.5 ns tPHL/tPLH propagation delay see Figs 5 and 11 50 pF − D to Qn 5.3 9.5 1.0 11.0 1.0 12.0 ns propagation delay see Figs 6 and 11 An to Qn − 6.5 11.5 1.0 13.5 1.0 15.0 ns propagation delay see Figs 7 and 11 LE to Qn − 5.5 10.0 1.0 11.5 1.0 12.5 ns tPHL propagation delay see Figs 8 and 11 MR to Qn − 5.1 9.0 1.0 10.5 1.0 11.5 ns tW LE pulse width HIGH or LOW see Figs 7 and 11 5.0 − − 5.0 − 5.0 − ns MR pulse width LOW see Figs 8 and 11 5.0 − − 5.0 − 5.0 − ns tsu set-up time D to LE, An to LE see Figs 9, 10 and 11 4.0 − − 4.0 − 4.0 − ns th hold time D to LE, see Figs 9 and 11 An to LE 1.0 − − 1.0 − 1.0 − ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 2000 Mar 14 11 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch Type 74AHCT259 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. propagation delay see Figs 5 and 11 15 pF − D to Qn 4.1 7.5 1.0 9.0 1.0 10.0 ns propagation delay see Figs 6 and 11 An to Qn − 5.5 9.5 1.0 11.5 1.0 12.5 ns propagation delay see Figs 7 and 11 LE to Qn − 4.3 8.0 1.0 9.5 1.0 10.4 ns tPHL propagation delay see Figs 8 and 11 MR to Qn − 3.9 7.0 1.0 8.5 1.0 9.5 ns tPHL/tPLH propagation delay see Figs 5 and 11 50 pF − D to Qn 5.4 9.5 1.0 11.0 1.0 12.0 ns propagation delay see Figs 6 and 11 An to Qn − 6.6 12.0 1.0 14.0 1.0 15.5 ns propagation delay see Figs 7 and 11 LE to Qn − 5.5 10.0 1.0 12.0 1.0 13.0 ns tPHL propagation delay see Figs 8 and 11 MR to Qn − 5.1 9.0 1.0 10.5 1.0 11.5 ns tW LE pulse width HIGH or LOW see Figs 7 and 11 5.0 − − 5.0 − 5.0 − ns MR pulse width LOW see Figs 8 and 11 5.0 − − 5.0 − 5.0 − ns VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH tsu set-up time see Figs 9, D to LE, An to LE 10 and 11 4.0 − − 4.0 − 4.0 − ns th hold time D to LE, see Figs 9 and 11 An to LE 1.0 − − 1.0 − 1.0 − ns Note 1. Typical values at VCC = 5.0 V. 2000 Mar 14 12 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch AC WAVEFORMS handbook, halfpageVCC handbook, halfpageVCC VM(1) D input GND GND t PHL t PHL t PLH VOH t PLH VOH VM(2) Qn output VOL MNA569 FAMILY VI INPUT REQUIREMENTS AHC GND to VCC AHCT GND to 3.0 V VM(2) Qn output VOL Fig.5 VM(1) An input VM(1) INPUT VM(2) OUTPUT MNA568 VM(1) INPUT VM(2) OUTPUT FAMILY VI INPUT REQUIREMENTS 50% VCC 50% VCC AHC GND to VCC 50% VCC 50% VCC 1.5 V AHCT GND to 3.0 V 1.5 V 50% VCC The data input (D) to output (Qn) propagation delays. Fig.6 50% VCC The address input (An) to output (Qn) propagation delays. VCC handbook, full pagewidth D input GND VCC VM(1) LE input GND tW t PHL t PLH VOH VM(2) Qn output VOL VM(1) INPUT MNA570 VM(2) OUTPUT FAMILY VI INPUT REQUIREMENTS AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.7 The enable input (LE) to output (Qn) propagation delays, the enable input pulse width. 2000 Mar 14 13 Philips Semiconductors Product specification 8-bit addressable latch 74AHC259; 74AHCT259 handbook, halfpage VCC VCC handbook, halfpage VM(1) MR input VM(1) An input GND ADDRESS STABLE GND tW t su t PHL th VCC VOH VM(1) LE input VM(2) Qn output VOL MNA550 GND MNA548 The shaded areas indicate when the input is permitted to change for predictable output performance. VM(1) INPUT VM(2) OUTPUT FAMILY VI INPUT REQUIREMENTS AHC GND to VCC 50% VCC 50% VCC AHC GND to VCC 50% VCC AHCT GND to 3.0 V 1.5 V AHCT GND to 3.0 V 1.5 V Fig.8 FAMILY 50% VCC The conditional reset input (MR) to output (Qn) propagation delays. Fig.9 VI INPUT REQUIREMENTS VM(1) INPUT The address set-up and hold time for An inputs to LE input. VCC handbook, full pagewidth VM(1) LE input GND t su t su th th VCC VM(1) D input GND VOH VM(2) Q=D Qn output VOL VM(1) INPUT Q=D MNA549 VM(2) OUTPUT FAMILY VI INPUT REQUIREMENTS AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.10 The data set-up and hold time for D input to LE input. 2000 Mar 14 14 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA219 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.11 Load circuitry for switching times. 2000 Mar 14 15 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.050 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 2000 Mar 14 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 16 o 8 0o Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 2000 Mar 14 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27 MO-153 17 o Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Mar 14 18 Philips Semiconductors Product specification 74AHC259; 74AHCT259 8-bit addressable latch Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Mar 14 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Mar 14 Document order number: 9397 750 06821