TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93PW32 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93PW32 Low Voltage/Low Power CMOS 16-bit Microcontrollers TMP93PW32F 1. Outline and Device Characteristics The TMP93PW32 is OTP type MCU which includes 128-Kbyte One-time PROM. Using the adapter-socket (BM11132), you can write and verify the data for the TMP93PW32. The TMP93PW32F has the same pin-assignment as TMP93CS32 (Mask ROM type). Writing the program to Built-in PROM, the TMP93PW32 operates as the same way as the TMP93CS32. The memory map and capacity of built in ROM and RAM are different between TMP93CS32 and TMP93PW32. The TMP93PW32 has the PROM of 128 Kbytes and the RAM of 4 Kbytes, and the TMP93CS32 has the ROM of 64 Kbytes and the RAM of 2 Kbytes. Following figure shows each memory map. 000000H 000080H 000000H Internal I/O (128 bytes) Internal I/O (128 bytes) 000080H Internal RAM (2 Kbytes) Internal RAM (4 Kbytes) 000880H 001080H External memory External memory FE0000H FF0000H Internal PROM (128 Kbytes) Internal ROM (64 Kbytes) FFFF00H FFFF00H Interrupt vector table (256 bytes) Interrupt vector table (256 bytes) FFFFFFH FFFFFFH TMP93PW32 memory map TMP93CS32 memory map Product No. ROM RAM Package Adapter Socket TMP93PW32F OTP 128 Kbytes 4 Kbytes P-QFP64-1414-0.80A BM11132 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 93PW32-1 2004-02-10 TMP93PW32 AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4, AN5 (P54, P55) AVCC AVSS VREFH VREFL VCC [1] VSS [2] 900/L CPU 10-bit 6-channel AD converter TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) Serial I/O (channel 0) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65) SERIAL I/O (channel 1) XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP OSC Clock controller CLK AM8/ AM16 32 bits SR X1 X2 EA RESET F ALE PC Interrupt controller INT0 (P35) NMI WAIT (P70) P71 Watchdog timer Port 7 4-Kbyte RAM 8-bit timer (Timer 0) Port 0 AD0 to AD7 (P00 to P07) Port 1 AD8 to AD15/A8 to A15 (P10 to P17) Port 2 A0 to A7/A16 to A23 (P20 to P27) 8-bit timer (Timer 1) 8-bit timer (Timer 2) TO3 (P41) 8-bit timer (Timer 3) Port 3 128-Kbyte PROM INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (Timer 4) RD (P30) WR (P31) HWR (P32) Wait controller (3-block) 16-bit timer (Timer 5) Note: The items in parentheses ( ) are the initial setting after reset. Figure 1.1 TMP93PW32 Block Diagram 93PW32-2 2004-02-10 TMP93PW32 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93PW32, their names and functions are described below. Pin Assignment 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TMP93PW32F QFP64 P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC RESET EA 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 (TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS CLK AM8/AM16 X1 X2 1 Top view NMI (TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54 47 48 P35 (INT0) P32 (HWR) P31(WR) P30 (RD) P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12) Figure 2.1.1 shows pin assignment of the TMP93PW32F. (AN5) P55 2.1 Figure 2.1.1 Pin Assignment (64-pin QFP) 93PW32-3 2004-02-10 TMP93PW32 2.2 Pin Names and Functions The TMP93PW32 has MCU mode and PROM mode. (1) Table 2.2.1 and Table 2.2.2 show pin function of TMP93PW32 in MCU mode. Table 2.2.1 Pin Names and Function (1/2) Pin Name Number of Pins P00 to P07 AD0 to AD7 8 P10 to P17 AD8 to AD15 A8 to A15 8 P30 RD P31 WR P32 HWR P35 INT0 P41 TO3 P42 TI4 Functions I/O 3 states I/O Port 1: I/O port that allows selection of I/O on a bit basis Address/Data (upper): Bits 8 to 15 for address/data bus I/O 8 1 1 1 1 Address: Bits 0 to 7 for address bus Address: Bits 16 to 23 for address bus Output Port 30: Output port Output Read: Strobe signal for reading external memory Output Port 31: Output port Output Write: Strobe signal for writing data on pins AD0 to AD7 I/O Output Input I/O Output P44 TO4 1 P45 TI6 INT6 1 P47 TO6 1 Port 42: I/O port Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 43: I/O port Input Timer input 5: Timer 4 count/capture trigger signal input Input Interrupt request pin 5: Interrupt request pin with rising edge I/O Output Port 44: I/O port Timer output 4: Timer 4 output pin Port 45: I/O port Input Timer input 6: Timer 5 count/capture trigger signal input Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge I/O P46 TI7 INT7 Port 41: I/O port PWM output 3: 8-bit PWM timer 3 output Input I/O 1 Port 35: I/O port Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Timer input 4: Timer 4 count/capture trigger signal input I/O 1 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Input INT4 P43 TI5 INT5 Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Output I/O 1 Address: Bits 8 to 15 for address bus Output I/O 1 Port 0: I/O port that allows selection of I/O on a bit basis Address/Data (lower): Bits 0 to 7 for address/data bus 3 states Output P20 to P27 A0 to A7 A16 to A23 I/O Port 46: I/O port Input Timer input 7: Timer 5 count/capture trigger signal input Input Interrupt request pin 7: Interrupt request pin with rising edge I/O Output Port 47: I/O port Timer output 6: Timer 5 output pin 93PW32-4 2004-02-10 TMP93PW32 Table 2.2.2 Pin Names and Function (2/2) Pin Name P50 to P52, P54, P55 AN0 to AN2, AN4, AN5 P53 AN3 Number of Pins I/O Functions Input Port 50 to Port 52, Port 54, Port 55: Input port Input Analog input: Analog signal input for AD converter 5 1 ADTRG Input Port 53: Input Port Input Analog input: Analog signal input for AD converter Input P60 TXD0 1 P61 RXD0 1 P62 SCLK0 I/O Output I/O Input I/O 1 CTS0 I/O Input P63 TXD1 1 P64 RXD1 1 P65 SCLK1 I/O Output I/O Input I/O 1 CTS1 I/O Input I/O P70 1 WAIT P71 1 Input I/O Input NMI 1 CLK Output 1 1 EA AM8/ AM16 1 Serial send data 0 Port 61: I/O port (with pull-up resistor) Serial receive data 0 Port 62: I/O port (with pull-up resistor) Serial clock I/O 0 Serial data send enable 0 (clear to send) Port 63: I/O port (with pull-up resistor) Serial send data 1 Port 64: I/O port (with pull-up resistor) Serial receive data 1 Port 65: I/O port (with pull-up resistor) Serial clock I/O 1 Serial data send enable 1 (clear to send) Port 70: I/O port (High current output available) Wait: Pin used to request CPU bus wait (It is active in (1 + N) waits mode. Set by the bus-width/wait control register.) Port 71: I/O port (High current output available) Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. Clock output: Outputs “fSYS ÷ 2” Clock. Pulled-up during reset. Can be disabled for reducing noise. Input “1” should be inputted with TMP93PW32. Input Address mode: Selects external data bus width. “1” should be inputted. The data bus width for external access is set by chip select/wait control register and Port 1 control register. 1 ALE AD converter external start trigger input Port 60: I/O port (with pull-up resistor) Output Address Latch Enable Can be disabled for reducing noise. RESET 1 Input Reset: Initializes TMP93PW32. (with pull-up resistor) VREFH 1 Input Pin for high level reference voltage input to AD converter VREFL 1 Input Pin for low level reference voltage input to AD converter AVCC 1 Input Power supply pin for AD converter AVSS 1 Input GND pin for AD converter (0 V) X1 1 Input Oscillator connecting pin X2 1 Output Oscillator connecting pin VCC 1 Input Power supply pin VSS 2 Input GND pin (All VSS pins are connected to the GND (0 V).) Note: Built-in pull-up resistors can be released from the pins other than the RESET pin by software. 93PW32-5 2004-02-10 TMP93PW32 (2) PROM mode Table 2.2.3 shows pin function of the TMP93PW32 in PROM mode. Table 2.2.3 Pin Name and Function of PROM Mode Pin Function Number of Pins Input/ Output Function Pin Name (MCU Mode) A7 to A0 8 Input A15 to A8 8 Input A16 1 Input D7 to D0 8 I/O Memory data of program P07 to P00 CE 1 Input Chip enable P32 OE 1 Input Output control P30 PGM 1 Input Program control P31 VPP 1 Power supply 12.75 V/5 V (Power supply of program) EA VCC 2 Power supply 6.25 V/5 V VCC, AVCC VSS 3 Power supply 0V VSS, AVSS Number of Pins Input/ Output Pin Function P60 1 Input RESET 1 Input CLK 1 Input ALE 1 Output X1 1 Input X2 1 Output P65 to P61 AM8/ AM16 6 Input 18 I/O P35 P47 to P41 P55 to P50 P70 VREFH VREFL P27 to P20 Memory address of program P17 to P10 P71 Disposal of Pin Fix to low level (security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level Open NMI 93PW32-6 2004-02-10 TMP93PW32 3. Operation This section describes the functions and basic operational blocks of the TMP93PW32. The TMP93PW32 has PROM in place of the mask ROM which is included in the TMP93CS32. The other configuration and functions are the same as the TMP93CS32. Regarding the functions of the TMP93PW32 (Not described), see the part of TMP93CS32. The TMP93PW32 has two operational modes: MCU mode and PROM mode. 3.1 MCU Mode (1) Mode-setting and function The MCU mode is set by opening the CLK pin (Pin open). In the MCU mode, the operation is same as TMP93CS32 except the followings. (2) Memory map The memory map of TMP93PW32 is not same as that of TMP93CS32. Figure 3.1.1 shows the memory map in MCU mode. Figure 3.1.2 show that in PROM mode. 000000H 00000H Internal I/O (128 bytes) 000080H Internal RAM (4 Kbytes) 001080H Internal PROM (128 Kbytes) External memory FE0000H Internal PROM (128 Kbytes) 1FFFFH Interrpt vector table (256 bytes) ( FFFF00H = Internal area) FFFFFFH Figure 3.1.1 Memory Map in MCU Mode Figure 3.1.2 Memory Map in PROM Mode 93PW32-7 2004-02-10 TMP93PW32 (3) Care point of bus width/wait controller The built in RAM capacity of the TMP93PW32 is larger than that of the TMP93CS32, therefore the following point is different about the accessing area of WAITC1. Setting WAITC1<B1C1:0> to “00” TMP93PW32 TMP93CS32 1080H to 7FFFH 880 to 7FFFH WAITC0 and WAITC2 addressing area are the same as TMP93CS32. 93PW32-8 2004-02-10 TMP93PW32 3.2 PROM Mode (1) Mode setting and function PROM mode is set by setting the RESET and CLK pins to the “L” level. The programming and verification for the internal PROM is achieved by using a general EPROM programmer with the adaptor socket. 1. Preparation of OTP adaptor BM11132: for TMP93PW32 2. Setting of OTP adaptor The switch (SW1) is set to N side. 3. Setting of PROM writer i) Set PROM type to TC 571000D. Size: 1 Mbits (128 K × 8 bits) VPP: 12.75 V tPW: 100 µs Electric signature mode: none ii) Data transmittion In TMP93PW32F, PROM is placed on addresses 00000 to 1FFFFH in PROM mode, and addresses FE0000H to FFFFFFH in MCU mode. Therefore data should be transferred to addresses 00000 to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode. (See instruction manual of PROM programmer.) iii) Setting of the program address Start address: 00000H End address: 1FFFFH 4. Programming Program and verify according to operating process of PROM programmer. 93PW32-9 2004-02-10 TMP93PW32 Figure 3.2.1 shows the setting of the pins in PROM mode. VPP (12.75 V/5 V) VCC AVCC, VCC EA P30 P32 P31 P71 P17 to P10 P27 to P20 A16 to A0 P07 to P00 OE CE PGM D7 to D0 RESET CLK VCC X1 P65 to P61 AM8/ AM16 X2 VSS AVSS P60 SECURITY For other pins, refer to the section on pin functions (Table 2.2.2 ). * Use the 10 MHz resonator in case of programming and verification by a general PROM programmer. Figure 3.2.1 PROM Mode Pin Setting (2) Caution for electric signature The TMP93PW32 dose not support the electric signature mode (hereinafter referred to as “signature”). If PROM programmer used the signature, the device would be damaged because of applying voltage of 12 ± 0.5 V to pin 9 (A9) of the address. Please use without setting the signature. (3) Program mode All bits of the TMP93PW32 are “1” when delivered (the erase state). Data “0” is written in the necessary bit location during program operating. Writing function can be operated at VPP = 12.5 V, OE = VIH, CE = VIL. Built-in one time PROM can be written in any sequence. It is possible to write only special address. (4) Adopter socket (BM11132) BM11132 is the adapter sockets to write data into the TMP93PW32F. The TMP93PW32F has built-in one time PROM using a general EPROM programmer. (5) Program storing area of PROM mode The TMP93PW32 has the program space (FE0000H to FFFFFFH) of 128 Kbytes. The address 00000H to 1FFFFH of PROM mode equals to the address FE0000H to FFFFFFH of MCU mode. 93PW32-10 2004-02-10 TMP93PW32 (6) Program write setting method using a general PROM programmer PROM to be prepared should equal to TC571000D functions. 1. Set the switch (SW1) of BM11132 (hereinafter referred to as “adapter”) to the program side (NOR) (Note 1). 2. Connect MCU to the adapter (Note 2). 3. Connect the adapter to PROM programmer (Note 2). 4. Set the PROM type of PROM programmer to TC571000D. 5. Set the start address for writing PROM to 00000H, and the end address to 1FFFFH (Note 3). 6. Writing to built-in one time PROM and verifying should be operated according to the operation procedures of PROM programmer. Note 1: If data is written to built-in one time PROM without setting the switch (SW1) to the program side, the device would be damaged. Note 2: Please set with the first pin of the adapter and that of PROM programmer socket matched. If the first pin is conversely set, MCU or programmer would be damaged. Note 3: If data “0” is written to the address which is over 1FFFFH, the contents of the original program would be damaged because of writing “0” to the addresses 00000H to 1FFFFH. (7) Programming flow chart The programming mode is set by applying 12.75 V (Programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : “L” level, CLK: “L” level). While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “L” level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address. (25 times maximum) Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.2.2 shows the programming flow chart. 93PW32-11 2004-02-10 TMP93PW32 Start VCC = 6.25 V ± 0.25 V VPP = 12.75 V ± 0.25 V Address = Start address X=0 Program 0.1 ms pulse X=X+1 X > 25? Yes No Error Address = Address + 1 Verify OK No Last address? Yes VCC = 5 V VPP = 5 V Read all data Error OK Pass Failure Figure 3.2.2 Flow Chart (High-speed program writing) 93PW32-12 2004-02-10 TMP93PW32 (8) Security bit The TMP93PW32 has a security bit in PROM cell. If the security bit is programmed to “0”, the content of the PROM is disable to be read (FFH data) in PROM mode. (How to program the security bit.) The difference from the programming procedures described in section 3.2 (1) are follows. 1. Setting OTP adaptor Set the switch (SW1) to S side. 2. Setting PROM programmer i) Transferring the data ii) Setting of programming address The security bit is in bit0 of address 00000H. Set the start address 00000H and the end address 00000H. Set the data FEH at the address 00000H. 93PW32-13 2004-02-10 TMP93PW32 4. Electrical Characteristics 4.1 Absolute Maximum Ratings (TMP93PW32) Parameter Symbol Power supply voltage Rating VIN Except EA pin −0.5 to VCC + 0.5 V −0.5 to 14.0 EA pin Output current (per 1 pin) P7 IOL1 Output current (per 1 pin) except P7 IOL2 2 Output current (total) Σ IOL 120 Output current (total) Σ IOH −80 Power dissipation (Ta = 85°C) PD 350 Soldering temperature (10 s) TSOLDER 260 20 Storage temperature TSTG −65 to 150 Operating temperature TOPR −40 to 85 Note: Unit −0.5 to 6.5 VCC Input voltage 4.2 “X” used in an expression shows a cycle of clock fFPH. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value as an example is gear = 1/fc (SYSCR1<GEAR2:0> = “000”). mA mW °C The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. DC Characteristics Ta = −40 to 85°C Parameter Input high voltage Input low voltage Power supply voltage AVCC = VCC AVSS = VSS = 0 V Symbol VCC AD0 to AD15 VIL Port 2 to 7 (except P35) VIL1 RESET , NMI , INT0 VIL2 EA , AM8/ AM16 VIL3 X1 VIL4 Condition Min fc = 4 to 20 MHz 4.5 fc = 4 to 12.5 MHz 2.7 Max VCC ≥ 4.5 V 0.8 0.6 −0.3 VCC = 2.7 to 5.5 V 0.3 VCC 0.25 VCC 0.3 0.2 VCC VCC ≥ 4.5 V VCC < 4.5 V V 2.2 VIH Port 2 to 7 (except P35) VIH1 0.7 VCC RESET , NMI , INT0 VIH2 0.75 VCC EA , AM8/ AM16 VIH3 X1 VIH4 VCC = 2.7 to 5.5 V Unit 5.5 VCC < 4.5 V AD0 to AD15 2.0 VCC + 0.3 VCC − 0.3 0.8 VCC Output low voltage VOL IOL = 1.6 mA (VCC = 2.7 to 5.5 V) Output low current (P7) IOL7 VOL = 1.0 V VOH1 IOH = −400 µA (VCC = 3 V ± 10%) 2.4 VOH2 IOH = −400 µA (VCC = 5 V ± 10%) 4.2 Output high voltage Typ. (Note) 0.45 (VCC = 5 V ± 10%) 16 (VCC = 3 V ± 10%) 7 mA V Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. 93PW32-14 2004-02-10 TMP93PW32 Parameter Symbol Condition VEXT = 1.5 V REXT = 1.1 kΩ (VCC = 5 V ± 10% only) Min Typ. (Note1) Max Unit −3.5 mA Darlington drive current (8 output pins max) IDAR (Note2) Input leakage current ILI 0.0 ≤ VIN ≤ VCC 0.02 ±5 Output leakage current ILO 0.2 ≤ VIN ≤ VCC − 0.2 0.05 ±10 Power down voltage (at STOP, RAM back up) VSTOP VIL2 = 0.2 VCC, VIH2 = 0.8 VCC 2.0 6.0 VCC = 5.5 V 45 130 VCC = 4.5 V 50 160 VCC = 3.3 V 70 280 VCC = 2.7 V 90 400 RESET pull-up resistor RRST Pin capacitance CIO Schmitt width RESET , NMI , INT0 VTH Programmable pull-up resistor RKH −1.0 fc = 1 MHz 10 0.4 45 130 VCC = 4.5 V 50 160 VCC = 3.3 V 70 280 VCC = 2.7 V 90 VCC = 5 V ± 10% fc = 20 MHz IDLE2 30 22 27 13 17 3.4 5 NORMAL (Note 3) 8.0 11 7.0 10 RUN ICC IDLE2 IDLE1 Ta ≤ 50°C Ta ≤ 70°C STOP Ta ≤ 85°C VCC = 2.7 V to 5.5 V kΩ pF kΩ 400 25 IDLE1 VCC = 3 V ± 10% fc = 12.5 MHz (Typ.: VCC = 3.0 V) V V VCC = 5.5 V NORMAL (Note 3) RUN 1.0 µA 4.2 6 1.2 1.8 mA 10 0.2 20 µA 50 Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: ICC measurement conditions (NORMAL): Only CPU is operational; output pins are open and input pins are fixed. (Reference) Definition of IDAR REXT IDAR VEXT 93PW32-15 2004-02-10 TMP93PW32 4.3 AC Electrical Characteristics (1) VCC = 5 V ± 10% No. Parameter Symbol Variable Min Max 31250 16 MHz Min Max 20 MHz Min Max Unit 1 Osc. period (= x) tOSC 50 62.5 50 ns 2 CLK pulse width tCLK 2x − 40 85 60 ns 3 A0 to A23 valid → CLK hold tAK 0.5x − 20 11 5 ns 4 CLK valid → A0 to A23 hold tKA 1.5x − 70 24 5 ns 5 A0 to A15 valid → ALE fall tAL 0.5x − 15 16 10 ns 6 ALE fall → A0 to A15 hold tLA 0.5x − 20 11 5 ns 7 ALE high pulse width tLL x − 40 23 10 ns 8 ALE fall → RD / WR fall tLC 0.5x − 25 6 0 ns 9 RD / WR rise → ALE rise tCL 0.5x − 20 11 5 ns 10 A0 to A15 valid → RD / WR fall tACL x − 25 38 25 ns 11 A0 to A23 valid → RD / WR fall tACH 1.5x − 50 44 25 ns 12 RD / WR rise → A0 to A23 hold tCA 0.5x − 25 6 0 13 A0 to A15 valid → D0 to D15 input tADL 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width tRR 2.0x − 40 85 60 17 RD rise → D0 to D15 hold tHR 0 0 0 ns 18 RD rise → A0 to A15output tRAE 48 35 ns 19 tWW 2.0x − 40 85 60 ns tDW 2.0x − 55 70 45 ns tWD 0.5x − 15 WR low pulse width 20 D0 to D15 valid → WR rise 21 WR rise → D0 to D15 hold 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold (1 + n) WAIT mode (1 + n) WAIT mode (1 + n) WAIT mode 133 95 ns tADH 3.5x − 65 154 110 ns tRD 2.0x − 60 65 40 ns 26 A0 to A23 valid → Port hold tAPH2 tCP 16 3.5x − 90 2.0x + 0 108 125 2.5x − 120 2.5x + 50 ns 85 ns 70 ns 5 ns 200 ns 100 ns 36 206 200 ns 10 129 3.0x − 80 tAWL tCW tAPH WR rise → Port valid x − 15 tAWH 25 A0 to A23 valid → Port input 27 ns 3.0x − 55 175 200 ns AC measuring conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (Except for AD0 to AD15) 93PW32-16 2004-02-10 TMP93PW32 (2) VCC = 3 V ± 10% No. Parameter Symbol Variable Min Max 31250 1 Osc. period (= x) tOSC 80 2 CLK pulse width tCLK 2x − 40 3 A0 to A23 valid → CLK hold tAK 4 CLK valid → A0 to A23 hold 5 A0 to A15 valid → ALE fall 12.5 MHz Min Max 80 Unit ns 120 ns 0.5x − 30 10 ns tKA 1.5x − 80 40 ns tAL 0.5x − 35 5 ns 6 ALE fall → A0 to A15 hold tLA 0.5x − 35 5 ns 7 ALE high pulse width tLL x − 60 20 ns 8 ALE fall → RD / WR fall tLC 0.5x − 35 5 ns 9 RD / WR rise → ALE rise tCL 0.5x − 40 0 ns x − 50 30 ns ns 10 A0 to A15 valid → RD / WR fall tACL 11 A0 to A23 valid → RD / WR fall tACH 1.5x − 50 70 12 RD / WR rise → A0 to A23 hold tCA 0.5x − 40 0 13 A0 to A15 valid → D0 to D15 input tADL ns 3.0x − 110 130 ns 14 A0 to A23 valid → D0 to D15 input tADH 3.5x − 125 155 ns 15 RD fall → D0 to D15 input tRD 2.0x − 115 45 ns 16 RD low pulse width tRR 2.0x − 40 17 RD rise → D0 to D15 hold tHR 0 0 ns 18 RD rise → A0 to A15 output tRAE x − 25 55 ns 19 tWW 2.0x − 40 120 ns tDW 2.0x − 120 40 ns tWD 0.5x − 40 0 WR low pulse width 20 D0 to D15 Valid → WR rise 21 WR rise → D0 to D15 hold 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold (1 + n) WAIT mode (1 + n) WAIT mode (1 + n) WAIT mode tAPH 26 A0 to A23 valid → Port hold tAPH2 WR rise → Port valid 3.0x − 100 tAWL 25 A0 to A23 valid → Port input 27 3.5x − 130 tAWH tCW 120 2.0x + 0 ns 150 ns 140 ns 5 ns 200 ns 160 2.5x − 195 2.5x + 50 tCP ns ns 250 200 ns AC measuring conditions • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF • Input level: High 0.9 × VCC/Low 0.1 × VCC 93PW32-17 2004-02-10 TMP93PW32 (3) Read cycle tOSC X1 tCLK CLK tAK tKA A0 to A23 tAWH tCW tAWL WAIT tAPH tAPH2 Port input (Note) tADH RD tACH tACL AD0 to AD15 tCA tRD tLC A0 to A15 tAL tRR tLA tADL tRAE tHR D0 to D15 tCL ALE tLL Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW32-18 2004-02-10 TMP93PW32 (4) Write cycle X1 CLK A0 to A23 WAIT Port output (Note) tWW tCP WR , HWR tDW AD0 to AD15 A0 to A15 tWD D0 to D15 ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW32-19 2004-02-10 TMP93PW32 4.4 Serial Channel Timing (1) I/O interface mode a. SCLK input mode Parameter Variable Symbol Min 12.5 MHz Max Min Max 20 MHz Min Max Unit SCLK cycle tSCY 16x 1.28 µs 0.8 µs ns Output data → Rising/falling edge of SCLK tOSS tSCY/2 − 5x − 50 190 100 ns SCLK rising/falling edge → Output data hold tOHS 5x − 100 300 150 ns SCLK rising/falling edge → Input data hold tHSR 0 0 0 SCLK rising/falling edge → Effective data input tSRD tSCY − 5x − 100 780 ns 450 ns Note: SCLK rising/falling timing ; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. b. SCLK output mode Parameter Variable Symbol 12.5 MHz Min Max 8192x Min Max 20 MHz Min Max 0.8 µs 409.6 µs Unit SCLK cycle (programmable) tSCY 16x Output data → SCLK rising edge tOSS tSCY − 2x − 150 970 550 ns SCLK rising edge → Output data hold tOHS 2x − 80 80 20 ns SCLK rising edge → Input data hold tHSR 0 0 0 SCLK rising edge → Effective data input tSRD 1.28 µs 655.36 µs tSCY − 2x − 150 SCLK Output mode /Input rising edge mode 970 ns ns 550 ns tSCY SCLK (Input falling edge mode) tOSS Output data TXD tOHS 0 1 2 tSRD Input data RXD 0 Valid 3 tHSR 1 Valid 2 Valid 3 Valid (2) UART mode (SCLK0 and SCLK1 are external input) Parameter Symbol Variable Min 12.5 MHz Max Min Max 20 MHz Min Max Unit SCLK cycle tSCY 4x + 20 340 220 ns SCLK low level pulse width tSCYL 2x + 5 165 105 ns SCLK high level pulse width tSCYH 2x + 5 165 105 ns 93PW32-20 2004-02-10 TMP93PW32 4.5 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Analog reference voltage (+) Analog reference voltage (−) Analog input voltage range Analog current for analog reference voltage <VREFON> = 1 <VREFON> = 0 Error (except quantization errors) Symbol VREFH VREFL Power Supply Min Typ. Max VCC VCC = 5 V ± 10% VCC − 1.5 VCC VCC = 3 V ± 10% VCC − 0.2 VCC VCC VCC = 5 V ± 10% VSS VSS VSS + 0.2 VCC = 3 V ± 10% VSS VSS VSS + 0.2 VAIN VREFL IREF (VREFL = 0 V) − Unit V VREFH VCC = 5 V ± 10% 0.5 1.5 VCC = 3 V ± 10% 0.3 0.9 VCC = 2.7 to 5.5 V 0.02 5.0 VCC = 5 V ± 10% ±1.0 ±3.0 VCC = 3 V ± 10% ±1.0 ±5.0 mA µA LSB Note 1: 1LSB = (VREFH − VREFL)/210 [V] Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.6 Event Counter Input Clock (External Input Clock: TI4, TI5, TI6, TI7) Parameter Variable Symbol Min 12.5 MHz Max Min Max 20 MHz Min Max Unit Clock cycle tVCK 8X + 100 740 500 ns Low level clock pulse width tVCKL 4X + 40 360 240 ns High level clock pulse width tVCKH 4X + 40 360 240 ns 4.7 Interrupt and Capture Operation (1) NMI and INT0 Interrupts Parameter Symbol Variable Min 12.5 MHz Max Min Max 20 MHz Min Max Unit NMI , INT0 low level pulse width tINTAL 4X 320 200 ns NMI , INT0 high level pulse width tINTAH 4X 320 200 ns (2) INT4 to INT7 Interrupts and Capture Parameter Symbol Variable Min 12.5 MHz Max Min Max 20 MHz Min Max Unit INT4 to INT7 low level pulse width tINTBL 4X + 100 420 300 ns INT4 to INT7 high level pulse width tINTBH 4X + 100 420 300 ns 93PW32-21 2004-02-10 TMP93PW32 4.8 Read Operation in PROM Mode DC/AC characteristics Ta = 25 ± 5°C, VCC = 5 V ± 10% Parameter Symbol Condition Min Max VPP − 4.5 5.5 Input high voltage (A0 to A16, CE , OE , PGM ) VIH1 − 2.2 VCC + 0.3 Input low voltage (A0 to A16, CE , OE , PGM ) VIL1 − −0.3 0.8 Address to output delay tACC CL = 50 pF − VPP read voltage 2.25 TCYC + α Unit V ns TCYC = 400 ns (10 MHz Clock) α = 200 ns A0 to A16 CE OE PGM D0 to D7 tACC Data output 93PW32-22 2004-02-10 TMP93PW32 4.9 Program operation in PROM Mode DC/AC characteristics Ta = 25 ± 5°C, VCC = 6.25 V ± 0.25 V Parameter Symbol Condition Min Typ. Max 12.75 13.00 Programming supply voltage VPP − 12.50 Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VIH − 2.6 VCC + 0.3 Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VIL − −0.3 0.8 VCC supply current ICC fc = 10 MHz − 50 VPP supply current IPP VPP = 13.00 V − 50 PGM program pulse width tPW CL = 50 pF 0.095 0.1 Unit V mA 0.105 ms A0 to A16 CE OE D0 to D7 Unknown Data-in stable Output data valid tPW PGM VPP Note 1: The power supply of VPP (12.75 V) must be set power on at the same time or the later time for a power supply of VCC and must be clear power on at the same time or early time for a power supply of VCC. Note 2: The pulling up/down device on condition of VPP = 12.75 V suffer a damage for the device. Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the program writing. 93PW32-23 2004-02-10 TMP93PW32 5. Package Dimensions P-QFP64-1414-0.80A Unit: mm 93PW32-24 2004-02-10