OKI MSM7507-03 Single rail codec Datasheet

E2U0019-28-81
¡ Semiconductor
MSM7507-01/02/03
¡ Semiconductor
This version:
Aug. 1998
MSM7507-01/02/03
Previous version: Nov. 1996
Single Rail CODEC
GENERAL DESCRIPTION
The MSM7507 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals, digital wireless systems, and digital PBX systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type and can drive a 600 W load, can directly
drive a handset receiver.
FEATURES
• Single power supply: +5 V ±5%
• Low power consumption
Operating mode:
20 mW Typ. 40 mW Max. VDD = 5 V
Power down mode:
0.03 mW Typ. 0.3 mW Max. VDD = 5 V
• ITU-T Companding law
MSM7507-01: m/A-law pin selectable
MSM7507-02: m-law
MSM7507-03: A-law
• Transmission characteristics conforms to ITU-T G.714
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Analog output can directly drive a 600 W line transformer
• The 24-Pin SOP package products provide pin compatibility with the MSM7543/7544
• The 20-Pin SSOP package products have 1/3 the foot print of conventional products
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7507-01GS-K)
(Product name : MSM7507-02GS-K)
(Product name : MSM7507-03GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7507-01MS-K)
(Product name : MSM7507-02MS-K)
(Product name : MSM7507-03MS-K)
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MSM7507-01/02/03
BLOCK DIAGRAM
AIN–
AIN+
–
+
RC
LPF
8th
BPF
PCMOUT
AD
CONV.
TCONT
AUTO
ZERO
PLL
GSX
BCLK
SGC
SG
VFRO
XSYNC
SG
GEN
–
+
SG
PWI
AOUT–
–
+
SG
AOUT+
–
+
SG
VR
GEN
5th
LPF
RTIM
DA
CONV.
RCONT
PWD
PWD
Logic
RSYNC
(ALAW)
PCMIN
PDN
VDD
AG
DG
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MSM7507-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG 1
24 SGC
SG 1
20 SGC
AOUT+ 2
23 AIN+
AOUT+ 2
19 AIN+
AOUT– 3
22 AIN–
AOUT– 3
18 AIN–
NC 4
21 GSX
PWI 4
17 GSX
PWI 5
20 NC
VFRO 5
16 NC
VFRO 6
19 NC
VDD 6
15 (ALAW)*
18 (ALAW)*
DG 7
14 AG
NC 7
VDD 8
17 NC
PDN 8
DG 9
16 AG
RSYNC 9
12 XSYNC
15 BCLK
PCMIN 10
11 PCMOUT
PDN 10
RSYNC 11
14 XSYNC
PCMIN 12
13 PCMOUT
13 BCLK
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7507-01GS-K/MSM7507-01MS-K.
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MSM7507-01/02/03
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
C1
R2
Analog input
R1
GSX
AIN–
AIN+
SG
–
+
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
Gain = R2/R1 £ 10
2) Non inverting input type
C2
AIN+
AIN–
GSX
Analog input
R5
R4
R3
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
Gain = 1 + R4 / R3 £ 10
AG
Analog signal ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.4 VPP above and below the signal ground voltage (SG)
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
When adding the frequency characteristics to the receive signal, refer to the application example.
During power saving or power down mode, the output of VFRO is at the voltage level of SG.
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MSM7507-01/02/03
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drive of an impedance of 1.2
kW, these outputs can directly be connected to a receiver of handset using a piezoelectric
earphone. Refer to the application example.
VI
VFRO
Receive Filter
PWI
SG
–
+
SG
–
+
R6
R6 > 20 kW
ZL ≥ 1.2 kW
R7
Gain = VO/VI = 2 ¥ R7/R6 £ 2
AOUT–
VO
ZL
AOUT+
During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.
The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The
output load resistor has a minimum value of 0.6 kW.
If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less
than that described above. For more details, refer to SINGLE POWER SUPPLY PCM CODEC
APPLICATION NOTE.
VDD
Power supply for +5 V.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
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MSM7507-01/02/03
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
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DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7507-03 (A-law) outputs the character signal, inverting the even bits.
Input/Output Level
PCMIN/PCMOUT
MSM7507-02 (m-law)
MSD
MSM7507-03 (A-law)
MSD
+Full scale
1 0 0 0
0 0 0 0
1 0 1 0
1 0 1 0
+0
1 1 1 1
1 1 1 1
1 1 0 1
0 1 0 1
–0
0 1 1 1
1 1 1 1
0 1 0 1
0 1 0 1
–Full scale
0 0 0 0
0 0 0 0
0 0 1 0
1 0 1 0
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SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±300 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down modes.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
ALAW
Control signal input of the companding law selection.
Provides only for the MSM7507-01GS-K/7507-01MS-K. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at
a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally
pulled down.
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MSM7507-01/02/03
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
Analog Input Voltage
VAIN
—
0 to 7
V
—
–0.3 to VDD + 0.3
V
Digital Input Voltage
Storage Temperature
VDIN
—
–0.3 to VDD + 0.3
V
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power Supply Voltage
VDD
Operating Temperature
Ta
Condition
Voltage must be fixed
—
Min.
Typ.
Max.
Unit
4.75
5.0
5.25
V
–30
+25
+85
°C
—
2.4
VPP
Analog Input Voltage
VAIN
Connect AIN– and GSX
—
Input High Voltage
VIH
XSYNC, RSYNC, BCLK,
2.2
—
VDD
V
Input Low Voltage
VIL
PCMIN, PDN, ALAW
0
—
0.8
V
Clock Frequency
FC
BCLK
Sync Pulse Frequency
FS
XSYNC, RSYNC
6.0
8.0
Clock Duty Ratio
DC
BCLK
40
50
60
%
Digital Input Rise Time
tIr
XSYNC, RSYNC, BCLK,
—
—
50
ns
64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
kHz
1536, 1544, 200
Digital Input Fall Time
Transmit Sync Pulse Setting Time
9.0
kHz
tIf
PCMIN, PDN, ALAW
—
—
50
ns
tXS
BCLKÆXSYNC, See Timing Diagram
100
—
—
ns
tSX
XSYNCÆBCLK, See Timing Diagram
100
—
—
ns
tRS
BCLKÆRSYNC, See Timing Diagram
100
—
—
ns
tSR
RSYNCÆBCLK, See Timing Diagram
100
—
—
ns
Sync Pulse Width
tWS
XSYNC, RSYNC
1 BCLK
—
100
ms
PCMIN Set-up Time
tDS
—
100
—
—
ns
tDH
—
100
—
—
ns
RDL
Pull-up resistor
0.5
—
—
kW
Receive Sync Pulse Setting Time
PCMIN Hold Time
Digital Output Load
CDL
Analog Input Allowable DC Offset
Voff
Allowable Jitter Width
—
—
—
—
100
pF
Transmit gain stage, Gain = 1
–100
—
+100
mV
Transmit gain stage, Gain = 10
–10
—
+10
mV
XSYNC, RSYNC
—
—
500
ns
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MSM7507-01/02/03
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Symbol
IDD1
Power Supply Current
IDD2
Condition
Operating mode
Power-save mode, PDN = 1,
XSYNC Æ OFF
Min.
Typ.
Max.
Unit
—
5.0
10
mA
—
1.5
3.0
mA
IDD3
Power-down mode, PDN = 0
—
0.01
0.05
mA
Input High Voltage
VIH
—
2.2
—
VDD
V
Input Low Voltage
VIL
—
0.0
—
0.8
V
High Level Input Leakage Current
IIH
—
—
—
2.0
mA
Low Level Input Leakage Current
IIL
Digital Output Low Voltage
VOL
—
Pull-up resistance > 500 W
—
—
0.5
mA
0.0
0.2
0.4
V
Digital Output Leakage Current
IO
—
—
—
10
mA
Input Capacitance
CIN
—
—
5
—
pF
Transmit Analog Interface Characteristics
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Resistance
RINX
AIN+, AIN–
10
—
—
MW
Output Load Resistance
RLGX
GSX with respect to SG
20
—
—
kW
Output Load Capacitance
CLGX
—
—
30
pF
–1.2
—
+1.2
V
–20
—
+20
mV
Output Amplitude
VOGX
Offset Voltage
VOSGX
Gain = 1
Receive Analog Interface Characteristics
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
RLVF
Output Load Resistance
Output Load Capacitance
Condition
RINPW PWI
RLAO
VFRO with respect to SG
AOUT+, AOUT– (each) with
respect to SG
Typ.
Max.
Unit
10
—
—
MW
20
—
—
kW
0.6
—
—
kW
CLVF
VFRO
—
—
30
pF
CLAO
AOUT+, AOUT–
—
—
50
pF
–1.2
—
+1.2
V
–1.3
—
+1.3
V
–100
—
+100
mV
–100
—
+100
mV
VOVF
Output Amplitude
VOAO
VFRO, RL = 20 kW with
respect to SG
AOUT+, AOUT–, RL = 0.6 kW
with respect to SG
VOSVF VFRO with respect to SG
Offset Voltage
Min.
VOSAO
AOUT+, AOUT–, Gain = 1 with
respect to SG
10/18
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MSM7507-01/02/03
AC Characteristics
(VDD = +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz)
Parameter
Transmit Frequency Response
Receive Frequency Response
Loss T1
Freq.
(Hz)
60
Loss T2
300
Loss T3
1020
Loss T4
2020
Loss T5
3000
Symbol
Unit
20
26
—
dB
–0.15
+0.07
+0.20
dB
Reference
0
dB
–0.15
–0.04
+0.20
dB
–0.15
+0.06
+0.20
dB
0
0.4
0.80
dB
300
–0.15
–0.03
+0.20
dB
Loss R2
1020
Loss R3
2020
Loss R4
Loss R5
Reference
0
dB
–0.15
0.0
+0.20
dB
3000
–0.15
+0.05
+0.20
dB
3400
0.0
0.56
0.80
dB
SD T1
3
35
43
—
SD T2
0
35
41
—
38
—
–30
1020
*1
35
31.5
–40
*2
29
SD T5
–45
*2
24
SD R1
3
36
43
—
SD R2
0
36
41
—
–30
36
40
—
SD T4
SD R4
1020
–40
SD R5
–45
GT T1
3
GT T3
*1
*2
30
*2
25
–0.3
31
27
26
33.5
32
30
27
+0.01
—
—
—
+0.3
–0.3
0
+0.3
GT T4
–50
–0.5
–0.03
+0.5
GT T5
–55
–1.2
+0.15
+1.2
GT R1
3
–0.3
0
+0.3
dB
Reference
–10
–40
–0.3
+0.08
+0.3
GT R4
–50
–0.5
+0.12
+0.5
GT R5
–55
–0.8
+0.15
+0.8
1020
dB
—
–40
GT R3
dB
Reference
–10
1020
GT R2
Receive Gain Tracking
Max.
3400
GT T2
Transmit Gain Tracking
Typ.
Loss T6
SD R3
Receive Signal to Distortion Ratio
Min.
Loss R1
SD T3
Transmit Signal to Distortion Ratio
Level Condition
(dBm0)
dB
*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
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MSM7507-01/02/03
AC Characteristics (Continued)
(VDD = +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz)
Parameter
Idle Channel Noise
Symbol
Freq.
(Hz)
Nidle T
—
Nidle R
—
Level Condition
(dBm0)
AIN = SG
—
*1 *2
*1 *3
—
VDD = 5.0 V
AV T
Absolute Level (Initial Difference)
(Deviation of Temperature and Power)
Typ.
Max.
–74.5
–70
–72.5
–69
—
–78
–75
0.58
0.6007
0.622
0.58
0.6007
0.622
–0.2
—
+0.2
dB
–0.2
—
+0.2
dB
—
—
0.60
ms
—
0.19
0.75
—
0.11
0.35
—
0.02
0.125
—
AV Tt
*4
1020
0
VDD = +5 V
±5%
Ta = –30
AV Rt
to 85°C *4
Unit
dBmOp
Vrms
Ta = 25°C
AV R
Absolute Level
Min.
A to A
Absolute Delay
Td
1020
0
BCLK
= 64 kHz
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
*1
*2
*3
*4
*5
tgd T1
500
tgd T2
600
tgd T3
1000
tgd T4
2600
—
0.05
0.125
tgd T5
2800
—
0.07
0.75
tgd R1
500
tgd R2
600
tgd R3
1000
tgd R4
2600
tgd R5
2800
CR T
CR R
1020
*5
0
*5
0
0
—
0.00
0.75
—
0.00
0.35
—
0.00
0.125
—
0.09
0.125
—
0.12
0.75
TRANS Æ RECV
75
80
—
RECV Æ TRANS
70
76
—
ms
ms
dB
Psophometric filter is used
Upper is specified for the m-law, lower for the A-law
Input "0" code to PCMIN
AVR is defined at VFRO output
Minimum value of the group delay distortion
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MSM7507-01/02/03
AC Characteristics (Continued)
(VDD = +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz)
Parameter
Discrimination
Out-of-band Spurious
Intermodulation Distortion
Power Supply Noise Rejection Ratio
Freq.
Level Condition
(Hz)
(dBm0)
0 to
4.6 kHz to
DIS
0
4000 Hz
72 kHz
Symbol
S
IMD
300 to
0
3400
fa = 470
–4
fb = 320
PSR T
0 to
PSR R
50 kHz
50 mVPP
4.6 kHz to
100 kHz
2fa – fb
*6
tSD
Digital Output Delay Time
tXD1
tXD2
CL = 100 pF + 1 LSTTL
tXD3
Min.
Typ.
Max.
Unit
30
32
—
dB
—
–37.5
–35
dBmO
—
–52
–35
dBmO
—
30
—
dB
20
—
200
20
—
200
20
—
200
20
—
200
ns
*6 The measurement under idle channel noise
13/18
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MSM7507-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
1
2
tXS
XSYNC
4
5
6
7
8
9
10
11
9
10
11
tSX
tWS
tXD1
PCMOUT
3
tSD
MSD
D2
tXD2
D3
D4
D5
D6
tXD3
D8
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1.
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.
Receive Timing
BCLK
1
tRS
RSYNC
2
3
4
6
7
8
tSR
tWS
tDS
PCMIN
5
MSD
D2
tDH
D3
D4
D5
D6
D7
D8
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APPLICATION CIRCUIT
Analog interface
Digital interface
+5 V
MSM7507
1:1
51 kW
AIN–
Analog input
600 W
0.1 mF
PCMOUT
PCM signal output
XSYNC
8 kHz SYNC signal input
GSX
AIN+
SG
300 W
1:1
AOUT+
Analog output
600 W
RSYNC
BCLK
PCM shift clock input
PCMIN
PCM data input
300 W
AOUT–
PDN
Power Down control input
PWI
VFRO
51 kW
SGC
0.1 mF
0V
+5 V
10 mF
AG
–
DG
1 mF
+
VDD
0–20W
FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT
Microphone amp
M
R1
AIN–
C1
C2
R2
Transmit frequency
characteristic
Adjustment determined with
C1, C2, R1, R2
GSX
AIN+
SG
AOUT+
R5
C4
R4
AOUT–
Receive frequency
characteristic
Adjustment determined with
C3, C4, R3, R4
PWI
VFRO
R3
C3
15/18
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MSM7507-01/02/03
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.
16/18
¡ Semiconductor
MSM7507-01/02/03
PACKAGE DIMENSIONS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/18
¡ Semiconductor
MSM7507-01/02/03
(Unit : mm)
SSOP20-P-250-0.95-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
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