Cypress CY7C1041CV33-15VC 4-mbit (256k x 16) static ram Datasheet

CY7C1041CV33
4-Mbit (256K x 16) Static RAM
Functional Description[1]
Features
• Pin equivalent to CY7C1041BV33
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
• Temperature Ranges
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written
into the location specified on the address pins (A0–A17). If Byte
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O8–I/O15) is written into the location specified on the
address pins (A0–A17).
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• High speed
— tAA = 10 ns
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin 400-milSOJ, 44-pin TSOP II and 48-ball FBGA packages
The input/output pins (I/O0–I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
Pin Configuration
SOJ/
TSOP II
Top View
256K × 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
I/O0–I/O7
I/O8–I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Notes:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05134 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 1, 2006
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CY7C1041CV33
Selection Guide
-10
-12
-15
-20
Unit
10
12
15
20
ns
Commercial
90
85
80
75
mA
Industrial
100
95
90
85
mA
Automotive-A
100
Maximum Access Time
Maximum Operating Current
Automotive-E
Maximum CMOS Standby Current
Commercial/
Industrial
10
Automotive-A
10
10
10
85
mA
90
mA
10
mA
mA
Automotive-E
15
mA
Pin Configurations
48-ball FBGA
(Top View)
Document #: 38-05134 Rev. *H
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O0
BHE
A3
A4
CE
I/O8
B
I/O1
I/O 2
A5
A6
I/O10 I/O9
C
VSS
I/O3
A17
A7
I/O11
VCC
D
VCC
I/O4
NC
A16
I/O12
VSS
E
I/O6
I/O5
A14
A15
I/O13
I/O14
F
I/O7
NC
A12
A13
WE
I/O15
G
NC
A8
A9
A10
A11
NC
H
Page 2 of 12
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CY7C1041CV33
Pin Definitions
Pin Name
44-SOJ,
44-TSOP
Pin Number
48-ball FBGA
Pin Number
I/O Type
Description
Input
Address Inputs used to select one of the address
locations.
A0–A17
1–5, 18–27,
42–44
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3
I/O0–I/O15
7–10,13–16,
29–32, 35–38
B1, C1, C2, D2,
E2, F2, F1, G1,
B6, C6, C5, D5,
E5, F5, F6, G6
Input/Output Bidirectional Data I/O lines. Used as input or output lines
depending on operation
NC
28
A6, E3, G2, H1,
H6
No Connect
WE
17
G5
Input/Control Write Enable Input, active LOW. When selected LOW, a
WRITE is conducted. When selected HIGH, a READ is
conducted.
CE
6
B5
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
40, 39
B2, A1
Input/Control Byte Write Select Inputs, active LOW. BHE controls
I/O15–I/O8, BLE controls I/O7–I/O0
OE
41
A2
Input/Control Output Enable, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and
act as input data pins.
VSS
12, 34
D1, E6
VCC
11, 33
D6, E1
Document #: 38-05134 Rev. *H
Ground
No Connects. This pin is not connected to the die
Ground for the device. Should be connected to ground of the
system.
Power Supply Power Supply inputs to the device.
Page 3 of 12
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CY7C1041CV33
Maximum Ratings
Static Discharge Voltage............. ...............................>2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current...................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Commercial
Industrial
DC Input Voltage[2] .................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) .........................................20 mA
Ambient
Temperature
VCC
0°C to +70°C
3.3V ± 0.3V
–40°C to +85°C
Automotive-A
–40°C to +85°C
Automotive-E
–40°C to +125°C
DC Electrical Characteristics Over the Operating Range
-10
Parameter
Description
Test Conditions
-12
Min. Max.
Min.
-15
Max.
Min.
-20
Max.
VOH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
VIL[2]
Input LOW Voltage
–0.3
0.8
–0.3
0.8
–0.3
IIX
Input Leakage
Current
Com’l/Ind’l
–1
+1
–1
+1
–1
Auto-A
–1
+1
GND < VI < VCC
2.4
2.4
0.4
2.4
Output Leakage
Current
GND < VOUT < VCC, Com’l/Ind’l
Output Disabled
Auto-A
–1
+1
0.4
–1
+1
–1
+1
0.4
–1
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
V
2.0
VCC
+ 0.3
V
0.8
–0.3
0.8
V
+1
–1
+1
µA
–1
+1
µA
–20
+20
µA
–1
+1
µA
–1
+1
µA
–20
+20
µA
+1
Com’l
90
85
80
75
mA
Ind’l
100
95
90
85
mA
Auto-A
100
Auto-E
ISB1
ISB2
V
0.4
Auto-E
ICC
Max. Unit
2.4
Auto-E
IOZ
Min.
Max. VCC,
Automatic CE
Com’l/Ind’l
Power-down Current CE > VIH
Auto-A
—TTL Inputs
VIN > VIH or
VIN < VIL, f = fMAX Auto-E
40
Max. VCC,
Automatic CE
Com’l/Ind’l
Power-down Current CE > VCC – 0.3V,
Auto-A
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0 Auto-E
10
40
40
40
10
10
10
85
mA
90
mA
40
mA
40
mA
45
mA
10
mA
10
mA
15
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05134 Rev. *H
Page 4 of 12
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CY7C1041CV33
Thermal Resistance[3]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance (Junction to Ambient) Test conditions follow standard
Thermal Resistance (Junction to Case) test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
TSOP-II
FBGA
SOJ
Unit
42.96
38.15
25.99
°C/W
10.75
9.15
18.8
°C/W
AC Test Loads and Waveforms[4]
10-ns Devices
12-, 15-, 20-ns Devices
Z = 50Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
OUTPUT
30 pF*
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z Characteristics
R 317Ω
ALL INPUT PULSES
3.0V
90%
90%
OUTPUT
10%
10%
GND
3.3V
R2
351Ω
5 pF
(c)
Rise Time: 1 V/ns
(d)
Fall Time: 1 V/ns
AC Switching Characteristics[5] Over the Operating Range
-10
Parameter
Description
Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Min.
Max.
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
tRC
Read Cycle Time
10
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
100
100
12
10
3
15
12
3
µs
100
20
15
3
ns
20
3
ns
ns
tACE
CE LOW to Data Valid
10
12
15
20
ns
tDOE
OE LOW to Data Valid
5
6
7
8
ns
tLZOE
OE LOW to Low-Z
0
High-Z[7, 8]
tHZOE
OE HIGH to
tLZCE
CE LOW to Low-Z[8]
tHZCE
CE HIGH to High-Z[7, 8]
0
5
3
0
6
3
5
0
7
3
6
ns
8
3
7
ns
ns
8
ns
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
10
12
15
20
ns
tDBE
Byte Enable to Data Valid
5
6
7
8
ns
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
0
0
0
0
0
6
0
0
6
ns
0
7
ns
8
ns
Notes:
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
Write.
Document #: 38-05134 Rev. *H
Page 5 of 12
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CY7C1041CV33
AC Switching Characteristics[5] Over the Operating Range (continued)
-10
Parameter
Description
Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Min.
Max.
Unit
Write Cycle[9, 10]
tWC
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
7
8
10
10
ns
tAW
Address Set-Up to Write End
7
8
10
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
10
ns
tSD
Data Set-Up to Write End
5
6
7
8
ns
tHD
Data Hold from Write End
0
0
0
0
ns
Low-Z[7]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[7, 8]
tBW
Byte Enable to End of Write
3
3
5
7
3
6
8
3
ns
7
10
8
10
ns
ns
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tHZBE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
IICC
CC
50%
IISB
SB
Notes:
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05134 Rev. *H
Page 6 of 12
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CY7C1041CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes:
14. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05134 Rev. *H
Page 7 of 12
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CY7C1041CV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05134 Rev. *H
I/O0–I/O7
I/O8–I/O15
Mode
Power
Page 8 of 12
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CY7C1041CV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1041CV33-10BAC
Package
Diagram
51-85106
48-ball Fine Pitch BGA
51-85082
44-lead (400-mil) Molded SOJ
CY7C1041CV33-10BAXC
CY7C1041CV33-10VC
44-pin TSOP II
51-85106
48-ball Fine Pitch BGA
44-pin TSOP II (Pb-Free)
CY7C1041CV33-10BAXI
CY7C1041CV33-10ZI
12
44-pin TSOP II (Pb-Free)
44-pin TSOP II (Pb-Free)
CY7C1041CV33-10BAXA
51-85106
48-ball Fine Pitch BGA (Pb-Free)
CY7C1041CV33-12VC
51-85082
44-lead (400-mil) Molded SOJ
44-pin TSOP II
CY7C1041CV33-12VXI
51-85082
44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-12ZI
51-85087
44-pin TSOP II
51-85082
51-85087
51-85082
51-85087
51-85087
44-pin TSOP II
44-pin TSOP II
Commercial
44-pin TSOP II (Pb-Free)
Automotive-A
51-85082
44-lead (400-mil) Molded SOJ
Automotive-E
51-85087
44-pin TSOP II
CY7C1041CV33-20VXE
CY7C1041CV33-20ZSXE
Industrial
44-pin TSOP II (Pb-Free)
CY7C1041CV33-20ZSXA
CY7C1041CV33-20ZE
44-lead (400-mil) Molded SOJ
44-pin TSOP II (Pb-Free)
CY7C1041CV33-20ZXC
CY7C1041CV33-20VE
44-pin TSOP II
44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-15ZXI
CY7C1041CV33-20ZC
Commercial
44-pin TSOP II (Pb-Free)
CY7C1041CV33-15VXI
CY7C1041CV33-15ZI
44-lead (400-mil) Molded SOJ
44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-15ZXC
CY7C1041CV33-15VI
Industrial
44-pin TSOP II (Pb-Free)
CY7C1041CV33-15VXC
CY7C1041CV33-15ZC
Commercial
44-pin TSOP II (Pb-Free)
CY7C1041CV33-12ZXI
CY7C1041CV33-15VC
Automotive-A
44-lead (400-mil) Molded SOJ (Pb-Free)
51-85087
CY7C1041CV33-12ZXC
20
44-pin TSOP II
CY7C1041CV33-10ZSXA
CY7C1041CV33-12VXC
15
Industrial
48-ball Fine Pitch BGA (Pb-Free)
51-85087
CY7C1041CV33-10ZXI
CY7C1041CV33-12ZC
Commercial
44-lead (400-mil) Molded SOJ (Pb-Free)
51-85087
CY7C1041CV33-10ZXC
CY7C1041CV33-10BAI
Operating
Range
48-ball Fine Pitch BGA (Pb-Free)
CY7C1041CV33-10VXC
CY7C1041CV33-10ZC
Package Type
44-lead (400-mil) Molded SOJ (Pb-Free)
44-pin TSOP II (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05134 Rev. *H
Page 9 of 12
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CY7C1041CV33
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA (51-85106)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
1
2
3
4
5
6
6
4
3
2
1
C
C
F
G
D
E
2.625
8.50±0.10
E
0.75
A
B
5.25
A
B
D
8.50±0.10
5
F
G
H
H
1.875
A
A
B
0.75
7.00±0.10
3.75
7.00±0.10
0.15 C
0.21±0.05
0.53±0.05
0.25 C
B
0.15(4X)
51-85106-*E
Document #: 38-05134 Rev. *H
1.20 MAX.
0.36
SEATING PLANE
C
Page 10 of 12
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CY7C1041CV33
Package Diagrams (continued)
44-lead (400-mil) Molded SOJ (51-85082)
51-85082-*B
44-pin TSOP II (51-85087)
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05134 Rev. *H
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
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CY7C1041CV33
Document History Page
Document Title: CY7C1041CV33 4-Mbit (256K x 16) Static RAM
Document Number: 38-05134
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
109513
12/13/01
HGK
New Data Sheet
*A
112440
12/20/01
BSS
Updated 51-85106 from revision *A to *C
*B
112859
03/25/02
DFP
Added CY7C1042CV33 in BGA package
Removed 1042 BGA option pin ACC Final Data Sheet
*C
116477
09/16/02
CEA
Add applications foot note to data sheet
*D
119797
10/21/02
DFP
Added 20-ns speed bin
*E
262949
See ECN
RKF
1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)
2) Added Automotive Specs to Datasheet
*F
361795
See ECN
SYT
Added Pb-Free offerings in the Ordering Information
*G
435387
See ECN
NXR
Removed -8 Speed bin from Product offering.
Corrected typo in description for BHE/BLE in pin definitions table on Page# 3
corrected ther Pin name from OE2 to OE.
Included the Maximum Ratings for Static Discharge Voltage and Latch up
Current.
Changed the description of IIX current from Input Load Current to
Input Leakage Current
Added note# 4 on page# 4
Updated the Ordering Information table
*H
499153
See ECN
NXR
Added Automotive-A Operating Range
Changed tpower value from 1 µs to 100 µs
Updated Ordering Information table
Document #: 38-05134 Rev. *H
Page 12 of 12
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