Elpida HB56UW1673E-F 128mb buffered edo dram dimm 16-mword ã 72-bit, 4k refresh, 1 bank module (18 pcs of 16m ã 4 components) Datasheet

HB56UW1673E-F
EO
128MB Buffered EDO DRAM DIMM
16-Mword × 72-bit, 4k Refresh, 1 Bank Module
(18 pcs of 16M × 4 components)
L
Description
E0101H10 (1st edition)
(Previous ADE-203-1123A (Z))
Jan. 31, 2001
• 168-pin socket type package (Dual lead out)
 Lead pitch : 1.27 mm
• Single 3.3 V supply : 3.3 ± 0.3 V
• High speed
 Access time: tRAC = 50 ns/60 ns (max)
 Access time: tCAC = 18 ns/20 ns (max)
• Low power dissipation
 Active mode: 8.46 W/7.16 W (max)
 Standby mode (TTL): 166 mW (max)
• Buffered input except RAS and DQ
• 4 byte interleave enabled, dual address input (A0/B0)
This Product become EOL in August, 2005.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
t
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od
Features
Pr
The HB 56UW 1673E belongs to 8-byte DI MM (D ual in-line Memory Module) fa mily , and have bee n
developed an optimized main memory solution for 4 and 8-byte processor applications. The HB56UW1673E
is a 16 M × 72 Dyna mic R AM Module, mounted 18 piec es of 64-Mbit DR AM (H M5165405) sea led in
TS OP pac kage and 2 piec es of 16-bit line drive r sea led in TS SOP pac kage . The HB 56UW 1673E off ers
Extende d Da ta Out (ED O) P age Mode as a high spee d ac ce ss mode. An outline of the HB 56UW 1673E is
168-pin socke t type pac kage (dua l lea d out). The ref ore, the HB 56UW 1673E make s high density mounting
possible without surface mount technology. The HB56UW1673E provides common data inputs and outputs.
Decoupling capacitors are mounted beside each TSOP on the its module board.
HB56UW1673E-F
JEDEC standard outline buffered 8-byte DIMM
EDO page mode capability
4096 refresh cycles: 64 ms
2 variations of refresh
 RAS-only refresh
 CAS-before-RAS refresh
EO
•
•
•
•
Ordering Information
Type No.
Access time
Package
Contact pad
HB56UW1673E-5F
HB56UW1673E-6F
50 ns
60 ns
168-pin dual lead out
socket type
Gold
L
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
Signal name Pin No.
Signal name Pin No.
Pr
Signal name
VSS
85
VSS
127
VSS
44
OE2
86
DQ36
128
NC
DQ1
45
RE2
87
DQ37
129
NC
4
DQ2
46
CE4
88
DQ38
130
NC
5
DQ3
47
NC
89
DQ39
131
NC
6
VCC
48
WE2
90
VCC
132
PDE
7
DQ4
49
VCC
91
DQ40
133
VCC
8
DQ5
50
NC
92
DQ41
134
NC
9
DQ6
51
NC
93
DQ42
135
NC
10
DQ7
52
DQ18
94
DQ43
136
DQ54
11
DQ8
53
DQ19
95
DQ44
137
DQ55
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ20
97
DQ45
139
DQ56
14
DQ10
56
DQ21
98
DQ46
140
DQ57
15
DQ11
57
DQ22
99
DQ47
141
DQ58
85 pin 94 pin 95 pin 124 pin 125 pin
Signal name Pin No.
1
VSS
43
2
DQ0
3
t
Data Sheet E0101H10
2
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Pin No.
168 pin
HB56UW1673E-F
Pin Arrangement (cont)
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
16
DQ12
58
DQ23
100
DQ48
142
DQ59
17
DQ13
59
VCC
101
DQ49
143
VCC
18
VCC
60
DQ24
102
VCC
144
DQ60
19
DQ14
61
NC
103
DQ50
145
NC
20
DQ15
62
NC
104
DQ51
146
NC
21
DQ16
63
NC
105
DQ52
147
NC
22
DQ17
64
NC
106
DQ53
148
NC
23
VSS
65
DQ25
107
VSS
149
DQ61
24
NC
66
DQ26
108
NC
150
DQ62
25
NC
67
DQ27
109
NC
151
DQ63
26
VCC
68
VSS
110
VCC
152
VSS
27
WE0
69
DQ28
111
NC
153
DQ64
28
CE0
70
DQ29
112
NC
154
DQ65
29
NC
71
DQ30
113
NC
155
DQ66
30
RE0
72
31
OE0
73
32
VSS
74
33
A0
75
34
A2
76
35
A4
77
36
A6
37
L
EO
Pin No.
Pr
114
NC
156
DQ67
VCC
115
NC
157
VCC
DQ32
116
VSS
158
DQ68
DQ33
117
A1
159
DQ69
DQ34
118
A3
160
DQ70
DQ35
119
A5
161
DQ71
78
VSS
120
A8
79
PD1
121
38
A10
80
PD3
122
39
NC
81
PD5
123
40
VCC
82
PD7
124
41
NC
83
ID0(VSS )
125
42
NC
84
VCC
126
uc
od
DQ31
A7
162
VSS
A9
163
PD2
A11
164
PD4
NC
165
PD6
VCC
166
PD8
NC
167
ID1 (VSS )
B0
168
VCC
t
Data Sheet E0101H10
3
HB56UW1673E-F
Pin Description
Pin name
Function
EO
A0 to A11, B0
Address input
Row address
A0 to A11, B0
Column address A0 to A11, B0
Refresh address A0 to A11, B0
Data input/output
RE0, RE2
Row address strobe (RAS)
CE0, CE4
Column address strobe (CAS)
WE0, WE2
Read/Write enable
OE0, OE2
Output enable
L
DQ0 to DQ71
PD1 to PD8
Presence detect
ID0, ID1
ID bit
PDE
Presence detect Enable
Power supply
VSS
Ground
NC
Pr
VCC
No connection
Presence Detect Pin Assignment (Controlled by PDE pin)
PDE = Low
Pin No.
50 ns
PD1
79
1
PD2
163
1
PD3
80
1
PD4
164
1
PD5
81
1
PD6
165
0
PD7
82
0
PD8
166
0
1 : High level (driver output)
0 : Low level (driver output)
60 ns
All
1
High-Z
1
High-Z
1
High-Z
1
High-Z
1
High-Z
1
High-Z
1
High-Z
0
High-Z
t
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od
Pin name
PDE = High
Data Sheet E0101H10
4
HB56UW1673E-F
Block Diagram
RE2
CE4
WE2
OE2
EO
RE0
CE0
WE0
OE0
CAS RAS WE OE
I/O
I/O
D0
I/O
I/O
DQ36
DQ37
DQ38
DQ39
CAS RAS WE OE
I/O
I/O
D9
I/O
I/O
DQ4
DQ5
DQ6
DQ7
CAS RAS WE OE
I/O
I/O
D1
I/O
I/O
DQ40
DQ41
DQ42
DQ43
CAS RAS WE OE
I/O
I/O
D10
I/O
I/O
DQ8
DQ9
DQ10
DQ11
CAS RAS WE OE
I/O
I/O
D2
I/O
I/O
DQ44
DQ45
DQ46
DQ47
CAS RAS WE OE
I/O
I/O
D11
I/O
I/O
CAS RAS WE OE
I/O
I/O
D3
I/O
I/O
DQ48
DQ49
DQ50
DQ51
CAS RAS WE OE
I/O
I/O
D12
I/O
I/O
DQ16
DQ17
DQ18
DQ19
CAS RAS WE OE
I/O
I/O
D4
I/O
I/O
DQ52
DQ53
DQ54
DQ55
CAS RAS WE OE
I/O
I/O
D13
I/O
I/O
DQ20
DQ21
DQ22
DQ23
CAS RAS WE OE
I/O
I/O
D5
I/O
I/O
DQ56
DQ57
DQ58
DQ59
CAS RAS WE OE
I/O
I/O
D14
I/O
I/O
DQ24
DQ25
DQ26
DQ27
CAS RAS WE OE
I/O
I/O
D6
I/O
I/O
DQ60
DQ61
DQ62
DQ63
CAS RAS WE OE
I/O
I/O
D15
I/O
I/O
DQ28
DQ29
DQ30
DQ31
CAS RAS WE OE
I/O
I/O
D7
I/O
I/O
DQ64
DQ65
DQ66
DQ67
CAS RAS WE OE
I/O
I/O
D16
I/O
I/O
DQ32
DQ33
DQ34
DQ35
CAS RAS WE OE
I/O
I/O
D8
I/O
I/O
DQ68
DQ69
DQ70
DQ71
CAS RAS WE OE
I/O
I/O
D17
I/O
I/O
DQ12
DQ13
DQ14
DQ15
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od
VSS
Pr
A0
B0
A1 to A11
VCC
L
DQ0
DQ1
DQ2
DQ3
D0 to D8
D9 to D17
D0 to D17
D0 to D17,16-bit line driver
PD1 to PD8
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
t
VCC
VCC
VCC
VCC
D0 to D17, 16-bit line driver VCC
0.22 µF × 20 pcs
VCC
VSS
*D0 to D17: HM5165405
VCC
: 16-bit line driver
VSS
VSS
Data Sheet E0101H10
5
HB56UW1673E-F
Absolute Maximum Ratings
Parameter
Value
Unit
Terminal voltage on any pin relative to VSS
VT
–0.5 to +4.6
V
Power supply voltage relative to VSS
VCC
–0.5 to +4.6
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
19
W
Storage temperature range
Tstg
–55 to +125
°C
EO
Symbol
DC Operating Conditions
Symbol
Min
Typ
Max
Unit
Notes
VCC
3.0
3.3
3.6
V
1, 2
VSS
0
0
0
V
2
VIH
2.0
—
VCC + 0.3
V
1
Input low voltage
VIL
–0.3
—
0.8
V
1
Ambient temperature range
Ta
0
—
70
°C
Supply voltage
Input high voltage
L
Parameter
Pr
Notes: 1. All voltage referred to VSS .
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins
must be on the same level.
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Data Sheet E0101H10
6
HB56UW1673E-F
DC Characteristics
HB56UW1673E
EO
Parameter
50 ns
60 ns
Symbol Min
Max
Min
Max
Unit
Test conditions
Operating current* , * 2
I CC1
—
2350
—
1990
mA
t RC = min
Standby current
I CC2
—
46
—
46
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
19
—
19
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
2350
—
1990
mA
t RC = min
I CC5
—
100
—
100
mA
RAS = VIH, CAS = VIL
Dout = enable
I CC6
—
2350
—
1990
mA
t RC = min
EDO page mode current* 1, * 3
I CC7
—
1990
—
1810
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
Input leakage current
I LI
–5
5
–5
5
µA
0 V ≤ Vin ≤ VCC + 0.3 V
Output leakage current
I LO
–5
5
–5
5
µA
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
VOH
2.4
VCC
2.4
VCC
V
High Iout = –2 mA
Output low voltage
VOL
0
0.4
0
0.4
V
Low Iout = 2 mA
1
Standby current*
1
CAS-before-RAS refresh
current
L
RAS-only refresh current* 2
Pr
Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V)
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od
Notes : 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
20
pF
1
Input capacitance (CAS, WE, OE)
CI2
—
20
pF
1
Input capacitance (RAS)
CI3
—
78
pF
1
I/O capacitance (DQ)
CI/O
—
20
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
t
Data Sheet E0101H10
7
HB56UW1673E-F
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1 , *2 ,*19
•
•
•
•
•
EO
Test Conditions
Input rise and fall times: 2 ns
Input levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
L
Parameter
50 ns
60 ns
Max
Min
Max
Unit
Random read or write cycle time
t RC
84
—
104
—
ns
RAS precharge time
t RP
30
—
40
—
ns
CAS precharge time
t CP
8
—
10
—
ns
RAS pulse width
t RAS
50
10000
60
10000
ns
CAS pulse width
t CAS
8
10000
10
10000
ns
Row address setup time
t ASR
5
—
5
—
ns
Row address hold time
t RAH
8
—
10
—
ns
Column address setup time
t ASC
0
—
0
—
ns
Column address hold time
t CAH
8
—
10
—
ns
RAS to CAS delay time
t RCD
12
32
14
40
ns
3
RAS to column address delay time
t RAD
10
20
12
25
ns
4
RAS hold time
t RSH
18
—
20
—
ns
CAS hold time
t CSH
38
—
40
—
ns
CAS to RAS precharge time
t CRP
10
—
10
—
ns
OE to Din delay time
t OED
18
—
20
—
ns
5
OE delay time from Din
t DZO
0
—
0
—
ns
6
CAS delay time from Din
t DZC
0
—
0
—
ns
6
Transition time (rise and fall)
tT
2
50
2
50
ns
7
Notes
t
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od
Pr
Symbol Min
Data Sheet E0101H10
8
HB56UW1673E-F
Read Cycle
50 ns
60 ns
Symbol Min
Max
Min
Max
Unit
Notes
Access time from RAS
t RAC
—
50
—
60
ns
8, 9
Access time from CAS
t CAC
—
18
—
20
ns
9, 10, 17
Access time from address
t AA
—
30
—
35
ns
9, 11, 17
Access time from OE
t OEA
—
18
—
20
ns
9
Read command setup time
t RCS
0
—
0
—
ns
Read command hold time to CAS
t RCH
0
—
0
—
ns
Read command hold time from RAS
t RCHR
50
—
60
—
ns
Read command hold time to RAS
t RRH
0
—
0
—
ns
Column address to RAS lead time
t RAL
30
—
35
—
ns
Column address to CAS lead time
t CAL
15
—
18
—
ns
CAS to output in low-Z
t CLZ
2
—
2
—
ns
t OH
3
—
3
—
ns
Output data hold time from OE
t OHO
3
—
3
—
ns
Output buffer turn-off time
t OFF
—
18
—
20
ns
13, 21
Output buffer turn-off to OE
t OEZ
—
18
—
20
ns
13
CAS to Din delay time
t CDD
18
—
20
—
ns
5
Output data hold time from RAS
t OHR
3
—
3
—
ns
21
Output buffer turn-off to RAS
t OFR
—
13
—
15
ns
13, 21
Output buffer turn-off to WE
t WEZ
—
18
—
20
ns
13
WE to Din delay time
t WED
18
RAS to Din delay time
t RDD
13
Output data hold time
L
EO
Parameter
50 ns
Symbol Min
Write command setup time
t WCS
0
Write command hold time
t WCH
8
Write command pulse width
t WP
8
Write command to RAS lead time
t RWL
18
Write command to CAS lead time
t CWL
8
Data-in setup time
t DS
0
Data-in hold time
t DH
13
21
—
20
—
ns
—
15
—
ns
60 ns
Max
Min
Max
Unit
Notes
—
0
—
ns
14
—
10
—
ns
—
10
—
ns
—
20
—
ns
—
10
—
ns
—
0
—
ns
15
—
15
—
ns
15
t
Parameter
12
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od
Pr
Write Cycle
12
Data Sheet E0101H10
9
HB56UW1673E-F
Read-Modify-Write Cycle
HB56UW1673E
EO
50 ns
60 ns
Parameter
Symbol Min
Max
Min
Max
Unit
Read-modify-write cycle time
t RWC
116
—
140
—
ns
RAS to WE delay time
t RWD
72
—
84
—
ns
14
CAS to WE delay time
t CWD
30
—
34
—
ns
14
Column address to WE delay time
t AWD
42
—
49
—
ns
14
OE hold time from WE
t OEH
13
—
15
—
ns
L
Refresh Cycle
50 ns
Parameter
60 ns
Max
Min
Max
Unit
CAS setup time (CBR refresh cycle)
t CSR
10
—
10
—
ns
CAS hold time (CBR refresh cycle)
t CHR
8
—
10
—
ns
WE setup time (CBR refresh cycle)
t WRP
5
—
5
—
ns
WE hold time (CBR refresh cycle)
t WRH
8
—
10
—
ns
RAS precharge to CAS hold time
t RPC
5
—
5
—
ns
50 ns
Parameter
Symbol Min
EDO page mode cycle time
t HPC
20
EDO page mode RAS pulse width
t RASP
—
Access time from CAS precharge
t CPA
—
RAS hold time from CAS precharge
t CPRH
33
Output data hold time from CAS low
t DOH
3
CAS hold time referred OE
t COL
8
CAS to OE setup time
t COP
5
Read command hold time from CAS
precharge
t RCHC
28
Write pulse width during CAS precharge t WPE
8
OE precharge time
8
t OEP
Notes
uc
od
Pr
Symbol Min
EDO Page Mode Cycle
Notes
60 ns
Max
Min
Max
Unit
Notes
—
25
—
ns
20
100000 —
100000 ns
16
33
—
40
ns
9, 17
—
40
—
ns
—
3
—
ns
—
10
—
ns
—
5
—
ns
—
35
—
ns
—
10
—
ns
—
10
—
ns
9, 22
t
Data Sheet E0101H10
10
HB56UW1673E-F
EDO Page Mode Read-Modify-Write Cycle
50 ns
60 ns
Symbol Min
Max
Min
Max
Unit
EDO page mode read- modify-write
cycle time
t HPRWC
57
—
68
—
ns
WE delay time from CAS precharge
t CPW
45
—
54
—
ns
EO
Parameter
Notes
14
Refresh
Symbol
Max
Unit
Notes
Refresh period
t REF
64
ms
4096 cycles
L
Parameter
t
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od
Pr
Notes: 1. AC measurements assume t T = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a
reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is
controlled exclusively by t CAC .
4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a
reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is
controlled exclusively by t AA .
5. Either t OED or t CDD must be satisfied.
6. Either t DZO or t DZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max).
11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max).
12. Either t RCH or t RRH must be satisfied for a read cycles.
13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min),
t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the
cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed
write or read-modify-write cycles.
16. t RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t AA , t CAC and t CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
Data Sheet E0101H10
11
HB56UW1673E-F
L
EO
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes large
VCC/V SS line noise, which causes to degrade VIH min/VIL max level.
20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page
mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the
specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO
page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold
time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS
between t OHR and t OH and between t OFR and t OFF.
22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
t
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Data Sheet E0101H10
12
HB56UW1673E-F
Timing Waveforms*23
Read Cycle
EO
tRC
tRAS
tRP
RAS
tT
tCAS
tRAD
tASR
Address
tCRP
tRSH
L
CAS
tCSH
tRCD
tRAL
tCAL
tASC
tRAH
tCAH
Column
Row
Pr
tRRH
tRCHR
tRCS
WE
tRCH
tDZC
tWED
uc
od
tCDD
tRDD
High-Z
;
Din
tDZO
tOEA
OE
tCAC
tAA
tRAC
tCLZ
tOED
tOEZ
tOHO
tOFF
tOH
tOFR
tOHR
tWEZ
Dout
Dout
t
Data Sheet E0101H10
13
HB56UW1673E-F
Early Write Cycle
EO
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tRAH
Row
tASC
tCAH
Column
Pr
Address
L
tASR
tWCS
WE
tWCH
Din
tDH
Din
uc
od
tDS
High-Z*
Dout
* t WCS
t WCS (min)
t
Data Sheet E0101H10
14
HB56UW1673E-F
Delayed Write Cycle*18
EO
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
Address
L
tASR
tRAH
tASC
Row
tCAH
Column
Pr
tCWL
tRWL
tWP
tRCS
WE
tDS
High-Z
Din
;
Din
tDH
uc
od
tDZC
tOED
tDZO
tOEH
tOEP
OE
tOEZ
tCLZ
High-Z
Dout
Invalid Dout
t
Data Sheet E0101H10
15
HB56UW1673E-F
Read-Modify-Write Cycle*18
EO
tRWC
tRAS
tRP
RAS
tT
tRCD
tCAS
tCRP
CAS
L
tRAD
tASR
Address
tASC
tRAH
Row
tCAH
Column
tCWL
Pr
tCWD
tRCS
tRWL
tWP
tAWD
tRWD
WE
tDZC
High-Z
Din
;
Din
tDH
uc
od
tDS
tOED
tDZO
tOEH
tOEA
OE
tCAC
tAA
tRAC
tOEZ
tOHO
Dout
Dout
tCLZ
High-Z
t
Data Sheet E0101H10
16
tOEP
HB56UW1673E-F
RAS-Only Refresh Cycle
EO
tRC
tRAS
tRP
RAS
tT
tRPC
tCRP
tCRP
CAS
tRAH
L
tASR
Row
Address
tOFR
tOFF
Pr
High-Z
t
uc
od
;
Dout
Data Sheet E0101H10
17
HB56UW1673E-F
CAS-Before-RAS Refresh Cycle
EO
tRP
tRC
tRC
tRP
tRAS
tRAS
tRP
RAS
tT
tRPC
tCP
tRPC
tCHR
tWRP
WE
tWRH
tWRP
tCHR
tWRH
Pr
Address
tOFR
tOFF
;
t
Data Sheet E0101H10
uc
od
High-Z
Dout
18
tCRP
tCSR
tCP
L
CAS
tCSR
HB56UW1673E-F
EDO Page Mode Read Cycle (1)
EO
t RP
RAS
tT
t CSH
t CP
t HPC
t CAS
CAS
t RCHR
t RCS
t HPC
t RASP
t CP
t HPC
t CPRH
t CP
t
t CRP
RSH
t CAS
tCAS
tCAS
t RCHC
t RCH t RCS
t RRH
t RCH
WE
Address
tRAH tASC
Row
tCAH
t WPE
t ASC t CAH
t ASC t CAH
L
tASR
Column 1
Column 2
t CAL
tDZC
t RAL
t CAH
tASC
Column 3
t CAL
t WED
Column 4
t CAL
t CAL
tRDD
tCDD
High-Z
Din
Pr
tCOL
tDZO
tCOP
t OEP
OE
tCPA
tOEA
tAA
tCAC
tCPA
tAA
tCAC
tOEZ
tOHO
tOEZ
tOFR
tOHR
tOEZ
tCPA
tAA
;
tCAC
tAA
tOED
tOEP
tWEZ
tRAC
tDOH
Dout 1
Dout 2
tOHO
tOHO
tOFF
tOH
tOEA
uc
od
Dout
tOEA
tCAC
Dout 2
Dout 3
Dout 4
t
Data Sheet E0101H10
19
HB56UW1673E-F
EDO Page Mode Read Cycle (2)
EO
t RP
t RASP
RAS
tT
t CSH
t CP
t HPC
t CAS
CAS
tHPC
t CP
t HPC
t CP
t CAS
t CAS
t CRP
tRSH
tCAS
t RCHC
t RRH
t RCH
t RCS
WE
Address
tRAH tASC
Row
tCAH
Column 1
Column 2
t CAL
tDZC
t ASC t CAH
t ASC t CAH
L
tASR
t RAL
t CAH
tASC
Column 3
t CAL
t WED
Column 4
t CAL
tRDD
t CAL
tCDD
High-Z
Din
Pr
tCOL
tDZO
tCOP
t OEP
OE
tOEA
tOEZ
tOFR
tOHR
tOEZ
tCPA
tAA
;
tCAC
tAA
tCPA
tAA
tCAC
tCPA
tAA
tCAC
tOED
tOEP
Dout
tDOH
tOEA
tOEZ
tDOH
tOHO
Dout 1
Dout 2
tCAC
tOHO
tOFF
tOH
tOEA
uc
od
tRAC
tOHO
Dout 2
Dout 3
Dout 4
t
Data Sheet E0101H10
20
HB56UW1673E-F
EDO Page Mode Early Write Cycle
EO
tRASP
tRP
RAS
tT
tCSH
tRCD
tHPC
tCAS
tCP
tRSH
tCAS
tCP
tCAS
tCRP
CAS
Address
Row
L
tASR
tRAH
tASC
tCAH
Column 1
tWCH
WE
Din
Dout
Column 2
tASC
tDH
Din 1
tWCS
tDS
tWCH
tCAH
Column N
tWCS
tWCH
uc
od
tDS
tCAH
Pr
tWCS
tASC
tDH
Din 2
tDS
tDH
Din N
High-Z*
* t WCS
t WCS (min)
t
Data Sheet E0101H10
21
HB56UW1673E-F
EDO Page Mode Delayed Write Cycle*18
EO
tRASP
tRP
RAS
tT
tCP
tRCD
tCRP
tCP
tCSH
tHPC
tCAS
tCAS
tRSH
tCAS
CAS
L
tRAD
tASR
tASC
tCAH
tASC
tCAH
Column 1
Column 2
tRAH
Address
Row
tASC
tCAH
tCWL
Column N
tCWL
tCWL
tRWL
Pr
tRCS
tRCS
WE
tWP
tDZC tDS
tRCS
tWP
tDZC tDS
tWP
tDZC tDS
tDH
tDH
tDZO tOED
uc
od
Din
1
Din
tDH
Din
2
tDZO
tOED
tOEP
tOEH
tDZO
tOED
tOEP
tOEH
;
tOEP
tOEH
Din
N
OE
tCLZ
tCLZ
tOEZ
Dout
Invalid Dout
Invalid Dout
tOEZ
High-Z
Invalid Dout
t
Data Sheet E0101H10
22
tCLZ
tOEZ
HB56UW1673E-F
EDO Page Mode Read-Modify-Write Cycle*18
EO
t RASP
t RP
RAS
tT
t RCD
t HPRWC
t CP
t RSH
t CP
t CAS
t CAS
t CRP
t CAS
CAS
L
t RAD
t ASR
Address
t ASC
t RAH
Row
t CAH
Column 1
t ASC
t CAH
Column 2
t RWD
t CWL
t CPW
WE
t WP
t
t DZC DS
t CWL
t WP
t
t DZC DS
t DH
t OEP
t OEH
Din
2
t OED
t DZO
t OEP
t OEH
OE
Din
N
t OED
t DZO
t OEP
t OEH
t OHO
t OHO
;
;
t OHO
t DH
uc
od
t OED
t RWL
t CWD
t WP
t
t DZC DS
Din
1
t DZO
t CWL
t AWD
t RCS
t CWD
t DH
Din
t CPW
t AWD
t RCS
t CWD
Column N
Pr
t AWD
t RCS
t ASC
t CAH
t OEA
t CAC
t OEA
t CAC
t AA
t OEA
t CAC
t AA
t CPA
t RAC
t OEZ
t CLZ
t AA
t CPA
t OEZ
t CLZ
t OEZ
t CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
t
Data Sheet E0101H10
23
HB56UW1673E-F
EDO Page Mode Mix Cycle (1) ∗20
EO
t RP
t RASP
RAS
tT
t CAS
CAS
t CRP
t CP
t CP
t CP
t CAS
tCAS
t CSH
tCAS
tCWL
tRSH
t RCD
t WCS
t WCH
tCPW
tAWD
WE
Address
Row
L
t ASC
tRAH
tASR
tCAH
Column 1
t RRH
t RCH
t RCS
t RCS
t ASC t CAH
tASC t CAH
Column 2
Column 3
tWP
tASC
t RAL
t CAH
Column 4
t CAL
t DS
Din 1
t DH
t DS
High-Z
Pr
Din
tRDD
tCDD
t CAL
t DH
Din 3
;
tOED
tOEP
OE
tCPA
tAA
tOEA
tCPA
tAA
Dout
tOFR
tWEZ
tCPA
tAA
tOEZ
tCAC
tOHO
uc
od
tCAC
t OEZ
tWED
t DOH
Dout 2
tCAC t OHO
Dout 3
tOEA
tOFF
tOH
Dout 4
t
Data Sheet E0101H10
24
HB56UW1673E-F
EDO Page Mode Mix Cycle (2) ∗20
EO
t RP
t RASP
RAS
tT
t CSH
t CAS
CAS
t RCD
t CAS
tCAS
t RCHR
t RCS
t RCH
tWCS t WCH
tCWL
Address
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
Column 3
tRSH
t RCS
t RRH
t RCH
tWP
tCPW
L
t ASC
tRAH
tCAS
t RCS
WE
tASR
t CRP
t CP
t CP
t CP
t RAL
t CAH
tASC
Column 4
t CAL
t DS
t DS
t DH
tRDD
tCDD
t DH
Pr
High-Z
Din
t CAL
Din 2
Din 3
t OEP
t OEP
tOED
tOED
tCOP
tWED
tCOL
OE
t OEA
tAA
tOEA
tCAC
tOEZ
t OHO
Dout 1
tOEZ
tAA
tCAC
tOEZ
tOEA
tOFF
tOH
tOHO
uc
od
tCAC
tRAC
Dout
tCPA
tAA
tOFR
tWEZ
tCPA
t OHO
Dout 3
Dout 4
t
Data Sheet E0101H10
25
HB56UW1673E-F
Physical Outline
EO
HB56UW1673E Series
Unit: mm
inch
Front side
4.00 max
0.157 max
127.35
5.014
L
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Component area
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(Front)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1
84
B
C
11.43
8.89
0.350
0.450
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;;
4.00 min
0.157 min
3.00
0.118
3.00
0.118
133.35
5.250
A
36.83
1.450
1.27 ± 0.10
0.050 ±0.004
54.61
2.150
85
3.175
0.125
3.125 ± 0.125
0.123 ± 0.005
0.25 max
0.010 max
2.54 min
0.100 min
168
1.00 ± 0.05
0.039 ± 0.002
Detail B and C
1.27
0.050
uc
od
Detail A
4.00
0.157
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Component area
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(Back)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
31.75
1.250
Pr
2 – φ 3.00
2 – φ 0.118
17.78
0.700
Back side
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
t
Data Sheet E0101H10
26
HB56UW1673E-F
Cautions
L
EO
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained
in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third
party’s rights, including intellectual property rights, in connection with use of the information contained
in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such
as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily
injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
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Data Sheet E0101H10
27
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