Hitachi HD61202U Dot matrix liquid crystal graphicdisplay column driver Datasheet

HD61202U
(Dot Matrix Liquid Crystal GraphicDisplay Column Driver)
Description
HD61202U is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores
the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot
matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to on/off state of a dot of a liquid crystal display to provide
more flexible than character display.
As it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic
displays with many dots.
The HD61202U, which is produced in the CMOS process, can complete portable battery drive equipment
in combination with a CMOS micro-controller, utilizing the liquid crystal display’s low power
dissipation.
Moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination
with the row (common) driver HD61203U.
Features
• Dot matrix liquid crystal graphic display column driver incorporating display RAM
• RAM data direct display by internal display RAM
 RAM bit data 1: On
 RAM bit data 0: Off
• Internal display RAM address counter preset, increment
• Display RAM capacity: 512 bytes (4096 bits)
• 8-bit parallel interface
• Internal liquid crystal display driver circuit: 64
• Display duty cycle
Drives liquid crystal panels with 1/32–1/64 duty cycle multiplexing
816
HD61202U
• Wide range of instruction function
Display data read/write, display on/off, set address, set display start line, read status
• Lower power dissipation: during display 2 mW max
• Power supply: VCC: 2.7V~5.5V
• Liquid crystal display driving voltage: 8V to 16V
• CMOS process
Ordering Information
Type No.
Package
HD61202UFS
100-pin plastic QFP (FP-100A)
HD61202UTE
100-pin thin plastic QFP (TFP-100B)
HCD61202U
Chip
817
HD61202U
HD61202UFS
(FP-100A)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
ADC
M
VCC
V4R
V3R
V2R
V1R
VEE2
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
FRM
E
ø1
ø2
CL
D/I
R/W
RST
CS1
CS2
CS3
NC
NC
NC
DB7
DB6
DB5
DB4
DB3
DB2
Pin Arrangement
(Top view)
818
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DB1
DB0
GND
V4L
V3L
V2L
V1L
VEE1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
HD61202UTE
(TFP-100B)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V4L
V3L
V2L
Y1L
VEE1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y45
Y44
Y43
Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
VCC
V4R
V3R
V2R
V1R
VEE2
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
M
ADC
FRM
E
ø1
ø2
CL
D/I
R/W
RST
NC
CS1
NC
CS2
CS3
NC
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
GND
HD61202U
(Top view)
819
HD61202U
HCD61202U PAD Arrangement
No.1
NO.78
NO.3
CHIP CODE
HD61202U
NO.54
NO.27
No.28
Chip Size
: 4.08 × 4.08 mm2
Coordinate
: Pad Center
Origin
: Chip center
Pad Size
: 90 × 90 µm2
PAD PAD
No. Name
Coordinate
X
Y
Coordinate
PAD PAD
Y
No. Name X
No.53
HCD61202U Pad Location Coordinates
Coordinate
PAD PAD
No. Name X
Y
820
Coordinate
PAD PAD
Y
No. Name X
1
ADC
–1493
1756
26
Y47
–1789 –1508
51 Y22
1452 –1789
76
V3L
1789
1442
2
–1649
1756
27
Y46
–1789 –1653
52 Y21
1604 –1789
77
V4L
1789
1590
–1789
1689
28
Y45
–1764 –1789
53 Y20
1764 –1789
78
GND
1789
1756
1445
29
Y44
–1604 –1789
54 Y19
1789 –1654
79
DB0
1495
1756
1293
30
Y43
–1452 –1789
55 Y18
1789 –1507
80
DB1
56 Y17
1789 –1369
81
DB2
1335
1176
1756
3
M
VCC
4
V4R
5
V3R
–1789
–1789
6
V2R
–1789
1148
31
Y42
–1312 –1789
7
V1R
VEE2
–1789
–1789
1011
32
Y41
–1171 –1789
57 Y16
1789 –1230
82
DB3
1016
1756
8
869
33
Y40
–976 –1789
58 Y15
1789 –1100
83
DB4
854
1756
9
Y64
–1789
721
34
Y39
59 Y14
84
DB5
694
1756
Y63
–1789
591
35
Y38
60 Y13
1789
1789
–970
10
–846 –1789
–716 –1789
–840
85
DB6
535
1756
375
1756
11
Y62
–1789
461
36
Y37
–586 –1789
61 Y12
1789
–710
86
DB7
12
Y61
–1789
331
37
Y36
–456 –1789
62 Y11
1789
–580
87
NC
1756
13
Y60
–1789
201
38
Y35
–326 –1789
63 Y10
1789
–450
88
NC
14
Y59
–1789
71
39
Y34
–196 –1789
64 Y9
1789
–320
89
NC
15
Y58
–1789
–60
40
Y33
–65 –1789
90
CS3
218
1756
–1789
–190
41
Y32
65 –1789
Y8
Y7
–190
Y57
65
66
1789
16
1789
–60
91
CS2
62
1756
17
Y56
–1789
–320
42
Y31
195 –1789
67
Y6
1789
71
92
CS1
–94
1756
18
Y55
–1789
–450
43
Y30
325 –1789
Y5
1789
201
93
RST
–249
1756
19
Y54
–1789
–580
44
Y29
455 –1789
68
69
Y4
1789
331
94
R/W
–405
1756
20
Y53
–1789
–710
45
Y28
585 –1789
70 Y3
1789
461
95
D/I
–560
1756
21
Y52
–1789
–840
46
Y27
715 –1789
71 Y2
1789
96
CL
–716
1756
22
Y51
–1789
–970
47
Y26
845 –1789
1789
97
ø2
–871
1756
23
Y50
–1789 –1100
48
Y25
975 –1789
72 Y1
73 VEE1
591
721
1789
1024
98
ø1
–1027
1756
24
Y49
–1789 –1230
49
Y24
1170 –1789
74
V1L
1789
1153
99
E
–1182
1756
25
Y48
–1789 –1369
50
Y23
1311 –1789
75
V2L
1789
1293
100
FRM –1338
1756
CS1, CS2, CS3
R/W
D/I
E
DB0–DB7
8
6
8
8
Input register
I/O buffer
Output register
Display
on/off
64
62
63
64
62
63
64
1
2
3
Display data latch
6
64
1
2
3
Liquid crystal display
driver circuit
Display start
line register
Z address counter
6
4096 bit
Display data RAM
9
XY address counter
M
8
3
VCC
GND
VEE1
VEE2
9
ADC
8
Interface control
V1R
V2R
V3R
V4R
Y62
Y63
Y64
Y1
Y2
Y3
V1L
V2L
V3L
V4L
HD61202U
Block Diagram
CL
FRM
Instruction
register
Busy
flag
RST
ø1
ø2
821
HD61202U
Terminal Functions
Terminal
Name
Number of
Terminals
VCC
GND
2
I/O
Connected to
Functions
Power supply
Power supply for internal logic.
Recommended voltage is:
GND = 0V
VCC = 2.7 to 5.5V
VEE1
VEE2
2
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
8
Power supply
Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is VCC–VEE = 8 to
16V. Connect the same power supply to VEE1 and VEE2.
VEE1 and VEE2 are not connected each other in the LSI.
Power supply
Power supply for liquid crystal display drive.
Apply the voltage specified depending on liquid crystals
within the limit of VEE through VCC.
V1L (V1R), V2L (V2R): Selection level
V3L (V3R), V4L (V4R): Non-selection level
Power supplies connected with V1L and V1R (V2L &
V2R, V3L & V3R, V4L & V4R) should have the same
voltages.
&6
&6
3
I
MPU
CS3
E
Chip selection.
Data can be input or output when the terminals are in
the following conditions:
1
I
MPU
Terminal name
&6
&6
CS3
Condition
L
L
H
Enable.
At write (R/W = low): Data of DB0 to DB7 is latched at
the fall of E.
At read (R/W = high): Data appears at DB0 to DB7
while
E is at high level.
R/W
1
I
MPU
Read/write.
R/W = High: Data appears at DB0 to DB7 and can be
read by the MPU.
When E = high, &6, &6 = low and
CS3 = high.
R/W = Low: DB0 to DB7 can accept at fall of E when
&6, &6 = low and CS3 = high.
D/I
1
I
MPU
Data/instruction.
D/I = High: Indicates that the data of DB0 to DB7 is
display data.
D/I = Low: Indicates that the data of DB0 to DB7 is
display control data.
822
HD61202U
Terminal
Name
Number of
Terminals
I/O
Connected to
Functions
ADC
1
I
VCC/GND
Address control signal to determine the relation between
Y address of display RAM and terminals from which the
data is output.
ADC = High: Y1: H’0, Y64: H’63
ACD = Low: Y64: H’0, Y1: H’63
DB0–DB7
8
I/O
MPU
Data bus, three-state I/O common terminal.
M
1
I
HD61203U
Switch signal to convert liquid crystal drive waveform
into AC.
FRM
1
I
HD61203U
Display synchronous signal (frame signal).
Presets the 6-bit display line counter and synchronizes
the common signal with the frame timing when the FRM
signal becomes high.
CL
1
I
HD61203U
ø1, ø2
2
I
HD61203U
Synchronous signal to latch display data. The rising CL
signal increments the display output address counter
and latches the display data.
2-phase clock signal for internal operation.
The ø1 and ø2 clocks are used to perform operations
(I/O of display data and execution of instructions) other
than display.
Y1–Y64
64
O
Liquid crystal
display
Liquid crystal display column (segment) drive output.
The outputs at these pins are at the light-on level when
the display RAM data is 1, and at the light-off level when
the display RAM data is 0.
Relation among output level, M, and display data (D) is
as follows:
1
M
D
Output
level
567
1
I
MPU or
external CR
1
0
0
1
0
V1 V3 V2 V4
The following registers can be initialized by setting the
567 signal to low level.
1. On/off register 0 set (display off)
2. Display start line register line 0 set (displays from line
0)
After releasing reset, this condition can be changed only
by instruction.
NC
3
Open
Unused terminals. Don’t connect any lines to these
terminals.
Note: 1 corresponds to high level in positive logic.
823
HD61202U
Function of Each Block
Interface Control
I/O Buffer: Data is transferred through 8 data bus lines (DB0–DB7).
DB7: MSB (most significant bit)
DB0: LSB (least significant bit)
Data can neither be input nor output unless &6 to CS3 are in the active mode. Therefore, when &6 to
CS3 are not in active mode it is useless to switch the signals of input terminals except 567 and ADC;
that is namely, the internal state is maintained and no instruction excutes. Besides, pay attention to 567
and ADC which operate irrespectively of &6 to CS3.
Register: Both input register and output register are provided to interface to an MPU whose speed is
different from that of internal operation. The selection of these registers depend on the combination of
R/W and D/I signals (Table 1).
1. Input register
The input register is used to store data temporarily before writing it into display data RAM.
The data from MPU is written into input register, then into display data RAM automatically by
internal operation. When &6 to CS3 are in the active mode and D/I and R/W select the input register
as shown in Table 1, data is latched at the fall of the E signal.
2. Output register
The output register is used to store data temporarily that is read from display data RAM. To read out
the data from the output register, &6 to CS3 should be in the active mode and both D/I and R/W
should be 1. With the read display data instruction, data stored in the output register is output while E
is high level. Then, at the fall of E, the display data at the indicated address is latched into the output
register and the address is increased by 1.
The contents in the output register are rewritten by the read display data instruction, but are held by
address set instruction, etc.
Therefore, the data of the specified address cannot be output with the read display data instruction
right after the address is set, but can be output at the second read of data. That is to say, one dummy
read is necessary. Figure 1 shows the MPU read timing.
Table 1
Register Selection
D/I
1
R/W
1
1
0
0
1
Operation
Reads data out of output register as internal operation (display data RAM →
output register)
Writes data into input register as internal operation (input register → display
data RAM)
Busy check. Read of status data.
0
0
Instruction
824
HD61202U
Busy Flag
Busy flag = 1 indicates that HD61202U is operating and no instructions except status read instruction can
be accepted. The value of the busy flag is read out on DB7 by the status read instruction. Make sure that
the busy flag is reset (0) before issuing instructions.
D/I
R/W
E
Address
N
Output
register
DB0–DB7
N+1
Data at address N
Busy
check
Write
address N
Busy
check
Read data
(dummy)
Busy
check
Read
data at
address N
N+2
Data at address N + 1
Busy
check
Data read
address
N+1
Figure 1 MPU Read Timing
E
Busy
flag
T Busy
1/fCLK ≤ T Busy ≤ 3/fCLK
fCLK is ø1, ø2 frequency
Figure 2 Busy Flag
825
HD61202U
Display On/Off Flip/Flop
The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In on
state, the display data corresponding to that in RAM is output to the segments. On the other hand, the
display data at all segments disappear in off state independent of the data in RAM. It is controlled by
display on/off instruction. 567 signal = 0 sets the segments in off state. The status of the flip/flop is
output to DB5 by status read instruction. Display on/off instruction does not influence data in RAM. To
control display data latch by this flip/flop, CL signal (display synchronous signal) should be input
correctly.
Display Start Line Register
The display start line register specifies the line in RAM which corresponds to the top line of LCD panel,
when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the screen.
6-bit display start line information is written into this register by the display start line set instruction.
When high level of the FRM signal starts the display, the information in this register is transferred to the
Z address counter, which controls the display address, presetting the Z address counter.
X, Y Address Counter
A 9-bit counter which designates addresses of the internal display data RAM. X address counter (upper 3
bits) and Y address counter (lower 6 bits) should be set to each address by the respective instructions.
1. X address counter
Ordinary register with no count functions. An address is set by instruction.
2. Y address counter
An Address is set by instruction and is increased by 1 automatically by R/W operations of display
data. The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off (data =
0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and segment pins can
be reversed by ADC signal.
As the ADC signal controls the Y address counter, reversing of the signal during the operation causes
malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to connect
ADC pin to VCC or GND when using.
Figure 3 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1 and
ADC = 0 (display start line = 0, 1/64 duty cycle).
826
HD61202U
LCD display
pattern
Y Y
62 63 Y64
Y1 Y2Y3 Y4 Y5 Y6
Line 0
Line 1
Line 2
X=0
Display
RAM data
0 1 1 1 0 0
0
0 0 1
1 0 0 0 1 0
0
0 0 1
1 0 0 0 1 0
1
0 0 1
1 0 0 0 1 0
0
1 0 1
1 1 1 1 1 0
0
0 1 1
1 0 0 0 1 0
0
0 0 1
1 0 0 0 1 0
0
0 0 1
0 0 0 0 0 0
0
0 0 0
0 0 0 0 0 0
0
0 0 0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
(HD61203U X1)
(HD61203U X2)
(HD61203U X3)
(HD61203U X4)
(HD61203U X5)
(HD61203U X6)
(HD61203U X7)
(HD61203U X8)
(HD61203U X9)
COM62
COM63
COM64
(HD61203U X62)
(HD61203U X63)
(HD61203U X64)
HD61202U pin name
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
X=1
X=7
Line 62
Line 63
1
0 1 0 0 0
0
0 0 0
1 1 1 1 1
0
0 0 0
0 0 0 0 0
0
0 0 0
0 1 2 3 4 5
61 62 63
RAM Y address
ADC = 1 (connected to VCC)
Figure 3 Relation between RAM Data and Display
827
HD61202U
LCD display
pattern
Y Y Y Y
64 63 62 61
Line 0
Line 1
Line 2
X=0
Display
RAM data
Y
59
Y3 Y2 Y1
0 1 1 1 0 0
0
0 0 1
1 0 0 0 1 0
0
0 0 1
1 0 0 0 1 0
1
0 0 1
1 0 0 0 1 0
0
1 0 1
1 1 1 1 1 0
0
0 1 1
1 0 0 0 1 0
0
0 0 1
1 0 0 0 1 0
0
0 0 1
0 0 0 0 0 0
0
0 0 0
0 0 0 0 0 0
0
0 0 0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
(HD61203U X1)
(HD61203U X2)
(HD61203U X3)
(HD61203U X4)
(HD61203U X5)
(HD61203U X6)
(HD61203U X7)
(HD61203U X8)
(HD61203U X9)
COM62
COM63
COM64
(HD61203U X62)
(HD61203U X63)
(HD61203U X64)
HD61202U pin name
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
X=1
X=7
Line 62
Line 63
1
0 1 0 0 0 0
0 0 0
1 1 1 1 1 0
0 0 0
0 0 0 0 0 0
0 0 0
0 1 2 3 4 5
61 62 63
RAM Y address
ADC = 0 (connected to GND)
Figure 3 Relation between RAM Data and Display (cont)
828
HD61202U
Z Address Counter
The Z address counter generates addresses for outputting the display data synchronized with the common
signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high level of FRM,
the contents of the display start line register is present at the Z counter.
Display Data Latch
The display data latch stores the display data temporarily that is output from display data RAM to the
liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction
controls the data in this latch and does not influence data in dicsplay data RAM.
Liquid Crystal Display Driver Circuit
The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels, V1,
V2, V3, and V4 to be output.
Reset
The system can be initialized by setting 567 terminal at low level when turning power on.
1. Display off
2. Set display start line register line 0.
While 567 is low level, no instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (ready) by status read
instruction. The conditions of power supply at initial power up are shown in Table 2.
Table 2
Power Supply Initial Conditions
Item
Symbol
Min
Typ
Max
Unit
Reset time
tRST
1.0
—
—
µs
Do not fail to set the system again because RESET during operation may destroy the data in all the
registers except on/off register and in RAM.
tRST
RST VILC
Reset timing
829
HD61202U
Display Control Instructions
Outline
Table 3 shows the instructions. Read/write (R/W) signal, data/instruction (D/I) signal, and data bus
signals (DB0 to DB7) are also called instructions because the internal operation depends on the signals
from the MPU.
These explanations are detailed in the following pages. Generally, there are following three kinds of
instructions:
1. Instruction to set addresses in the internal RAM
2. Instruction to transfer data from/to the internal RAM
3. Other instructions
In general use, the second type of instruction is used most frequently. Since Y address of the internal
RAM is increased by 1 automatically after writing (reading) data, the program can be shortened. During
the execution of an instruction, the system cannot accept instructions other than status read instruction.
Send instructions from MPU after making sure that the busy flag is 0, which is proof that an instruction is
not being executed.
830
0
0
0
0
1
0
1
Display on/off
Display start line
Set page (X address)
Set Y address
Status read
Write display data
Read display data
1
1
0
0
0
0
0
D/I
1
0
1
0
DB6
Read data
Write data
Busy 0
0
1
1
0
DB7
1
DB3
1
DB2
1
1
1
ON/
OFF
Reset 0
Y address (0–63)
1
DB1
1
0
0
Page (0–7)
Display start line (0–63)
1
DB4
Code
DB5
Note: Busy time varies with the frequency (fCLK) of ø1, and ø2.
(1/fCLK ≤ TBUSY ≤ 3/fCLK)
R/W
DB0
0
1/0
Functions
1: Reset
0: Normal
Reads data DB0 (LSB)
to DB7 (MSB) from the
display RAM to the data
bus.
Has access to the
address of the display
RAM specified in
advance. After the
access, Y address is
increased by 1.
1: Internal operation
0: Ready
Writes data DB0 (LSB)
to DB7 (MSB) on the
data bus into display
RAM.
Busy
ON/OFF 1: Display off
0: Display on
RESET
Reads the status.
Sets the Y address in the Y address counter.
Sets the page (X address) of RAM at the page
(X address) register.
Specifies the RAM line displayed at the top of the
screen.
Controls display on/off. RAM data and internal
status are not affected. 1: on, 0: off.
Table 3
Instructions
HD61202U
Instructions
831
HD61202U
Detailed Explanation
Display On/Off
R/W D/I DB7
Code
0
0
0
DB0
0
1
1
1
1
1
MSB
D
LSB
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen
with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0
into D = 1.
Display Start Line
R/W D/I DB7
Code
0
0
1
DB0
1
A
A
A
A
A
MSB
A
LSB
Z address AAAAAA (binary) of the display data RAM is set in the display start line register and
displayed at the top of the screen. Figure 4 shows examples of display (1/64 duty cycle) when the start
line = 0–3. When the display duty cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number
of LCD screen, from the line specified by display start line instruction, is displayed.
Set Page (X Address)
R/W D/I DB7
Code
0
0
1
DB0
0
1
1
1
A
A
MSB
A
LSB
X address AAA (binary) of the display data RAM is set in the X address register. After that, writing or
reading to or from MPU is executed in this specified page until the next page is set. See Figure 5.
Set Y Address
R/W D/I DB7
Code
0
0
0
MSB
DB0
1
A
A
A
A
A
A
LSB
Y address AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Y
address counter is increased by 1 every time the data is written or read to or from MPU.
832
HD61202U
Status Read
R/W D/I DB7
Code
1
0
Busy
MSB
DB0
0
ON/
OFF RESET
0
0
0
0
LSB
• Busy
When busy is 1, the LSI is executing internal operations. No instructions are accepted while busy is 1,
so you should make sure that busy is 0 before writing the next instruction.
• ON/OFF
Shows the liquid crystal display conditions: on condition or off condition.
When on/off is 1, the display is in off condition.
When on/off is 0, the display is in on condition.
• RESET
RESET = 1 shows that the system is being initialized. In this condition, no instructions except status
read can be accepted.
RESET = 0 shows that initializing has finished and the system is in the usual operation condition.
833
HD61202U
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM60
COM61
COM62
COM63
COM64
COM60
COM61
COM62
COM63
COM64
Start line = 1
Start line = 0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM60
COM61
COM62
COM63
COM64
COM60
COM61
COM62
COM63
COM64
Start line = 2
Start line = 3
Figure 4 Relation between Start Line and Display
834
HD61202U
Write Display Data
R/W D/I DB7
Code
0
1
D
DB0
D
D
D
D
D
D
MSB
D
LSB
Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1
automatically.
Read Display Data
R/W D/I DB7
Code
1
1
D
DB0
D
D
D
D
D
D
MSB
D
LSB
Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased by 1
automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of output
register in “Function of Each Block”.
Y address
0 1 2
DB0
to
DB7
DB0
to
DB7
DB0
to
DB7
DB0
to
DB7
61 62 63
Page 0
X=0
Page 1
X=1
Page 6
X=6
Page 7
X=7
Figure 5 Address Configuration of Display Data RAM
835
HD61202U
Use of HD61202U
Interface with HD61203 (1/64 Duty Cycle)
CR
VCC
V1L, V1R
V6L, V6R
V5L, V5R
V2L, V2R
VEE
GND
VCC
V1
V6
V5
V2
VEE
VCC
C
X1
COM1
LCD panel
64 × 64 dots
X64
COM64
SEG64
R
Cf
SEG1
Rf
Y1
Y64
HD61203U
SHL
DS1
DS2
TH
CL1
FS
M/S
FCS
STB
DL
DR
M
CL2
FRM
ø1
ø2
Open
Open
M
CL
FRM
ø1
ø2
HD61202U
Power supply circuit
+5V (VCC)
VCC
RST
R1
R2
R1
R1
R3 V6
–
+
R3
–
+
R3
–
+
–
+
V3
V4
R3 V5
836
External CR
R3 V2
VEE
–10V
CS1
CS2
CS3
R/W
D/I
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
R3 V1
R1
ADC
Contrast
VCC
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
VEE1, VEE2
GND
MPU
R3 = 15 Ω
VCC
V1
V2
V3
V4
VEE
HD61202U
ø1
ø2
1
CL
64
2
3
48
49
Input
1
2
3
64
1
2
64
3
1
FRM
1 frame
M
1 frame
V1
V6
X1
V5
V5
V2
V2
V1
V6
V6
COM
X2
V6
V5
V5
V5
V2
V1
V1
V6
V6
X64 V5
V5
V2
V1
V1
V3
Y1
V4
V4
V2
SEG
V1
Y64 V4
V1
V3
Selected
V4
V2
Non-selected
The waveforms of Y1 to Y64 outputs vary with the display data. In this example, the top line of
the panel lights up and other dots do not.
Figure 6 LCD Driver Timing Chart (1/64 Duty Cycle)
837
HD61202U
Interface with CPU
1. Example of Connection with H8/536/S
Decoder
A15
to
A1
AS
VCC
A
R/W
CS1
CS2
CS3
D/I
R/W
H8/536S
HD61202U
E
E
D0
to
D7
DB0
to
DB7
VCC
RES
RST
Figure 7 Example of Connection with H8/536S
838
HD61202U
2. Example of Connection with HD6801
• Set HD6801 to mode 5. P10 to P14 are used as the output port and P30 to P37 as the data bus.
• 74LS154 4-to-16 decoder generates chip select signal to make specified HD61202U active after
decoding 4 bits of P10 to P13.
• Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write
from/to the external memory area ($0100 to $01FE) to control HD61202U. In this case, IOS signal is
output from SC1 and R/W signal from SC2.
• For details of HD6800 and HD6801, refer to their manuals.
74LS154
P10
P11
P12
P13
(IOS) (SC1)
(R/W) (SC2)
HD6801
P14
E
A
Y0
B
Y1
C
Y15
D
G1 G2
VCC
CS1
CS2
CS3
R/W
D/I
HD61202U
No. 1
E
P30
DB0
(Data bus)
P37
DB7
Figure 8 Examples of Connection with HD6801
839
HD61202U
Example of Application
In this example, two HD61203s output the equivalent waveforms. So, stand-alone operation is possible.
In this case, connect COM1 and COM65 to X1, COM2 and COM66 to X2, ..., and COM64 and COM128
to X64. However, for the large screen display, it is better to drive in 2 rows as in this example to
guarantee the display quality.
HD61202U
HD61202U
No. 9
No. 10
Y1
Y64 Y1
Y64
HD61202U
No. 16
Y1
Y32
HD61203U
(slave)
HD61203U
(master)
COM1
COM2
COM3
X1
X2
X3
X64
COM64
X1
X2
X3
COM65
COM66
COM67
LCD panel
128 × 480 dots
X64
COM128
Y1
Y64
HD61202U
No. 1
Y1
Y64
HD61202U
No. 2
Figure 9 Application Example
840
Y1
Y32
HD61202U
No. 8
HD61202U
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Supply voltage
VCC
–0.3 to +7.0
V
2
VEE1
VEE2
VCC – 17.0 to VCC + 0.3
V
3
Terminal voltage (1)
VT1
VEE – 0.3 to VCC + 0.3
V
4
Terminal voltage (2)
VT2
–0.3 to VCC + 0.3
V
2, 5
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. LSIs may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended operation conditions.
Useing them beyond these conditions may cause malfunction and poor reliability.
2. All voltage values are referenced to GND = 0V.
3. Apply the same supply voltage to VEE1 and VEE2.
4. Applies to V1L, V2L, V3L, V4L, V1R, V2R, V3R, and V4R.
Maintain
VCC ≥ V1L = V1R ≥ V3L = V3R ≥ V4L = V4R ≥ V2L = V2R ≥ VEE
5. Applies to M, FRM, CL, 567, ADC, ø1, ø2, &6, &6, CS3, E, R/W, D/I, and DB0–DB7.
841
HD61202U
Electrical Characteristics (GND = 0V, VCC = 2.7 ~ 5.5V, VCC − VEE = 8.0 to 16.0V,
Ta = −20 ~ +75°C)
Limit
Item
Symbol
Min
Typ
Max
Unit
Test Condition
Notes
Input high voltage
VIHC
0.7VCC
—
VCC
V
VCC = 2.7V~5.5V
1
VIHT
0.7VCC
—
VCC
V
VCC = 2.7V~4.5V
2
2.0
—
VCC
V
VCC = 4.5V~5.5V
2
0.3VCC
V
VCC = 2.7V~5.5V
1
—
0.5
V
VCC = 2.7V~4.5V
2
0.8
V
VCC = 4.5V~5.5V
2
Input low voltage
VILC
0.0
VILT
0.0
0.0
Output high voltage
Output low voltage
VOH
VOL
0.75VCC
—
—
V
IOH = –100 µA,
VCC = 2.7V~4.5V
3
2.4
—
—
V
IOH = –205 µA
VCC = 4.5V~5.5V
3
0.2VCC
V
IOL = 100 uA,
VCC = 2.7V~4.5V
3
—
—
—
0.4
V
IOL = 1.2mA,
VCC = 4.5V~5.5V
3
Input leakage current IIL
–1
—
1
µA
Vin = GND ~ VCC
4
Three-state (off)
input current
ITSL
–5
—
5
µA
Vin = GND ~ VCC
5
Liquid crystal supply
leakage current
ILSL
–2
—
2
µA
Vin = VEE–VCC
6
Driver on resistance
RON
—
—
7.5
kΩ
±ILOAD = 0.1 mA,
VCC–VEE = 15V
8
Dissipation current
ICC (1)
—
—
100
µA
During display
7
ICC (2)
—
—
500
µA
During access,
Cycle = 1MHz
7
Notes: 1.
2.
3.
4.
5.
6.
7.
842
Applies to M, FRM, CL, RST, ø1, and ø2.
Applies to CS1, CS2, CS3, E, R/W, D/I, and DB0–DB7.
Applies to DB0–DB7.
Applies to terminals except for DB0–DB7.
Applies to DB0–DB7 at high impedance.
Applies to V1L–V4L and V1R–V4R.
Specified when LCD is in 1/64 duty cycle mode.
Operation frequency:
fCLK = 250 kHz (ø1 and ø2 frequency)
Frame frequency: fM = 70 Hz (FRM frequency)
Specified in the state of
Output terminal: Not loaded
Input level:
VIH = VCC (V)
VIL = GND (V)
Measured at VCC terminal
HD61202U
8. Resistance between terminal Y and terminal V (one of V1L, V1R, V2L, V2R, V3L, V3R, V4L,
and V4R) when load current flows through one of the terminals Y1 to Y64. This value is
specified under the following condition:
VCC–VEE = 15.0V
V1L = V1R, V3L = V3R = VCC–2/7 (VCC–VEE)
V2L = V2R, V4L = V4R = VCC+2/7 (VCC–VEE)
RON
V1L, V1R
V3L, V3R
Terminal Y
(Y1–Y64)
V4L, V4R
V2L, V2R
The following is a description of the range of power supply voltage for liquid crystal display
drive. Apply positive voltage to V1L = V1R and V3L = V3R and negative voltage to V2L = V2R
and V4L = V4R within the ÆV range. This range allows stable impedance on driver output
(RON). Notice that ÆV depends on power supply voltage VCC–VEE.
VCC
V1 (V1L = V1R)
Range of power supply
voltage for liquid crystal
display drive
V3 (V3L = V3R)
∆V (V)
∆V
5.0
3
∆V
V4 (V4L = V4R)
V2 (V2L = V2R)
VEE
8
16
VCC–VEE (V)
Correlation between driver output
waveform and power supply voltages
for liquid crystal display drive
Correlation between power supply
voltage VCC–VEE and ∆V
843
HD61202U
Terminal Configuration
Input Terminal
VCC
PMOS
Applicable terminals:
M, FRM, CL, RST, ø1, ø2, CS1, CS2, CS3,
E, R/W, D/I, ADC
NMOS
Input/Output Terminal
Applicable terminals: DB0–DB7
VCC
(Input circuit)
PMOS
VCC
Enable
NMOS
PMOS
Data
NMOS
(Output circuit)
[three state]
Output Terminal
PMOS
Applicable terminals:
Y1–Y64
V1L, V1R
VCC
PMOS
V3L, V3R
VCC
NMOS
V4L, V4R
VEE
NMOS
VEE
844
V2L, V2R
HD61202U
Interface AC Characteristics
MPU Interface (GND = 0V, VCC = 2.7 to 5.5V, Ta = –20 to +75°C)
Item
Symbol
Min
Typ
Max
Unit
Note
E cycle time
tCYC
1000
—
—
ns
Fig. 10, Fig. 11
E high level width
PWEH
450
—
—
ns
E low level width
PWEL
450
—
—
ns
E rise time
tr
—
—
25
ns
E fall time
tf
—
—
25
ns
Address setup time
tAS
140
—
—
ns
Address hold time
tAH
10
—
—
ns
Data setup time
tDSW
200
—
—
ns
Fig. 10
Data delay time
tDDR
—
—
320
ns
Fig. 11, Fig. 12
Data hold time (write)
tDHW
10
—
—
ns
Fig. 10
Data hold time (read)
tDHR
20
—
—
ns
Fig. 11
tCYC
E
VIHT
VILT
PWEL
PWEH
tf
tAH
tr
R/W
VIHT
VILT
tAS
tAS
CS1–CS3
D/I
tAH
VIHT
VILT
tDSW
DB0–DB7
tDHW
VIHT
VILT
Figure 10 MPU Write Timing
845
HD61202U
tCYC
PWEL
E
PWEH
tf
tr
VIHT
VILT
R/W
tAS
tAH
tAH
tAS
VIHT
VILT
CS1–CS3
D/I
tDDR
tDHR
VIHT
VILT
DB0–DB7
Figure 11 MPU Read Timing
VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
VCC = 5V
D1
2.4kΩ
Test point
90pF
Test point
11kΩ
Diodes
IS2074 H
Notes) including jip capacitance
Figure 12 DB0–DB7: Load Circuit
846
50pF
HD61202U
Clock Timing (GND = 0V, VCC = 2.7 to 5.5V, Ta = –20 to +75°C)
Limit
Item
Symbol
Min
Typ
Max
Unit
Test Condition
ø1, ø2 cycle time
tcyc
2.5
—
20
µs
Fig. 13
ø1 low level width
tWLø1
625
—
—
ns
ø2 low level width
tWLø2
625
—
—
ns
ø1 high level width
tWHø1
1875
—
—
ns
ø2 high level width
tWHø2
1875
—
—
ns
ø1–ø2 phase difference
tD12
625
—
—
ns
ø2–ø1 phase difference
tD21
625
—
—
ns
ø1, ø2 rise time
tr
—
—
150
ns
ø1, ø2 fall time
tf
—
—
150
ns
tcyc
tf
ø1
VIHC
VILC
tWLø1
ø2
tWHø1
tr
tD12
tD21
VIHC
tWHø2
VILC
tf
tWLø2
tr
tcyc
Figure 13 External Clock Waveform
847
HD61202U
Display Control Timing (GND = 0V, VCC = 2.7 to 5.5V, Ta = –20 to +75°C)
Limit
Item
Symbol
Min
Typ
Max
Unit
Test Condition
FRM delay time
tDFRM
–2
—
+2
µs
Fig. 14
M delay time
tDM
–2
—
+2
µs
CL low level width
tWLCL
35
—
—
µs
CL high level width
tWHCL
35
—
—
µs
CL
VIHC
VILC
tDFRM
FRM
tWLCL
tWHCL
tDFRM
VIHC
VILC
tDM
M
VIHC
VILC
Figure 14 Display Control Signal Waveform
848
Similar pages