TOSHIBA TC9447F

TC9447F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9447F
Single-Chip Audio Digital Signal Processor
The TC9447F is a single-chip audio digital signal processor
incorporating an AD/DA converter. The built-in program memory
(ROM) can contain a range of application programs for concert
hall acoustic field simulation, for digital filters such as equalizers,
and for dynamic range control. In addition, the device includes
64kb of data delay RAM, making external RAM unnecessary.
Features
·
Incorporates a 1-bit Σ∆-type AD converter (two channels).
·
Incorporates a 1-bit Σ∆-type DA converter (four channels).
·
A ±10-dB attenuator is built into the DA converter output block (two channels only)
·
Each port has a digital input/output (three lead-type)
·
A built-in self-boot function automatically sets the coefficients and register values at initialization.
·
The DSP block specifications are as follows:
THD: −82dB, S/N ratio: 95dB (typ.)
Weight: 1.57g (typ.)
THD: −85dB, S/N ratio: 100dB (typ.)
Boot ROM
: 1024 words × 18 bits
Data bus
: 24 bits
Multiplier/adder
: 24 bits × 16 bits + 43 bits → 43 bits
Accumulator
: 43 bits (sign extension: 4 bits)
Program ROM
: 1024 words × 32 bits
Coefficient RAM
: 320 words × 16 bits
Coefficient ROM
: 256 words × 16 bits
Offset RAM
: 64 words × 16 bits
Data RAM
: 256 words × 24 bits
Operation speed
: 44ns (510-step (approx) operation per cycle at fs = 44.1 kHz)
Interface buffer RAM : 32 words × 16 bits
·
Incorporates data delay RAM.
Delay RAM
: 4096 words × 16 bits (64 kbits)
·
The microcontroller interface can be selected between Standard Transmission mode and I2C bus mode.
·
CMOS silicon structure supports high speed.
·
The package is a 100-pin flat package.
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Pin Connection
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TC9447F
TC9447F
Block Diagram
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TC9447F
Pin Function
Pin
No.
Symbol
I/O
1
ECKO
O
Amp output pin for external clock input
2
ECKI
I
Amp input pin for external clock input
3
GNDX
―
Ground pin for oscillator circuit
4
GNDAL
―
Ground pin for DAC L channel
5
AOL
O
DAC analog signal output pin (L channel)
6
VRL
―
DAC reference voltage pin (L channel)
7
VDAL
―
Power pin for DAC L channel
8
VDAR
―
Power pin for DAC R channel
9
VRR
―
DAC reference voltage pin (R channel)
10
AOR
O
DAC analog signal output pin (R channel)
11
GNDAR
―
Ground pin for DAC R channel
12
GNDAC
―
Ground pin for DAC C channel
13
AOC
O
DAC analog signal output pin (C channel)
14
AOCT
O
DAC analog signal output pin with attenuator (C channel)
15
VRC
―
DAC reference voltage pin (C channel)
16
VDAC
―
Power pin for DAC C channel
17
VRO
O
Reference voltage pin for attenuator (buffer output)
18
VRI
I
Reference voltage pin for attenuator (buffer input)
19
VDAS
―
Power pin for DAC S channel
20
VRS
―
DAC reference voltage pin (S channel)
21
AOST
O
DAC analog signal output pin with attenuator (S channel)
22
AOS
O
DAC analog signal output pin (S channel)
23
GNDAS
―
Ground pin for DAC S channel
24
GND
―
Ground pin
25~29
TP0~TP4
O
Test pins (leave open)
30
VDD
―
Power pin
31
VDDR
―
Power pin for DLRAM
Function
32
GNDR
―
Ground pin for DLRAM
33~40
TP5~TP12
O
Test pins (leave open)
41
FS
O
Clock output pin (1 fs)
42
CKO0
O
Clock output pin 0
43
CKO1
O
Clock output pin 1
44
GND
―
Ground pin
45
TP13
O
Test pin (leave open)
46
MCK
O
MCK clock output pin (256 fs/512 fs/ (384/768 fs) )
47
VDD
―
Power pin
O
Test pin (leave open)
48~53 TP14~TP19
Remarks
Pulled-down resistor
(with on/off switching
function)
Push-pull output
54
CKS
I
Master clock switching pin
Schmitt input
55
STEP0
I
Execution step switching pin 0
Schmitt input
56
STEP1
I
Execution step switching pin 1
Schmitt input
57
RST
I
Reset pin
Schmitt input
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TC9447F
Pin
No.
Symbol
I/O
58
VDD
―
59
SYNC
I
Program SYNC signal input pin
Schmitt input
60
ELRO
I
LR clock input pin for serial data output
Schmitt input
Function
Remarks
Power pin
61
ELRI
I
LR clock input pin for serial data input
Schmitt input
62
EBCO
I
Bit clock input pin for serial data output
Schmitt input
63
EBCI
I
Bit clock input pin for serial data input
Schmitt input
64
DIN
I
Serial data input pin
Schmitt input
65
DOUT
O
Serial data output pin
Push-pull output
66
EM0
I
De-emphasis setting pin 0
Schmitt input
67
EM1
I
De-emphasis setting pin 1
Schmitt input
68
IFF0
I
Interface flag pin 0
Schmitt input
69
IFF1
I
Interface flag pin 1
Schmitt input
70
IFF2
I
Interface flag pin 2
Schmitt input
71
GND
―
72
CS
I
Microcontroller interface chip select signal input pin
Schmitt input
73
IFCK
I
Microcontroller interface data shift clock input pin
Schmitt input
74
IFDI
I/O
Microcontroller interface data2input pin
(Data input/output pin when I C bus selected)
Schmitt input/
open drain output
75
IFDO
O
Microcontroller interface
data output pin
2
(Leave open when I C bus selected.)
Push-pull output
76
IFOK
O
Microcontroller interface operation flag output pin
Open drain output
77
ACK
O
Microcontroller interface acknowledge output pin
Open drain output
78
ERR
O
Microcontroller interface error flag output pin
Open drain output
2
Ground pin
2
79
I CS
I
Microcontroller interface I C bus switching pin
80
BOOT
I
Self-boot control pin
Schmitt input
81
BA0
I
Boot address setting pin 0
Schmitt input
82
BA1
I
Boot address setting pin 1
Schmitt input
83
VDD
―
84~87 TST0~TST3
I
Power pin
Test pins. Use fixed to low level.
Schmitt input
88
GND
―
Ground pin
89
VSAL
―
Ground pin for analog mode (ADC L channel)
90
LIN
I
ADC analog signal input pin (L channel)
91
AVRL
―
ADC reference voltage pin (L channel)
92
VDL
―
Power pin for analog mode (ADC L channel)
93
VDR
―
Power pin for analog mode (ADC R channel)
94
AVRR
―
ADC reference voltage pin (R channel)
95
RIN
I
ADC analog signal input pin (R channel)
96
VSAR
―
Ground pin for analog mode (ADC R channel)
97
GNDX
―
Ground pin for oscillator circuit
98
XI
I
Crystal oscillator connecting pin (input)
99
XO
O
Crystal oscillator connecting pin (output)
100
VDX
―
Power pin for oscillator circuit
5
Pulled-down resistor
(with on/off switching
function)
2002-02-05
TC9447F
Operation
1. Pin operations
Pin
No.
Symbol
1
ECKO
2
ECKI
3~24
Omitted
25~40
TP [0:12]
41
FS
Function
Supplies an external clock to ECKI (for slave operations).
When CKS pin = H, oscillation activated. When CKS = L, pulled down internally.
―
Test pins (leave open) (TPx description is omitted.)
1 fs output
Timing output pins. The output frequency is set from the microcontroller. (CMD-40h)
CKOS0
2
1
0
0
42, 43
1
CKO [1:0]
0
1
1
CKOS1
CKO0
0
2
0
Fixed to L (initial value)
1
fs2
0
fs4
1
fs8
0
fs16
1
fs32
0
fs64
1
fs128
1
0
0
1
0
1
1
CKO1
0
0
Fixed to L (initial value)
1
fs2
0
fs4
1
fs8
0
fs16
1
fs32
0
fs64
1
1/2 XI or 1/2 ECKI
Master clock output pin. Output is validated/invalidated and the frequency is switched from the
microcontroller. (CMD-4Dh)
MCKE
46
MCK
MCK
MCKE
0
Fixed to L
0
1
Output valid (initial value)
STEP1
MCK
don't care 256 fs
1
0
Source oscillation (XI/XO or ECKI)
1
For testing
Source oscillation selector pin
CKS
54
CKS
Source Oscillation
0
XI/XO pin
1
ECKI/ECKO pin
Source oscillation frequency/ASP operation speed switching pins
STEP1 STEP0
55, 56
STEP [1:0]
0
1
Source Oscillation Frequency
No. of ASP Operation Steps
0
512 fs
340/fs
1
768 fs
510/fs
*
For testing
*: don't care
57
RST
Reset input (L at initialization)
59
SYNC
Program operation SYNC signal input pin. Valid when program is executing a slave operation.
60
ELRO
LR clock signal input pin for serial output data. Valid when serial data are output in a slave operation.
61
ELRI
LR clock signal input pin for serial input data. Valid when serial data are input in a slave operation.
62
EBCO
Bit clock signal input pin for serial output data. Valid when serial data are output in a slave operation.
63
EBCI
Bit clock signal input pin for serial input data. Valid when serial data are input in a slave operation.
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TC9447F
Pin
No.
Symbol
64
DIN
65
DOUT
Function
Serial input data signal input pin. Normally connected to internal register SI2 in ASP block.
Serial output data signal output pin. Normally connected to internal register SO2 in ASP block.
De-emphasis control pins
EM1
66, 67
0
EM [1:0]
1
68~70
IFF [2:0]
72
CS
73
IFCK
74
IFDI
75
IFDO
76
IFOK
77
ACK
78
ERR
79
2
I CS
EM0
De-Emphasis Settings
0
De-emphasis off
1
For fs = 48 kHz
0
For fs = 44.1 kHz
1
For fs = 32 kHz
IFF control input pins. This functions the same as the microcontroller IFF [2:0] setting.
The program uses the latest changes to the flags.
Microcontroller interface pins
2
2
Standard Transmission Mode (I CS = L)
2
I CS
CS
2
I C Mode (I CS = H)
2
Transmit/receive mode switching (Standard Transmission mode/I C mode)
Chip select (Control required)
Chip select (Can be fixed to L)
IFCK
Transmit/receive clock
IFDI
MCU data input
MCU data input/output
IFDO
Monitor data output
Fixed to L output
ACK
Acknowledge signal output
Fixed to HZ
ERR
Error flag signal output
IFOK
Internal operation confirmation flag signal output
For details, see 2, microcontroller interface below.
Self-boot select pin
BOOT
80
BOOT
Operation
0
Does not boot at reset
1
Boot at reset
Self-boot start address pins (at reset)
BA1
81, 82
BA [1:0]
0
1
84~87
TST [3:0]
88~97
Omitted
98
XI
99
XO
BA0
Start Address
0
000h
1
001h
0
002h
1
003h
Pins for inputting test settings. Use fixed to L.
―
Connect the crystal oscillator (master mode).
Setting CKS = L enables oscillation. Setting CKS = H pulls down XI/XO using the internal resistor.
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TC9447F
2. Microcontroller interface
(1)
Standard transmission mode 1
When I2CS = L, data can be transmitted or received in Standard Transmission mode.
When the CS signal is Low, control from the microcontroller is enabled.
The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the
IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care.
(1-1)
Setting registers
The registers are set by command data using the IFDI signal. The first byte is a command, which
differs for each register. The data sent after that are fixed to two bytes. Both command and data
are sent starting from the MSB.
The ACK signal is the acknowledge signal that the TC9447F returns to the microcontroller.
Because the ACK signal is open drain output, it must be pulled up outside the pin. Data are
loaded on the rising edge of the IFCK signal.
Note that commands or data that must be switched on the SYNC signal, such as the RUN
command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
(1-2)
Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal. The first byte is a command, which
differs for each RAM. The next two bytes contain the start address for the RAM written.
The length of the data field following the RAM address bytes is 2 × n bytes. The address is
automatically incremented by 1.
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TC9447F
(1-3)
Setting RAM (ACMP mode)
In ACMP mode, the TC9447F does not write data directly to coefficient RAM (CRAM) or offset
RAM (OFRAM). In this mode, data must first be written to the interface buffer RAM (IFB-RAM).
Then, all the data are updated together in a period of 1 fs.
For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5
data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data.
Using ACMP mode can reduce the noise caused by updating coefficients while the TC9447F is
operating. This mode can suppress noise in almost all cases.
IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32
words.
The format of IFB-RAM is similar to the format of the RAM in 1-2 above. The length of the data
field is 2 × n bytes, where n ≤ 32.
In ACMP mode, the IFOK pin outputs an ACMP operation end flag.
When ACMP operations complete, the flag is set to Low (1) and is initialized at the next low chip
select CS signal (2).
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TC9447F
(1-4)
Monitor mode
Monitor mode is used to monitor the data bus or pointers.
There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset
program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in
addition to the PC. After the command is issued, when the TC9447F loads data to the IFDO
register (IFDOR), the IFOK pin signal is set to Low (see (1) above).
Next, when the IFCK signal is sent, the data are output on the IFCK signal falling edge starting
from the MSB. The data length is at its maximum (24 bits or three bytes) during monitoring of
the data bus. In cases where transfer must be interrupted, such as where only eight or 16 bits of
the MSB side are required, monitoring can be interrupted at any time by setting the CS signal
to High. When the CS signal goes High, the IFOK signal also goes High.
When CS = H, all monitor circuits are initialized.
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TC9447F
(2)
Standard transmission mode 2
When I2CS = L, data can be transmitted or received in Standard Transmission mode.
When the CS signal is Low, control from the microcontroller is enabled.
The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the
IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care.
(2-1)
Setting registers
The registers are set by command data using the IFDI signal. The first byte is a command, which
differs for each register. The data sent after that are fixed to two bytes. Both command and data
are sent starting from the MSB.
The ACK signal is the acknowledge signal that the TC9447F returns to the microcontroller. As
the ACK signal is open drain output, it must be pulled up outside the pin. The data are loaded
on the rising edge of the IFCK signal.
Note that commands or data that must be switched on the SYNC signal, such as the RUN
command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
(2-2)
Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal. The first byte is a command, which
differs for each RAM. The next two bytes contain the start address for the RAM written.
The length of the data field following the RAM address bytes is 2 × n bytes. The address is
automatically incremented by 1.
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TC9447F
(2-3)
Setting RAM (ACMP mode)
In ACMP mode, the TC9447F does not write data directly to coefficient RAM (CRAM) or offset
RAM (OFRAM). In this mode, data must first be written to the interface buffer RAM (IFB-RAM).
Then, all the data are updated together in a period of 1 fs.
For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5
data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data.
Using ACMP mode can reduce the noise caused by updating coefficients while the TC9447F is
operating. This mode can suppress noise in almost all cases.
IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32
words. The format of IFB-RAM is similar to the format of the RAM in 2-2 above. The length of the
data field is 2 × n bytes, where n ≤ 32.
In ACMP mode, the IFOK pin outputs an ACMP operation end flag.
When ACMP operations complete, the flag is set to Low (1) and is initialized at the next low chip
select CS signal (2).
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TC9447F
(2-4)
Monitor mode
Monitor mode is used to monitor the data bus or pointers.
There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset
program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in
addition to the PC. After the command is issued, when the TC9447F loads data to the IFDO
register (IFDOR), the IFOK pin signal is set to Low (see (1) above).
Next, when the IFCK signal is sent, data are output on the IFCK signal falling edge from the
MSB first. The data length is at its maximum (24 bits or three bytes) during monitoring of the
data bus. In cases where transfer must be interrupted, such as where only eight or 16 bits of the
MSB side are required, monitoring can be interrupted at any time by setting the CS signal to
High. When the CS signal goes High, the IFOK signal also goes High.
When CS = H, all monitor circuits are initialized.
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TC9447F
(3)
I2C bus mode
When I2CS = H, data can be transmitted or received in Standard Transmission mode.
When the CS signal is Low, control from the microcontroller is enabled.
In I2C mode, the CS signal can be used fixed to L.
The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the
IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care.
(3-1)
Setting registers
The registers are set by command data using the IFDI signal. The first byte after the I2C address
(32h) is a command, which differs for each register. The data sent after that are fixed to two bytes.
Both command and data are sent starting from the MSB in I2C format.
The ACK pin cannot be used in I2C format. However, the acknowledge signal can be read by
using data signals in I2C format. The data are loaded internally every two bytes.
Note that commands or data that must be switched on the SYNC signal, such as the RUN
command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
(3-2)
Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal.
The first byte after the I2C address (32h) is a command, which differs for each RAM. The next two
bytes contain the start address for the RAM to be written to. The length of the data field following
the RAM address bytes is 2 × n bytes. The address is automatically incremented by 1.
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TC9447F
(3-3)
Monitor mode
Monitor mode is used to monitor the data bus or pointers.
There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset
program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in
addition to the PC.
First, issue the monitoring command, which has no data.
When the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low
(see (1) above).
Next, the I2C read command (ID = 33h) is issued, then when the IFCK signal is sent, the data are
output on the IFCK signal falling edge starting from the MSB. The data length is at its maximum
(24 bits or three bytes) during monitoring of the data bus. In cases where transfer must be
interrupted, such as where only eight or 16 bits of the MSB side are required, monitoring can be
interrupted by sending the I2C end condition (set data level to H while the clock = H).
After issuing a monitor command (50h~56h), be sure to perform a continuous read operation by
issuing the I2C read command (ID = 33h).
(3-4)
MCU does not write data by ACMP mode at I2C bus controlling.
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TC9447F
(4)
IFOK pin description
The IFOK signal has the following three functions.
(4-1)
ACMP mode end flag output
After the completion of a RAM data update with CRAM-ACMP (CMD: 47h) or OFRAM-ACMP
(CMD: 49h), the IFOK pin goes Low. Setting the CS signal to Low changes the IFOK signal
from Low to High.
Example:
(4-2)
Loading end flag output in Monitor mode
When monitoring using the bus monitor command (CMD: 50h), for example, after data are loaded
to the internal register under the specified conditions, the IFOK signal goes Low. In monitor
mode, when the CS signal goes High, the IFOK signal also goes High.
Example:
(4-3)
Mute end flag output for digital filter (DF) block
When using a command to control the DF block mute on/off (CMD: 36h, bit 5), the mute end flag
is output from the IFOK pin after the mute operation completes.
Example:
Note 1: At power on, the IFOK pin output is undefined. When the CS signal goes Low, the
IFOK signal goes High.
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TC9447F
3. Control commands
The following table lists the control commands that can be used from the microcontroller.
(1)
Control commands
Table 1 Control commands
Command
Code
R/W
Description
RAM
Sequential
Transfer Sync With/Async to
Sync Signal
TIMING
40h
Timing
―
Async
BOOT
41h
Self-boot ROM start address
―
Async
DAC
42h
DAC output attenuator
―
Async
SIO
43h
SIO setting
―
Async
RUN-MUTE
44h
Program execution, mute
―
Sync
MSEQ
45h
Sequential RAM
Sync (RUN)/Async (STOP)
CRAM
46h
CRAM
Sync (RUN)/Async (STOP)
CRAM-ACMP
47h
OFRAM
48h
OFRAM-ACMP
49h
OFRAM (ACMP mode)
IFF
4Ah
Interface flag (IFF)
―
Sync
MONI-PC
4Bh
Monitor (PC conditions)
―
Async
MONI-LC
4Ch
Monitor (LC conditions)
―
Async
MISC
4Dh
Others
―
Async
4Eh
(Prohibited)
―
―
―
W
CRAM (ACMP mode)
Enable
OFRAM
Async
Sync (RUN)/Async (STOP)
Async
M-RST
4Fh
Initialization
―
Async
MONI-DB
50h
DB monitor
―
Async
MONI-CP
51h
CP monitor
―
Async
MONI-OFP
52h
OFP monitor
―
Async
MONI-DP
53h
DP monitor
―
Async
MONI-AR
54h
AR monitor
―
Async
MONI-CRP
55h
CRP monitor
―
Async
MONI-SR
56h
SR monitor
―
Async
R
(Note 2)
(Note 2)
Note 2: The command which is "Sync" in the transfer Sync with Sync signal needs to set the CS = H
section to a minimum of 1 fs more until it transmits the following command.(It needs more than
22.68 µs at fs = 44.1 kHz)
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TC9447F
(2)
Control commands
COMMAND-40h
(Timing)
D15
D14
0100 0000
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Unas- CKOS1 CKOS1 CKOS1 CKOS0 CKOS0 CKOS0
SYPD SYD1 SYD0 SYPA SYA1 SYA0 SYPS SYS1 SYS0 signed
2
1
0
2
1
0
Name
Description
SYPD Digital block sync polarity switching
SYD
[1:0]
ASP digital block SYNC signal input
switching
SYPA Analog block sync polarity switching
SYA
[1:0]
Analog block SYNC signal input
switching
SYPS Overall system sync polarity switching
SYS
[1:0]
SYNC circuit input switching
CKOS1
CKO1 pin output selection
[2:0]
CKOS0
CKO0 pin output selection
[2:0]
Value
Operation
0
ASP program starts on falling edge
1
ASP program starts on rising edge (initial value)
0
Signal after SYNC output (initial value)
1
SYNC pin
2
ELRI pin
3
ELRO pin
0
Digital filter (DF) program starts on falling edge (initial value)
1
Digital filter (DF) program starts on rising edge
0
Signal after SYNC output (initial value)
1
SYNC pin
2
ELRI pin
3
ELRO pin
0
Operates at polarity for SYPD, SYPA settings above (initial value).
1
Reverses all polarities for SYPD, SYPA settings above.
0
Internal SYNC signal (initial value)
1
SYNC pin
2
ELRI pin
3
ELRO pin
0
Fixed to L (initial value)
1
fs2
2
fs4
3
fs8
4
fs16
5
fs32
6
fs64
7
Outputs XI or ECKI clock divided by 2
0
Fixed to L (initial value)
1
fs2
2
fs4
3
fs8
4
fs16
5
fs32
6
fs64
7
fs128
18
2002-02-05
TC9447F
COMMAND-41h
(BOOT)
0100 0001
D15
D14
D13
D12
D11
D10
0
0
0
0
0
0
Name
BTA
[9:0]
Description
BTA9 BTA8
D7
D6
BTA7 BTA6
D5
D4
D3
BTA5
BTA4
BTA3
D2
D1
BTA2 BTA1
D0
BTA0
Operation
000h
~
Starts self-boot operation from specified address.
3FFh
0100 0010
D15
D14
D13
0
0
0
Name
D8
Value
Self-boot ROM start address
COMMAND-42h
(DAC)
D9
D12
D11
D10
D9
D8
ATTC4 ATTC3 ATTC2 ATTC1 ATTC0
Description
Value
D7
D6
D5
0
0
0
D4
D3
D2
D1
D0
ATTS4 ATTS3 ATTS2 ATTS1 ATTS0
Operation
ATTC DAC C channel attenuator value
00h
~
1Fh
00h → 0dB, 01h = −1dB, 02h = −2dB, …, 15h~1Fh = −∞
(Initial value = 1Fh=－∞)
ATTS DAC S channel attenuator value
00h
~
1Fh
00h → 0dB, 01h = −1dB, 02h = −2dB, …, 15h~1Fh = −∞
(Initial value = 1Fh = −∞)
19
2002-02-05
TC9447F
COMMAND-43h
(SIO)
D15
CHSI
Name
0100 0011
D14
D13
D12
D11
D10
D9
0
ISLT
1
ISLT
2
IBCS
1
IBCS
0
IFMT
1
IFMT CHSO CHSO OSLT OSLT OBCS OBCS OFMT OFMT
0
1
0
1
0
1
0
1
0
Value
Operation
Description
CHSI Serial input switching
ISLT
[1:0]
Number of serial input slots
IBCS
Serial input bit length
[1:0]
IFMT
Serial input format
[1:0]
OBCS
Serial output bit length
[1:0]
OFMT
Serial output format
[1:0]
D6
D5
D4
D3
D2
D1
ADC → SI0 register, DIN pin → SI1 register (initial value)
1
ADC → SI1 register, DIN pin → SI0 register
0
16 bits/channel (initial value)
1
20 bits/channel
2
24 bits/channel
3
32 bits/channel
0
16 bits (initial value)
1
18 bits
2
20 bits
3
24 bits
0
Pads from the beginning (initial value)
1
Pads from the end
2
2
SO0 register → DOUT pin
1
SO1 register → DOUT pin
2
SO2 register → DOUT pin (initial value = 2)
0
16 bits/channel (initial value)
1
20 bits/channel
2
24 bits/channel
3
32 bits/channel
0
16 bits (initial value)
1
18 bits
2
20 bits
3
24 bits
0
Pads from the beginning (initial value)
1
Pads from the end
2
3
D0
I S format
0
3
OSLT
Number of serial output slots
[1:0]
D7
0
3
CHSO
Serial output switching
[1:0]
D8
2
I S format
20
2002-02-05
TC9447F
COMMAND-44h
(RUN-MUTE)
D15
0
D14
0
0100 0100
D13
D12
0
0
Name
D11
0
D10
0
Description
D9
0
D8
0
D7
RUN
D6
0
D5
Value
Stops program (initial value).
1
Runs program.
DF
DF block mute
MUTE
0
Mute off
1
Mute on (initial value)
DA
DAC mute (all four channels)
MUTE
0
Mute off
1
Mute on (initial value)
0
Mute off
1
Mute on (initial value)
0
Mute off
1
Mute on (initial value)
0
Mute off
1
Mute on (initial value)
0
Mute off
1
Mute on (initial value)
ASP program execution
IMUTE ASP block input mute (SI0, SI1)
ASP block serial output mute (Mutes
SODOUT output whichever register is
MUTE
selected in CHSO.)
OMUTE
ASP block output mute (SO1)
1
OMUTE
ASP block output mute (SO0)
0
COMMAND-45h
(MSEQ)
D3
D2
D1
D0
Operation
0
RUN
D4
DF
DA
SO- OMUTE OMUTE
MUTE MUTE IMUTE MUTE
1
0
0100 0101
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Name
Description
MSA
[9:0]
Sequential RAM address
COMMAND-46h
(MSEQ)
Value
Operation
000h
Set sequential RAM.
~
Enable a sequential write to RAM.
3FFh
0100 0110
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
D
CRAM
[15:0]
Description
Value
Operation
0000h
Set CRAM.
~
Enable a sequential write to RAM.
FFFFh
21
2002-02-05
TC9447F
COMMAND-47h
(CRAM-ACMP)
0100 0111
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Description
Value
0000h
~
Set CRAM in ACMP mode.
FFFFh
D
CRAM-ACMP
[15:0]
COMMAND-48h
(OFRAM)
Operation
0100 1000
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Description
Value
Operation
0000h
Set OFRAM.
~
Enable a sequential write to RAM.
FFFFh
D
OFRAM
[15:0]
COMMAND-49h
(OFRAM-ACMP)
0100 1001
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Description
Value
0000h
~
Set OFRAM in ACMP mode.
FFFFh
D
OFRAM-ACMP
[15:0]
COMMAND-4Ah
(IFF)
Operation
0100 1010
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
IFF2
IFF1
IFF0
Name
IFF
[2:0]
Description
Interface flag (IFF)
Value
Operation
0
IFFn = 0 (initial value)
1
IFFn = 1
22
2002-02-05
TC9447F
COMMAND-4Bh
(MONI-PC)
D15
D14
0100 1011
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I2COS I2COS
1
0
Name
Description
Value
0h
~
3h
2
I2COS
Monitor data length in I C mode
[1:0]
A
[9:0]
0100 1100
D15
D14
D13
D12
D11
D10
D9
0
0
0
0
0
LCE
LCS
Name
Description
LCE
Adds the LC (loop counter) value to
the monitor conditions.
LCS
LC selection
LCDE Automatic LC decrement
LCA
[7:0]
2
Set the data byte length when monitoring in I C mode.
(3 = 3 byte, 2 = 2 byte, 1 or 0 = 1 byte)
000h
~
Set the PC conditions when monitoring.
3FFh
Monitor conditions
(PC: program counter)
COMMAND-4Ch
(MONI-LC)
Operation
Monitor conditions (LC)
D8
D7
LCDE LCA7
D6
D5
D4
D3
D2
D1
D0
LCA6
LCA5
LCA4
LCA3
LCA2
LCA1
LCA0
Value
Operation
0
Does not add LC value to the conditions (initial value).
1
Adds LC value to the conditions.
0
Compares with LC0 value.
1
Compares with LC1 value.
0
After a match, does not change the value to be compared with the LC.
1
After a match, automatically decrements by 1 the value to be
compared with the LC.
00h
~
FFh
Set the value to be compared with the LC.
23
2002-02-05
TC9447F
COMMAND-4Dh
(MISC)
0100 1101
D15
D14
D13
D12
D11
D10
0
0
0
0
0
SIS
Name
Description
SIS
Serial input
SOS
Serial output
Switches to access CROM using
LOG-LIN adjustment.
DP7F DATA-RAM 128/256 word switching
SYRC Initializes CP at each SYNC.
SYRO Initializes OFP at each SYNC
MCKE MCK pin output enable
MCKS MCK pin output switching
DLSEP Delay RAM table area switching
DLAC4 Delay RAM access method
COMMAND-4Fh
(M-RST)
D8
D7
SOS ERDET ZST
D6
D5
D4
D3
D2
D1
D0
DP7F SYRC SYRO MCKE MCKS DLSEP DLAC4
Value
ERDET Error detection
ZST
D9
Operation
0
Master (LRCK = FS, BCK = FSxx) (initial value)
1
Slave (LRCK = ELRI, BCK = EBCI)
0
Master (LRCK = FS, BCK = FSxx) (initial value)
1
Slave (LRCK = ELRO, BCK = EBCO)
0
Invalid
1
Valid (initial value)
0
2-cycle access
1
1-cycle access (initial value)
0
256 words (initial value)
1
128 words
0
Does not initialize.
1
Initializes (initial value).
0
Does not initialize.
1
Initializes (initial value).
0
Fixes to L
1
Output (initial value)
0
256 fs
1
When STEP1 pin = 0, outputs source oscillation (initial value).
When STEP1 pin = 1, used for testing.
0
Does not use table.
1
Uses 2-k word area as the table (initial value).
0
One access/6 cycles (initial value)
1
One access/4 cycles
0100 1111
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MRST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Description
MRST Initialization from the microcontroller
Value
Operation
0
Does not initialize.
1
Initializes (after initialization, automatically set to 0).
24
2002-02-05
TC9447F
COMMAND-50h
(MON-DB)
0101 0000
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3 D2
D1
D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3 D2
D1
D0
D1
D0
Name
Description
Value
D
Data bus monitor
[23:0]
COMMAND-51h
(MON-CP)
Operation
000000h~FFFFFFh
Reads data bus on the condition CMD: 4Bh, 4Ch.
0101 0001
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
0
0
0
Name
0
0
0
0
0
Description
CP
[8:0]
0
0
0
0
0
0
0
0
Name
000000h~00013h
0
0
0
0
0
0
Name
0
0
0
0
0
0
0
0
0
Name
0
0
0
D6
D5
D4
D3 D2
D1
D0
OFP OFP OFP OFP OFP OFP
0
5
4
3
2
1
0
Reads OFP on the condition CMD: 4Bh, 4Ch.
0
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3 D2
D1
D0
BP BP BP BP BP BP BP BP BP BP BP BP
11 10 9
8
7
6
5
4
3
1
2
0
Value
Operation
000000h~000FFFh
Reads BP on the condition CMD: 4Bh, 4Ch.
0101 0100
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
0
0
D7
0101 0011
BP
BP monitor
[11:0]
0
D8
Operation
000000h~00003h
Description
COMMAND-54h
(MON-AR)
D3 D2
Reads CP on the condition CMD: 4Bh, 4Ch.
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
0
D4
CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0
Value
OFP monitor
COMMAND-53h
(MON-BP)
D5
0101 0010
Description
OFP
[5:0]
D6
Operation
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
0
D7
Value
CP monitor
COMMAND-52h
(MON-OFP)
0
D8
0
0
Description
AR Delay RAM address
[11:0] monitor
0
0
0
0
0
0
Value
000000h~000FFFh
D8
D7
D6
D5
D4
D3 D2
D1
D0
AR AR AR AR AR AR AR AR AR AR AR AR
11 10 9
8
7
5
4
3
1
6
2
0
Operation
Reads delay RAM address on the condition CMD: 4Bh, 4Ch.
25
2002-02-05
TC9447F
COMMAND-55h
(MON-CRP)
0101 0101
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
0
0
0
Name
0
0
0
0
0
Description
COMMAND-56h
(MON-SR)
0
0
0
0
0
000000h~0001FFh
Name
SR
0
0
0
D6
D5
D4
D3 D2
D1
D0
Operation
Reads CRP on the condition CMD: 4Bh, 4Ch.
0101 0110
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
0
D7
Value
CRP (LIN-LOG
adjustment pointer)
monitor
CRP
[8:0]
0
D8
CRP CRP CRP CRP CRP CRP CRP CRP CRP
0
8
7
6
5
4
3
2
1
0
0
0
Description
SR (status register)
monitor
0
0
0
D1
D0
LI LG OV OV RD RD
LRF GF3 GF2 GF1 GF0 LG LI 1E 0E 24 16 V1F V0F ZF
SF
Value
―
D8
D7
D6
D5
D4
D3 D2
Operation
Reads SR on the condition CMD: 4Bh, 4Ch.
26
2002-02-05
TC9447F
4. Self-boot function description
(1)
Self-boot function
The TC9447F supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the
data are set via the microcontroller interface circuit.
First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various
modes to be set later. The microcontroller interface circuit supports two formats: I2C and the original
mode. However, the boot must be executed in Standard Transmission (the original) mode.
Figure 1 Self-boot system
(2)
Boot ROM format
The following shows the breakdown of the 18 bits.
00
Data that are being sent
01
Command
10
Final data (after the data are sent, the CS signal is set to “H”).
11
Jump address (jump to any address in the self-boot ROM).
Figure 2 Boot ROM Format and Example
Boot mode completes when the address reaches 3FFh, the maximum value.
Therefore, for the final address, write JMP 3FFh (data = 303FFh).
27
2002-02-05
TC9447F
(3)
Self-boot operation
Self-boot operations support two modes: one for use at reset and one for setting the microcontroller.
The modes can be used in combination.
(3-1)
Self-boot operation at reset
To enter this mode, set the BOOT pin to High, then set the RST pin from Low to High.
The 2048 fs period (46.4 ms when fs = 44.1 kHz) after a reset release is a wait period (for
power-on reset). The boot operation starts at the end of this period.
When switching the setting according to the application, specify the start address using the BA
[1:0] pin. At addresses 000h to 002h, set jump addresses.
The data setting speed is one word of SBROM per 1 fs. As up to 1024 words can be set in the
SBROM, the maximum time required for setting the data is half of the wait period.
Table 2 Relationship between fs and wait period
fs
Wait Period
Boot Time (Maximum)
32 kHz
64.0 ms
32.0 ms
44.1 kHz
46.4 ms
23.2 ms
48 kHz
42.7 ms
21.3 ms
Table 3 Relationship between BA [1:0] pin value
and start address
(3-2)
BA1
BA0
Start Address
0
0
000h
0
1
001h
1
0
002h
1
1
003h
Self-boot operation when setting microcontroller
In this mode, the microcontroller can specify any address and the operation starts from that
address. The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address
using the BOOT command (CMD: 41h) from the microcontroller starts the boot operation with no
wait.
The boot operation when set from the microcontroller is the same as the self-boot operation at
reset except that the boot operation can start from any address.
28
2002-02-05
29
Figure 3 Boot timing chart (at reset)
2002-02-05
TC9447F
TC9447F
Table 4 Differences depending on operating mode
(4)
Parameter
Boot Mode at Reset
Boot Mode Set from Microcontroller
Boot wait period
Yes
No
Boot start address
Select from 000h to 003h
Any address specified from
microcontroller
Boot pin
“H” level
Don't care
Programming examples
30
2002-02-05
TC9447F
(5)
Code format example
The following shows the format for storing data in SBROM.
31
2002-02-05
TC9447F
5. Cautions on use
(1)
The cautions at the time of using IFOK terminal
The timing which outputs IFOK signal is the signal which shows whether the command received from
the microcomputer was performed normally.
Since the initial value of IFCK signal is unfixed when a control microcomputer is checking IFOK
signal, before sending a command, it may stop performing control from a microcomputer.
(2)
The cautions at the time of using ACMP (address comparing mode)
In rewriting coefficient data and offset data using ACMP mode, please do not use it the following
condition.
(2-1)
Please do not transmit the following command before completing rewriting of data.
Please do not send the following command before completing rewriting of data of CRAM or
OFRAM.
Please check that waiting the term after rewriting of data is completed until it transmits the
following command was carried out, or rewriting has been completed using IFOK signal.
(2-2)
Please do not include data of an intact address.
Please do not include coefficient data of offset data of an address which are not used by the
program under execution, into transmitting data.
When data of an intact address is contained, operation in ACMP mode cannot be ended.
If the following command is transmitted in this state, RAM data will become unfixed also by the
command with the command unrelated to CRAM or OFRAM.
It needs to reset and all data needs to be re-set up to interrupt before completing rewriting of data
in the rewriting processing.
(2-3)
Please do not perform continuation transmission over the 0th address.
The transmission over the 0th address may incorrect-operate.
The same of this restriction is said not only of ACMP mode but continuation transmission of
usual RAM data.
For example, when writing in 007h from 1BFh and 000h from 1B8h of CRAM, it must transmit in
2 steps.
(3)
The following cautions are required when transmitting a reset command and a boot command in the
cautions I2C bus mode at the time of using the I2C bus mode.
(3-1)
At the time of reset command use
When transmitting a reset command (4Fh: M-RST) from a microcomputer, the acknowledgement
signal in front of the end conditions outputted from IFDI terminal is not transmitted to a
microcomputer.
Therefore, the acknowledgement signal of the last of IFDI signal should repeal at the time of
reset command transmission.
The timing at the time of reset command transmission is shown if Figure 4.
Figure 4 Timing at the time of command transmission
32
2002-02-05
TC9447F
(3-2)
At the time of self boot command use
When a self boot command (41h: BOOT) is transmitted, even if end conditions happen to the
acknowledgement signal of the last of boot command data, please repeal.
If it becomes the boot mode, data will be transmitted internal boot ROM data using the internal
circuit of a microcomputer interface.
Data is transmitted not in the I2C bus mode but in the standard transmitting mode at the time of
boot mode operation in that case.
Therefore, IFDI terminal will be in the state of H level, and operation of an I2C bus and
conditions may not be performed normally.
The timing at the time of self boot command transmission is shown if Figure 5.
Figure 5 Timing at the time of self boot command transmission
33
2002-02-05
34
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
Peripheral Circuit Example 1 (standard transmission mode)
2002-02-05
TC9447F
2
35
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
Peripheral Circuit Example 2 (I C bus mode)
2002-02-05
TC9447F
TC9447F
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Power supply voltage
VDD
−0.3~6.0
V
Input voltage
VIN
−0.3~VDD + 0.3
V
Power dissipation
PD
1500
mW
Operating temperature
Topr
Storage temperature
Tstg
Note 3:
−40~75 (Note 3)
°C
−55~150
°C
Only when frequency of operation is 340 step mode, a temperature of operation becomes Ta = −40~85°C.
Electrical Characteristics
(unless otherwise noted,
Ta = 25°C, VDD = VDX = VDDR = VDL = VDR = VDAL = VDAR = VDAC = VDAS = 5 V)
DC characteristics
Symbol
Test
Circuit
Operating power supply voltage
VDD
―
Operating frequency range
fopr
―
Operating power supply current
IDD
―
Characteristics
Test Condition
Min
Typ.
Max
Unit
Ta = −40~75°C
4.5
5.0
5.25
V
340-step mode
8
15
25
511-step mode
12
33.8
34
fopr = 33.8688 MHz
511-step mode
―
135
140
mA
Min
Typ.
Max
Unit
3.5
―
―
―
―
1.5
4.5
―
―
―
―
0.5
―
3.0
5.0
kΩ
Min
Typ.
Max
Unit
4.2
―
―
―
―
0.8
―
―
10
−10
―
―
―
2.8
―
―
2.0
―
―
0.8
―
MHz
Clock pins (XI, XO, ECKI, ECKO)
Symbol
Test
Circuit
“H” level
VIH1
―
“L” level
VIL1
―
“H” level
VOH1
―
IOH = −3.0 mA
“L” level
VOL1
―
IOL = 5.0 mA
RXD
―
XI, ECKI pin
Symbol
Test
Circuit
“H” level
VIH2
―
“L” level
VIL2
―
“H” level
IIH2
―
VIN = VDD
“L” level
IIL2
―
VIN = 0 V
“H” level
VP
―
“L” level
VN
―
VH
―
Characteristics
Input voltage (1)
Output voltage (1)
Pull-down resistance
Test Condition
XI, ECKI pin
XO, ECKO pin
V
V
Input pins
Characteristics
Input voltage (2)
Input leakage
current
Threshold voltage
Hysteresis voltage
Test Condition
(Note 4)
(Note 4)
(Note 5)
(Note 5)
V
µA
V
V
2
Note 4:
CKS, STEP0, STEP1, RST , SYNC, ELRO, ELRI, EBCO, EBCI, DIN, EM0, EM1, I CS, CS , IFCK, IFDI,
BOOT, BA0, BA1, TST0~3 (Normally input pins and Schmitt input pins)
Note 5:
Pins excluding I CS pins in Note 1 above (Schmitt input pins)
2
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TC9447F
Output pins
Symbol
Test
Circuit
“H” level
VOH2
―
IOH = −2.0 mA
“L” level
VOL2
―
IOL = 2.0 mA
“H” level
VOH3
―
IOH = −4.0 mA
“L” level
VOL3
―
IOL = 4.0 mA
Output voltage (4) “L” level
VOL4
―
IOL = 4.0 mA
Output open leakage current
IOZ4
―
VOH = VDD
Characteristics
Output voltage (2)
Output voltage (3)
Test Condition
(Note 6)
(Note 7)
(Note 8)
Min
Typ.
Max
Unit
4.5
―
―
―
―
0.5
4.5
―
―
―
―
0.5
―
―
0.5
V
―
―
±10
µA
V
V
Note 6: FS, CKO0, CKO1, MCK, DOUT (Normally output)
Note 7: IFDO (Normally output)
2
Note 8: IFDI (When I C mode output), IFOK, ACK , ERR (Open drain output)
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TC9447F
AC Characteristics (1) Analog
AD converter characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Maximum input signal level
Vi
―
Input level that ADC digital output
does not overflow
(Note 9)
1.13
1.20
―
Vrms
Input impedance
Zin
―
LIN, RIN pins
(Note 9)
―
27.0
―
kΩ
S/Na1
―
A-Weight, When using X'tal
oscillator at 33.8688 MHz (Note 9)
90
98
―
S/Na2
―
CCIR-ARM, When using X'tal
oscillator at 33.8688 MHz (Note 9)
88
94
―
THD + N
THDa
―
20 kHz LPF, When using X'tal
oscillator at 33.8688 MHz (Note 9)
―
−77
−70
dB
Crosstalk
CTa
―
A-Weight, When using X'tal
oscillator at 33.8688 MHz (Note 9)
―
−95
−88
dB
Dynamic range
DRa
―
A-Weight, When using X'tal
oscillator at 33.8688 MHz (Note 9)
―
95
90
dB
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
VO1
―
Output voltage at full-scale digital
input
(Note 10)
1.10
1.21
1.32
VO2
―
Output voltage at full-scale digital
input (Trim output)
(Note 11)
1.35
1.52
1.61
Trim output pin:
attenuation level
VOAL
―
(Note 11)
0
―
−20
dB
Trim output pin:
step level
VOAS
―
(Note 11)
―
1
―
dB
S/N ratio
S/Nd
―
A-Weight, When using X'tal
oscillator at 33.8688 MHz (Note 12)
90
100
―
dB
THDd1
―
20 kHz, When using X'tal oscillator
at 33.8688 MHz
(Note 10)
―
−87
−80
THDd2
―
20 kHz, When using X'tal oscillator
at 33.8688 MHz
(Note 11)
―
−82
−75
Crosstalk
CTd
―
A-Weight, When using X'tal
oscillator at 33.8688 MHz (Note 12)
―
−95
−88
dB
Dynamic range
DRd
―
A-Weight, When using X'tal
oscillator at 33.8688 MHz (Note 12)
―
95
90
dB
Characteristics
S/(N + D) ratio
dB
Note 9: Input channels: LIN, RIN
DA converter characteristics
Characteristics
Output signal level
THD+N
Vrms
dB
Note 10: Output channel: AOL, AOR, AOC, AOS
Note 11: Output channel: AOCT, AOST
Note 12: Output channel: AOL, AOR, AOC, AOS, AOCT, AOST
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TC9447F
AC Characteristics (2) Timing
Clock input pins (XI, ECKI)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
tXI
―
―
29
―
―
ns
Clock “H” cycle width
tXIH
―
―
―
14.5
―
ns
Clock “L” cycle width
tXIL
―
―
―
14.5
―
ns
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Standby time
tRRS
―
―
10
―
―
ms
Reset pulse width
tWRS
―
―
1.0
―
―
µs
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
tDFC
―
―
−150
―
150
ns
Test Condition
Min
Typ.
Max
Unit
Characteristics
Clock cycle
Reset pin ( RST )
Characteristics
Timing output
Characteristics
CKO output delay time
Audio serial interface (EBCI, DIN, EBCO, DOUT)
Symbol
Test
Circuit
ELRI hold time
tLIH
―
CL = 30 pF
−75
―
75
ns
DIN setup time
tSDI
―
CL = 30 pF
50
―
―
ns
DIN hold time
tHDI
―
CL = 30 pF
50
―
―
ns
EBCI clock cycle
tEBCI
―
CL = 30 pF
300
―
―
ns
EBCI clock “H” cycle width
tEBIH
―
CL = 30 pF
150
―
―
ns
EBCI clock “L” cycle width
tEBIL
―
CL = 30 pF
150
―
―
ns
ELRO hold time
tLOH
―
CL = 30 pF
−75
―
75
ns
DOUT output delay time (1)
tDO1
―
CL = 30 pF
―
―
60
ns
DOUT output delay time (2)
tDO2
―
CL = 30 pF
―
―
60
ns
EBCO clock cycle
tEBCO
―
CL = 30 pF
300
―
―
ns
EBCO clock “H” cycle width
tEBOH
―
CL = 30 pF
150
―
―
ns
EBCO clock “L” cycle width
tEBOL
―
CL = 30 pF
150
―
―
ns
Characteristics
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TC9447F
Microcontroller Interface
Standard transmission mode ( CS , IFCK, IFDI, IFDO, ACK )
Symbol
Test
Circuit
Standby time
tSTB
CS ↓ - IFCK↓
Setup time (Mode 1)
Characteristics
Test Condition
Min
Typ.
Max
Unit
―
1.0
―
―
µs
tCCD
―
0.5
―
―
µs
IFCK “L” cycle width
tWLC
―
0.5
―
―
µs
IFCK “H” cycle width
tWHC
―
0.5
―
―
µs
IFCK↑ - CS ↑
Setup time
tCKC
―
0.5
―
―
µs
CS “H” cycle width
tWCS
―
1.0
―
―
µs
IFCK↑ - CS ↑
Setup time (Mode 2)
tCCU
―
0.5
―
―
µs
IFCK↓ - CS ↓
Setup time
tSCK
―
0.5
―
―
µs
IFDI - IFCK↑
Setup time
tSCD
―
0.5
―
―
µs
IFCK↑ - IFDI
Hold time
tHCD
―
0.5
―
―
µs
IFCK↓ - IFDO
Propagation delay time
tDDO
―
CL = 30 pF
―
―
0.5
µs
IFCK↑ - ACK ↓
Propagation delay time
tDAKD
―
CL = 30 pF
(Pull-up resistor) RL = 1 kΩ
―
―
0.5
µs
IFCK↓ - ACK ↑
Propagation delay time
tDAKZ
―
CL = 30 pF
(Pull-up resistor) RL = 1 KΩ
―
―
0.5
µs
(Note 13)
Note 13: The command which is "Sync" in the transfer Sync with Sync signal of a 17 page table 1 control command
table needs to set the CS = H section to a minimum of 1 fs more until it transmits the following command.(It
needs more than 22.68 µs at fs = 44.1 kHz)
2
I C mode ( CS , IFCK, IFDI)
Symbol
Test
Circuit
IFCK clock frequency
fIFCK
―
IFCK “H” cycle width
tH
IFCK “L” cycle width
Characteristics
Min
Typ.
Max
Unit
CL = 400 pF
0
―
400
kHz
―
CL = 400 pF
0.6
―
―
µs
tL
―
CL = 400 pF
1.3
―
―
µs
Data setup time
tDS
―
CL = 400 pF
0.1
―
―
µs
Data hold time
tDH
―
CL = 400 pF
0
―
―
µs
Transmission start condition hold
time
tSCH
―
CL = 400 pF
0.6
―
―
µs
Repeat transmission start
condition setup time
tSCS
―
CL = 400 pF
0.6
―
―
µs
Transmission end condition setup
time
tECS
―
CL = 400 pF
0.6
―
―
µs
Data transmission interval
tBUF
―
CL = 400 pF
1.3
―
―
µs
tR
―
CL = 400 pF
―
―
0.3
µs
tF
―
CL = 400 pF
―
―
0.3
µs
2
I C rise time
2
I C fall time
Test Condition
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TC9447F
AC Characteristics Test Points
1. Clock pins (XI, ECKI)
2. Reset
3. Timing output
4. Audio serial interface (ELRI, EBCI, DIN, ELRO, EBCO, DOUT)
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TC9447F
5. Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO, ACK )
2
6. Microcontroller interface in I C mode (IFCK, IFDI)
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Right to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
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TC9447F
Package Dimensions
Weight: 1.57 g (typ.)
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2002-02-05
TC9447F
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
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