Sharp LH28F320BFHG-PTTLZK 32m (x16) flash memory Datasheet

Date
32M (x16) Flash Memory
LH28F320BFHG-PTTLZK
Mar. 19. 2003
LHF32FDJ
• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
• When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
• Office electronics
• Instrumentation and measuring equipment
• Machine tools
• Audiovisual equipment
• Home appliance
• Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
• Mainframe computers
• Traffic control systems
• Gas leak detectors and automatic cutoff devices
• Rescue and security equipment
• Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in terms of functionality, reliability, or accuracy.
• Aerospace equipment
• Communications equipment for trunk lines
• Control equipment for the nuclear power industry
• Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 2.44
LHF32FDJ
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CONTENTS
PAGE
PAGE
0.75mm pitch 48-Ball CSP (7mm×7mm) Pinout ....... 3
Extended Status Register Definition ......................... 15
Pin Descriptions.......................................................... 4
Partition Configuration Register Definition.............. 16
Simultaneous Operation Modes
Allowed with Four Planes .................................. 5
Partition Configuration ............................................. 16
1 Electrical Specifications......................................... 17
Memory Map .............................................................. 6
1.1 Absolute Maximum Ratings ........................... 17
Identifier Codes and OTP Address
for Read Operation ............................................. 7
Identifier Codes and OTP Address for
Read Operation on Partition Configuration........ 7
1.2 Operating Conditions ...................................... 17
1.2.1 Capacitance .............................................. 18
1.2.2 AC Input/Output Test Conditions ............ 18
OTP Block Address Map for OTP Program............... 8
1.2.3 DC Characteristics ................................... 19
Bus Operation............................................................. 9
Command Definitions .............................................. 10
Functions of Block Lock and Block Lock-Down..... 12
Block Locking State Transitions upon
Command Write................................................ 12
Block Locking State Transitions upon
WP# Transition................................................. 13
1.2.4 AC Characteristics
- Read-Only Operations......................... 21
1.2.5 AC Characteristics
- Write Operations ................................. 25
1.2.6 Reset Operations ...................................... 27
1.2.7 Block Erase, Full Chip Erase,
(Page Buffer) Program and
OTP Program Performance.................... 28
Status Register Definition......................................... 14
2 Related Document Information.............................. 29
Rev. 2.44
LHF32FDJ
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LH28F320BFHG-PTTLZK
32Mbit (2Mbit×16)
Page Mode Dual Work Flash MEMORY
32M density with 16Bit I/O Interface
High Performance Reads
• 80/35ns 8-Word Page Mode
Configurative 4-Plane Dual Work
• Flexible Partitioning
• Read operations during Block Erase or (Page Buffer)
Program
• Status Register for Each Partition
Low Power Operation
• 2.7V Read and Write Operations
• VCCQ for Input/Output Power Supply Isolation
• Automatic Power Savings Mode Reduces ICCR
in Static Mode
Enhanced Code + Data Storage
• 5µs Typical Erase/Program Suspends
OTP (One Time Program) Block
• 4-Word Factory-Programmed Area
• 4-Word User-Programmable Area
High Performance Program with Page Buffer
• 16-Word Page Buffer
• 5µs/Word (Typ.) at 12V VPP
Flexible Blocking Architecture
• Eight 4K-word Parameter Blocks
• Sixty-three 32K-word Main Blocks
• Top Parameter Location
Enhanced Data Protection Features
• Individual Block Lock and Block Lock-Down with
Zero-Latency
• All blocks are locked at power-up or device reset.
• Absolute Protection with VPP≤VPPLK
• Block Erase, Full Chip Erase, (Page Buffer) Word
Program Lockout during Power Transitions
Automated Erase/Program Algorithms
• 3.0V Low-Power 11µs/Word (Typ.)
Programming
• 12V No Glue Logic 9µs/Word (Typ.)
Production Programming and 0.5s Erase (Typ.)
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
0.75mm pitch 48-Ball CSP (7mm×7mm)
Operating Temperature -40°C to +85°C
ETOXTM* Flash Technology
CMOS Process (P-type silicon substrate)
Not designed or rated as radiation hardened
The product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at VCC=2.7V-3.6V and VPP=1.65V-3.6V or 11.7V-12.3V. Its low voltage operation capability greatly extends
battery life for portable applications.
The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus
eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual
work operation.
The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 2.44
LHF32FDJ
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1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP#
A19
A7
A4
B
A14
A10
A18
A17
A5
A2
C
A15
A12
A20
A6
A3
A1
D
A16
DQ14 DQ5 DQ11 DQ2
DQ8
CE#
A0
E
VCCQ DQ15 DQ6 DQ12 DQ3
DQ9
DQ0 GND
F
GND DQ7 DQ13 DQ4
WE# RST#
A9
NC
VCC DQ10 DQ1
0.75mm pitch
48-BALL CSP
PINOUT
7mm x 7mm
TOP VIEW
OE#
Figure 1. 0.75mm pitch 48-Ball CSP (7mm×7mm) Pinout
Rev. 2.44
LHF32FDJ
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Table 1. Pin Descriptions
Symbol
A0-A20
Type
INPUT
Name and Function
ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code and partition configuration register code reads. Data pins float to highimpedance (High Z) when the chip or outputs are deselected. Data is internally latched
during an erase or program cycle.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to
standby levels.
RST#
INPUT
RESET: When low (VIL), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (VIH) enables normal operation. After
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
OE#
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WP#
INPUT
WRITE PROTECT: When WP# is VIL, locked-down blocks cannot be unlocked. Erase
or program operation can be executed to the blocks which are not locked and not lockeddown. When WP# is VIH, lock-down is disabled.
VPP
INPUT
MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin.
With VPP≤VPPLK, block erase, full chip erase, (page buffer) program or OTP program
cannot be executed and should not be attempted.
Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this
mode, VPP is power supply pin. Applying 12V±0.3V to VPP during erase/program can
only be done for a maximum of 1,000 cycles on each block. VPP may be connected to
12V±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits
may reduce block cycling capability or cause permanent damage.
VCC
SUPPLY
DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VCC voltage (see DC
Characteristics) produce spurious results and should not be attempted.
VCCQ
SUPPLY
INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output
pins.
GND
SUPPLY
GROUND: Do not float any ground pins.
DQ0-DQ15
CE#
NC
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Rev. 2.44
LHF32FDJ
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Table 2. Simultaneous Operation Modes Allowed with Four Planes(1, 2)
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
IF ONE
PARTITION IS:
Read Read
Read
Array ID/OTP Status
Read
Word
Query Program
Page
Block
OTP
Block Full Chip Program
Buffer
Erase
Program Erase
Erase Suspend
Program
Suspend
Read Array
X
X
X
X
X
X
X
X
X
Read ID/OTP
X
X
X
X
X
X
X
X
X
Read Status
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
X
Word Program
X
X
X
X
X
Page Buffer
Program
X
X
X
X
X
OTP Program
Block Erase
X
X
X
X
X
X
X
Full Chip Erase
X
X
X
Program
Suspend
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
X
NOTES:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each
partition. Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
Rev. 2.44
LHF32FDJ
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70
4K-WORD
1FF000H - 1FFFFFH
69
4K-WORD
1FE000H - 1FEFFFH
68
4K-WORD
1FD000H - 1FDFFFH
67
4K-WORD
1FC000H - 1FCFFFH
66
4K-WORD
1FB000H - 1FBFFFH
65
4K-WORD
1FA000H - 1FAFFFH
64
4K-WORD
1F9000H - 1F9FFFH
63
4K-WORD
1F8000H - 1F8FFFH
31 32K-WORD
0F8000H - 0FFFFFH
62
32K-WORD
1F0000H - 1F7FFFH
30 32K-WORD
0F0000H - 0F7FFFH
61
32K-WORD
1E8000H - 1EFFFFH
29 32K-WORD
0E8000H - 0EFFFFH
60
32K-WORD
1E0000H - 1E7FFFH
28 32K-WORD
0E0000H - 0E7FFFH
59
32K-WORD
1D8000H - 1DFFFFH
27 32K-WORD
0D8000H - 0DFFFFH
58
32K-WORD
1D0000H - 1D7FFFH
26 32K-WORD
0D0000H - 0D7FFFH
57
32K-WORD
1C8000H - 1CFFFFH
25 32K-WORD
0C8000H - 0CFFFFH
56
32K-WORD
1C0000H - 1C7FFFH
24 32K-WORD
0C0000H - 0C7FFFH
55
32K-WORD
1B8000H - 1BFFFFH
23 32K-WORD
0B8000H - 0BFFFFH
54
32K-WORD
1B0000H - 1B7FFFH
22 32K-WORD
0B0000H - 0B7FFFH
53
32K-WORD
1A8000H - 1AFFFFH
21 32K-WORD
0A8000H - 0AFFFFH
52
32K-WORD
1A0000H - 1A7FFFH
20 32K-WORD
0A0000H - 0A7FFFH
51
32K-WORD
198000H - 19FFFFH
19 32K-WORD
098000H - 09FFFFH
50
32K-WORD
190000H - 197FFFH
18 32K-WORD
090000H - 097FFFH
49
32K-WORD
188000H - 18FFFFH
17 32K-WORD
088000H - 08FFFFH
48
32K-WORD
180000H - 187FFFH
16 32K-WORD
080000H - 087FFFH
47
32K-WORD
178000H - 17FFFFH
15 32K-WORD
078000H - 07FFFFH
46
32K-WORD
170000H - 177FFFH
14 32K-WORD
070000H - 077FFFH
45
32K-WORD
168000H - 16FFFFH
13 32K-WORD
068000H - 06FFFFH
44
32K-WORD
160000H - 167FFFH
12 32K-WORD
060000H - 067FFFH
43
32K-WORD
158000H - 15FFFFH
11 32K-WORD
058000H - 05FFFFH
42
32K-WORD
150000H - 157FFFH
10 32K-WORD
050000H - 057FFFH
41
32K-WORD
148000H - 14FFFFH
9
32K-WORD
048000H - 04FFFFH
40
32K-WORD
140000H - 147FFFH
8
32K-WORD
040000H - 047FFFH
39
32K-WORD
138000H - 13FFFFH
7
32K-WORD
038000H - 03FFFFH
38
32K-WORD
130000H - 137FFFH
6
32K-WORD
030000H - 037FFFH
37
32K-WORD
128000H - 12FFFFH
5
32K-WORD
028000H - 02FFFFH
36
32K-WORD
120000H - 127FFFH
4
32K-WORD
020000H - 027FFFH
35
32K-WORD
118000H - 11FFFFH
3
32K-WORD
018000H - 01FFFFH
34
32K-WORD
110000H - 117FFFH
2
32K-WORD
010000H - 017FFFH
33
32K-WORD
108000H - 10FFFFH
1
32K-WORD
008000H - 00FFFFH
32
32K-WORD
100000H - 107FFFH
0
32K-WORD
000000H - 007FFFH
PLANE1 (UNIFORM PLANE)
BLOCK NUMBER ADDRESS RANGE
PLANE0 (UNIFORM PLANE)
PLANE2 (UNIFORM PLANE)
PLANE3 (PARAMETER PLANE)
BLOCK NUMBER ADDRESS RANGE
Figure 2. Memory Map (Top Parameter)
Rev. 2.44
LHF32FDJ
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Table 3. Identifier Codes and OTP Address for Read Operation
Code
Address
[A15-A0]
Data
[DQ15-DQ0]
Notes
Manufacturer Code
Manufacturer Code
0000H
00B0H
1
Device Code
Top Parameter Device Code
0001H
00B4H
1, 2
Block Lock Configuration
Code
Block is Unlocked
DQ0 = 0
3
DQ0 = 1
3
DQ1 = 0
3
DQ1 = 1
3
Block
Address
+2
Block is Locked
Block is not Locked-Down
Block is Locked-Down
Device Configuration Code
Partition Configuration Register
0006H
PCRC
1, 4
OTP
OTP Lock
0080H
OTP-LK
1, 5
0081-0088H
OTP
1, 6
OTP
NOTES:
1. The address A20-A16 are shown in below table for reading the manufacturer code, device code,
device configuration code and OTP data.
2. Top parameter device has its parameter blocks in the plane3 (The highest address).
3. Block Address = The beginning location of a block address within the partition to which
the Read Identifier Codes/OTP command (90H) has been written.
DQ15-DQ2 are reserved for future implementation.
4. PCRC=Partition Configuration Register Code.
5. OTP-LK=OTP Block Lock configuration.
6. OTP=OTP Block data.
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) (32M-bit device)
Partition Configuration Register (2)
Address (32M-bit device)
[A20-A16]
PCR.10
PCR.9
PCR.8
0
0
0
00H
0
0
1
00H or 08H
0
1
0
00H or 10H
1
0
0
00H or 18H
0
1
1
00H or 08H or 10H
1
1
0
00H or 10H or 18H
1
0
1
00H or 08H or 18H
1
1
1
00H or 08H or 10H or 18H
NOTES:
1. The address to read the identifier codes or OTP data is dependent on the partition which is selected
when writing the Read Identifier Codes/OTP command (90H).
2. Refer to Table 12 for the partition configuration register.
Rev. 2.44
LHF32FDJ
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[A20-A0]
000088H
Customer Programmable Area
000085H
000084H
Factory Programmed Area
000081H
000080H
Reserved for Future Implementation
(DQ15-DQ2)
Customer Programmable Area Lock Bit (DQ1)
Factory Programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program
(The area outside 80H~88H cannot be used.)
Rev. 2.44
LHF32FDJ
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Table 5. Bus Operation(1, 2)
Mode
Notes
RST#
CE#
OE#
WE#
Address
VPP
DQ0-15
6
VIH
VIL
VIL
VIH
X
X
DOUT
Output Disable
VIH
VIL
VIH
VIH
X
X
High Z
Standby
VIH
VIH
X
X
X
X
High Z
Read Array
Reset
3
VIL
X
X
X
X
X
High Z
Read Identifier
Codes/OTP
6
VIH
VIL
VIL
VIH
See
Table 3 and
Table 4
X
See
Table 3 and
Table 4
6,7
VIH
VIL
VIL
VIH
See
Appendix
X
See
Appendix
4,5,6
VIH
VIL
VIH
VIL
X
X
DIN
Read Query
Write
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but cannot be altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK
and VPPH1/2 voltages.
3. RST# at GND±0.2V ensures the lowest power consumption.
4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed
when VPP=VPPH1/2 and VCC=2.7V-3.6V.
5. Refer to Table 6 for valid DIN during a write operation.
6. Never hold OE# low and WE# low at the same timing.
7. Refer to Appendix of LH28F320BF series for more information about query code.
Rev. 2.44
LHF32FDJ
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Table 6. Command Definitions(11)
Command
Read Array
Bus
Cycles
Req’d
First Bus Cycle
Notes
1
Oper
(1)
Addr
(2)
Second Bus Cycle
Data
Write
PA
FFH
(1)
Oper
Addr(2)
Data(3)
Read Identifier Codes/OTP
≥2
4
Write
PA
90H
Read
IA or OA
ID or OD
Read Query
≥2
4
Write
PA
98H
Read
QA
QD
Read
PA
SRD
Read Status Register
2
Write
PA
70H
Clear Status Register
1
Write
PA
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
Full Chip Erase
2
5,9
Write
X
30H
Write
X
D0H
2
5,6
Write
WA
40H or
10H
Write
WA
WD
≥4
5,7
Write
WA
E8H
Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
8,9
Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
8,9
Write
PA
D0H
Set Block Lock Bit
2
Write
BA
60H
Write
BA
01H
Clear Block Lock Bit
2
Write
BA
60H
Write
BA
D0H
Set Block Lock-down Bit
2
Write
BA
60H
Write
BA
2FH
OTP Program
2
Write
OA
C0H
Write
OA
OD
Set Partition Configuration Register
2
Write
PCRC
60H
Write
PCRC
04H
Program
Page Buffer Program
10
9
NOTES:
1. Bus operations are defined in Table 5.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
bus cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See Table 3 and Table 4).
QA=Query codes address. Refer to Appendix of LH28F320BF series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
PCRC=Partition configuration register code presented on the address A0-A15.
3. ID=Data read from identifier codes. (See Table 3 and Table 4).
QD=Data read from query database. Refer to Appendix of LH28F320BF series for details.
SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever
goes high first) during command write cycles.
OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)
during command write cycles.
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when RST# is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
Rev. 2.44
LHF32FDJ
11
LH28F320BF series for details.
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while
the block erase operation is being suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is VIL. When
WP# is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 2.44
LHF32FDJ
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Table 7. Functions of Block Lock(5) and Block Lock-Down
Current State
State
WP#
DQ1
(1)
DQ0(1)
State Name
Erase/Program Allowed (2)
[000]
0
0
0
Unlocked
Yes
[001](3)
0
0
1
Locked
No
[011]
0
1
1
Locked-down
No
[100]
1
0
0
Unlocked
Yes
[101](3)
1
0
1
Locked
No
[110](4)
1
1
0
Lock-down Disable
Yes
[111]
1
1
1
Lock-down Disable
No
NOTES:
1. DQ0=1: a block is locked; DQ0=0: a block is unlocked.
DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, full chip erase and
(page buffer) program operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.
4. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are
automatically locked.
5. OTP (One Time Program) block has the lock function which is different from those described
above.
Table 8. Block Locking State Transitions upon Command Write(4)
Current State
Result after Lock Command Written (Next State)
State
WP#
DQ1
DQ0
Set Lock(1)
Clear Lock(1)
Set Lock-down(1)
[000]
0
0
0
[001]
No Change
[011](2)
[001]
0
0
1
No Change(3)
[000]
[011]
[011]
0
1
1
No Change
No Change
No Change
[100]
1
0
0
[101]
No Change
[111](2)
[101]
1
0
1
No Change
[100]
[111]
[110]
1
1
0
[111]
No Change
[111](2)
[111]
1
1
1
No Change
[110]
No Change
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
command and "Set Lock-down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the
corresponding block is locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that WP# is not changed and fixed VIL or VIH.
Rev. 2.44
LHF32FDJ
13
Table 9. Block Locking State Transitions upon WP# Transition(4)
Current State
Previous State
Result after WP# Transition (Next State)
State
WP#
DQ1
DQ0
WP#=0→1(1)
WP#=1→0(1)
-
[000]
0
0
0
[100]
-
-
[001]
0
0
1
[101]
-
[110]
-
[011]
0
1
1
[111]
-
-
[100]
1
0
0
-
[000]
-
[101]
1
0
1
-
[001]
-
[110]
1
1
0
-
[011](3)
-
[111]
1
1
1
-
[011]
[110](2)
Other than [110](2)
NOTES:
1. "WP#=0→1" means that WP# is driven to VIH and "WP#=1→0" means that WP# is driven to
VIL.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are
automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in
previous, current and next state.
Rev. 2.44
LHF32FDJ
14
Table 10. Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
WSMS
BESS
BEFCES
PBPOPS
VPPS
PBPSS
DPS
R
7
6
5
4
3
2
1
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
STATUS (BEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
SR.4 = (PAGE BUFFER) PROGRAM AND
OTP PROGRAM STATUS (PBPOPS)
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
SR.3 = VPP STATUS (VPPS)
1 = VPP LOW Detect, Operation Abort
0 = VPP OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
NOTES:
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to 2,
3 or 4 partitions configuration.
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit, set partition configuration register
attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to
report accurate feedback when VPP≠VPPH1, VPPH2 or VPPLK.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Rev. 2.44
LHF32FDJ
15
Table 11. Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) register.
Rev. 2.44
LHF32FDJ
16
Table 12. Partition Configuration Register Definition
R
R
R
R
R
PC2
PC1
PC0
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
PCR.15-11 and PCR.7-0 are reserved for future use and
should be masked out when checking the partition
configuration register.
PLANE0
PLANE1
PLANE3
0 1 1
PLANE2
PARTITIONING FOR DUAL WORK
PARTITION2 PARTITION1 PARTITION0
PC2 PC1PC0
PLANE0
PLANE1
1 1 0
PLANE2
PARTITION2 PARTITION1 PARTITION0
PLANE0
1 0 1
PLANE1
PARTITION2 PARTITION1 PARTITION0
PLANE2
PLANE0
PLANE0
PLANE1
1 1 1
PLANE2
PLANE0
PARTITION3 PARTITION2 PARTITION1 PARTITION0
PLANE3
PLANE1
PLANE1
PLANE2
PLANE3
See Figure 4 for the detail on partition configuration.
PARTITION0
PARTITION1
1 0 0
After power-up or device reset, PCR10-8 (PC2-0) is set to
"001" in a bottom parameter device and "100" in a top
parameter device.
PARTITION0
PLANE0
PLANE2
0 1 0
PLANE3
PARTITION1
NOTES:
PARTITION0
PLANE1
PLANE2
0 0 1
PLANE3
PARTITION1
PLANE0
PLANE1
PLANE2
0 0 0
PARTITIONING FOR DUAL WORK
PARTITION0
PLANE3
PC2 PC1PC0
PCR.7-0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
PLANE3
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
010 = Plane 0-1 and Plane2-3 are merged into one
partition respectively.
100 = Plane 0-2 are merged into one partition.
(default in a top parameter device)
011 = Plane 2-3 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
110 = Plane 0-1 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
101 = Plane 1-2 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
111 = There are four partitions in this configuration.
Each plane corresponds to each partition respectively. Dual work operation is available between any
two partitions.
PLANE3
PCR.15-11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
Figure 4. Partition Configuration
Rev. 2.44
LHF32FDJ
1 Electrical Specifications
17
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond
the "Operating Conditions" may affect device
reliability.
1.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Erase and Program ...-40°C to +85°C (1)
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on VCC and VPP pins. During transitions,
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins is
VCC+0.5V which, during transitions, may overshoot to
VCC+2.0V for periods <20ns.
3. Maximum DC voltage on VPP may overshoot to
+13.0V for periods <20ns.
4. VPP erase/program voltage is normally 2.7V-3.6V.
Applying 11.7V-12.3V to VPP during erase/program
can be done for a maximum of 1,000 cycles on the
main blocks and 1,000 cycles on the parameter blocks.
VPP may be connected to 11.7V-12.3V for a total of 80
hours maximum.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
Storage Temperature
During under Bias............................... -40°C to +85°C
During non Bias................................ -65°C to +125°C
Voltage On Any Pin
(except VCC and VPP).............. -0.5V to VCC+0.5V (2)
VCC and VCCQ Supply Voltage .......... -0.2V to +3.9V (2)
VPP Supply Voltage .................... -0.2V to +12.6V (2, 3, 4)
Output Short Circuit Current ........................... 100mA (5)
1.2 Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
TA
-40
+25
+85
°C
VCC Supply Voltage
VCC
2.7
3.0
3.6
V
1
I/O Supply Voltage
VCCQ
2.7
3.0
3.6
V
1
VPP Voltage when Used as a Logic Control
VPPH1
1.65
3.0
3.6
V
1
VPP Supply Voltage
VPPH2
11.7
12
12.3
V
1, 2
Operating Temperature
Main Block Erase Cycling: VPP=VPPH1
100,000
Cycles
Parameter Block Erase Cycling: VPP=VPPH1
100,000
Cycles
Main Block Erase Cycling: VPP=VPPH2, 80 hrs.
1,000
Cycles
Parameter Block Erase Cycling: VPP=VPPH2, 80 hrs.
1,000
Cycles
80
Hours
Maximum VPP hours at VPPH2
Notes
NOTES:
1. See DC Characteristics tables for voltage range-specific specification.
2. Applying VPP=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks
and 1,000 cycles on the parameter blocks. A permanent connection to VPP=11.7V-12.3V is not allowed and can cause
damage to the device.
Rev. 2.44
LHF32FDJ
18
1.2.1 Capacitance(1) (TA=+25°C, f=1MHz)
Parameter
Symbol
Condition
CIN
COUT
Input Capacitance
Output Capacitance
Min.
Typ.
Max.
Unit
VIN=0.0V
4
7
pF
VOUT=0.0V
6
10
pF
NOTE:
1. Sampled, not 100% tested.
1.2.2 AC Input/Output Test Conditions
VCCQ
INPUT
VCCQ/2
TEST POINTS
VCCQ/2 OUTPUT
0.0
AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when VCC=VCC(min).
Figure 5. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Table 13. Configuration Capacitance Loading Value
VCCQ(min)/2
1N914
Test Configuration
CL (pF)
VCC=2.7V-3.6V
50
RL=3.3k
DEVICE
UNDER
TEST
CL Includes Jig
Capacitances.
OUT
CL
Figure 6. Transient Equivalent Testing Load Circuit
Rev. 2.44
LHF32FDJ
19
1.2.3 DC Characteristics
VCC=2.7V-3.6V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
VCC=VCCMax.,
VCCQ=VCCQMax.,
VIN/VOUT=VCCQ or
GND
ILI
Input Load Current
1
-1.0
+1.0
µA
ILO
Output Leakage Current
1
-1.0
+1.0
µA
1
4
20
µA
VCC=VCCMax.,
CE#=RST#=
VCCQ±0.2V,
WP#=VCCQ or GND
1,4
4
20
µA
VCC=VCCMax.,
CE#=GND±0.2V,
WP#=VCCQ or GND
1
4
20
µA
RST#=GND±0.2V
Average VCC Read
Current
Normal Mode
1,7
15
25
mA
Average VCC Read
8 Word Read
Current
Page Mode
1,7
5
10
mA
VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=5MHz
1,5,7
20
60
mA
VPP=VPPH1
1,5,7
10
20
mA
VPP=VPPH2
1,5,7
10
30
mA
VPP=VPPH1
1,5,7
4
10
mA
VPP=VPPH2
ICCS
VCC Standby Current
ICCAS
VCC Automatic Power Savings Current
ICCD
VCC Reset Power-Down Current
ICCR
ICCW
VCC (Page Buffer) Program Current
ICCE
VCC Block Erase, Full Chip
Erase Current
ICCWS
ICCES
VCC (Page Buffer) Program or
Block Erase Suspend Current
1,2,7
10
200
µA
CE#=VIH
IPPS
IPPR
VPP Standby or Read Current
1,6,7
2
5
µA
VPP≤VCC
IPPW
VPP (Page Buffer) Program Current
1,5,6,7
2
5
µA
VPP=VPPH1
1,5,6,7
10
30
mA
VPP=VPPH2
IPPE
VPP Block Erase, Full Chip
Erase Current
1,5,6,7
2
5
µA
VPP=VPPH1
1,5,6,7
5
15
mA
VPP=VPPH2
IPPWS
VPP (Page Buffer) Program
Suspend Current
1,6,7
2
5
µA
VPP=VPPH1
1,6,7
10
200
µA
VPP=VPPH2
IPPES
VPP Block Erase Suspend Current
1,6,7
2
5
µA
VPP=VPPH1
1,6,7
10
200
µA
VPP=VPPH2
Rev. 2.44
LHF32FDJ
20
DC Characteristics (Continued)
VCC=2.7V-3.6V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
5
-0.4
0.4
V
VIH
Input High Voltage
5
2.4
VCCQ
+ 0.4
V
VOL
Output Low Voltage
5
0.2
VCCQ
-0.2
VOH
Output High Voltage
VPPLK
VPP Lockout during Normal
Operations
VPPH1
VPP during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations
6
1.65
VPPH2
VPP during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations
6
11.7
VLKO
VCC Lockout Voltage
5
3,5,6
1.5
Test Conditions
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOL=100µA
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOH=-100µA
0.4
V
3.0
3.6
V
12
12.3
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25°C
unless VCC is specified.
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device’s current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page
buffer) program suspend mode, the device’s current draw is the sum of ICCWS and ICCR.
3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when VPP≤VPPLK, and not guaranteed
in the range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.) and above VPPH2(max.).
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (tAVQV) provide new data when addresses are changed.
5. Sampled, not 100% tested.
6. VPP is not used for power supply pin. With VPP≤VPPLK, block erase, full chip erase, (page buffer) program and OTP
program cannot be executed and should not be attempted.
Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths
and layout considerations given to the VCC power bus.
Applying 12V±0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP
may be connected to 12V±0.3V for a total of 80 hours maximum.
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
Rev. 2.44
LHF32FDJ
21
1.2.4 AC Characteristics - Read-Only Operations(1)
VCC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
Parameter
Notes
Min.
Max.
Unit
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE# to Output Delay
tAPA
Page Address Access Time
tGLQV
OE# to Output Delay
tPHQV
RST# High to Output Delay
tEHQZ, tGHQZ
CE# or OE# to Output in High Z, Whichever Occurs First
2
tELQX
CE# to Output in Low Z
2
0
ns
tGLQX
OE# to Output in Low Z
2
0
ns
tOH
Output Hold from First Occurring Address, CE# or OE# change
2
0
ns
tAVEL, tAVGL
Address Setup to CE#, OE# Going Low
for Reading Status Register
4, 6
10
ns
tELAX, tGLAX
Address Hold from CE#, OE# Going Low
for Reading Status Register
5, 6
30
ns
tEHEL, tGHGL
CE#, OE# Pulse Width High for Reading
Status Register
6
25
ns
80
3
3
ns
80
ns
80
ns
35
ns
20
ns
150
ns
20
ns
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to tELQV  tGLQV after the falling edge of CE# without impact to tELQV.
4. Address setup time (tAVEL, tAVGL) is defined from the falling edge of CE# or OE# (whichever goes low last).
5. Address hold time (tELAX, tGLAX) is defined from the falling edge of CE# or OE# (whichever goes low last).
6. Specifications tAVEL, tAVGL, tELAX, tGLAX and tEHEL, tGHGL for read operations apply to only status register read
operations.
Rev. 2.44
LHF32FDJ
VIH
A20-0 (A)
22
VALID
ADDRESS
tAVAV
VIL
tEHQZ
tGHQZ
tAVQV
tEHEL
VIH
CE# (E)
VIL
tAVEL
tELAX
tAVGL
tGHGL
tGLAX
VIH
OE# (G)
VIL
tELQV
VIH
WE# (W)
VIL
tGLQV
tGLQX
tOH
tOH
tELQX
VOH
DQ15-0 (D/Q)
High Z
VALID
OUTPUT
VOL
tPHQV
RST# (P)
VIH
VIL
Figure 7. AC Waveform for Single Asynchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 2.44
LHF32FDJ
A20-3 (A)
VIH
23
VALID
ADDRESS
VIL
tAVAV
tAVQV
A2-0 (A)
CE# (E)
VIH
VALID
ADDRESS
VALID
ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
VIH
VIL
tELQV
OE# (G)
WE# (W)
tEHQZ
tGHQZ
VIH
VIL
VIH
tGLQV
VIL
tGLQX
tAPA
tELQX
DQ15-0 (D/Q)
VOH
High Z
VALID
OUTPUT
VOL
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
tPHQV
RST# (P)
VIH
VIL
Figure 8. AC Waveform for Asynchronous 4-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 2.44
LHF32FDJ
A20-3 (A)
VIH
24
VALID
ADDRESS
VIL
tAVAV
tAVQV
A2-0 (A)
CE# (E)
VIH
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VIH
VIL
tEHQZ
tGHQZ
tELQV
OE# (G)
WE# (W)
VIH
VIL
VIH
tGLQV
VIL
tGLQX
tAPA
tELQX
DQ15-0 (D/Q)
VOH
High Z
VOL
VALID
OUTPUT
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tPHQV
RST# (P)
VIH
VIL
Figure 9. AC Waveform for Asynchronous 8-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 2.44
LHF32FDJ
25
1.2.5 AC Characteristics - Write Operations(1), (2)
VCC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
Parameter
tAVAV
Write Cycle Time
tPHWL (tPHEL)
RST# High Recovery to WE# (CE#) Going Low
tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Going Low
tWLWH (tELEH)
WE# (CE#) Pulse Width
tDVWH (tDVEH)
Notes
Min.
Max.
Unit
80
ns
150
ns
0
ns
4
55
ns
Data Setup to WE# (CE#) Going High
8
40
ns
tAVWH (tAVEH)
Address Setup to WE# (CE#) Going High
8
50
ns
tWHEH (tEHWH)
CE# (WE#) Hold from WE# (CE#) High
0
ns
tWHDX (tEHDX)
Data Hold from WE# (CE#) High
0
ns
tWHAX (tEHAX)
Address Hold from WE# (CE#) High
0
ns
tWHWL (tEHEL)
WE# (CE#) Pulse Width High
5
25
ns
tSHWH (tSHEH)
WP# High Setup to WE# (CE#) Going High
3
0
ns
tVVWH (tVVEH)
VPP Setup to WE# (CE#) Going High
3
200
ns
tWHGL (tEHGL)
Write Recovery before Read
30
ns
tQVSL
WP# High Hold from Valid SRD
3, 6
0
ns
tQVVL
VPP Hold from Valid SRD
3, 6
0
ns
tWHR0 (tEHR0)
WE# (CE#) High to SR.7 Going "0"
3, 7
3
tAVQV+
50
ns
NOTES:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and
OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.
5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
6. VPP should be held at VPP=VPPH1/2 until determination of block erase, full chip erase, (page buffer) program or OTP
program success (SR.1/3/4/5=0).
7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.
8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
configuration.
Rev. 2.44
LHF32FDJ
NOTE 1
A20-0 (A)
VIH
VIL
NOTE 2
NOTE 3
VALID
ADDRESS
VALID
ADDRESS
tAVAV
CE# (E)
tAVWH (tAVEH)
NOTES 5, 6
VIL
tWHEH (tEHWH)
tWHGL (tEHGL)
NOTES 5, 6
VIH
VIL
tWHWL (tEHEL)
VIH
VIL
tWLWH
(tELEH )
DQ15-0 (D/Q)
NOTE 5
VALID
ADDRESS
VIH
tPHWL (tPHEL)
WE# (W)
NOTE 4
tWHAX
(tEHAX)
tELWL (tWLEL)
OE# (G)
26
tWHQV1,2,3 (tEHQV1,2,3)
tWHDX (tEHDX)
tDVWH (tDVEH)
VIH
VIL
DATA IN
VALID
SRD
DATA IN
tWHR0 (tEHR0)
SR.7 (R)
"1"
"0"
RST# (P)
WP# (S)
VIH
VIL
tSHWH (tSHEH)
tQVSL
tVVWH (tVVEH)
tQVVL
VIH
VIL
VPPH1,2
VPP (V)
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.
Figure 10. AC Waveform for Write Operations
Rev. 2.44
LHF32FDJ
27
1.2.6 Reset Operations
tPHQV
RST#
VIH
(P)
VIL
V
DQ15-0 (D/Q) OH
VOL
tPLPH
High Z
VALID
OUTPUT
(A) Reset during Read Array Mode
SR.7="1"
tPLRH
RST#
VIH
VIL
(P)
V
DQ15-0 (D/Q) OH
VOL
ABORT
COMPLETE
tPHQV
tPLPH
High Z
VALID
OUTPUT
(B) Reset during Erase or Program Mode
VCC(min)
VCC
tVHQV
GND
t2VPH
RST#
(P)
tPHQV
VIH
VIL
V
DQ15-0 (D/Q) OH
VOL
High Z
VALID
OUTPUT
(C) RST# rising timing
Figure 11. AC Waveform for Reset Operations
Reset AC Specifications (VCC=2.7V-3.6V, TA=-40°C to +85°C)
Symbol
Parameter
Notes
Min.
100
tPLPH
RST# Low to Reset during Read
(RST# should be low during power-up.)
1, 2, 3
tPLRH
RST# Low to Reset during Erase or Program
1, 3, 4
t2VPH
VCC 2.7V to RST# High
1, 3, 5
tVHQV
VCC 2.7V to Output Delay
3
Max.
Unit
ns
22
100
µs
ns
1
ms
NOTES:
1. A reset time, tPHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for tPHQV.
2. tPLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and
also has been in stable there.
Rev. 2.44
LHF32FDJ
28
1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)
VCC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
Parameter
Page Buffer
Command is
Notes
Used or not
Used
VPP=VPPH1
(In System)
VPP=VPPH2
(In Manufacturing)
Unit
Min. Typ.(1) Max.(2) Min. Typ.(1) Max.(2)
tWPB
4K-Word Parameter Block
Program Time
2
Not Used
0.05
0.3
0.04
0.12
s
2
Used
0.03
0.12
0.02
0.06
s
tWMB
32K-Word Main Block
Program Time
2
Not Used
0.38
2.4
0.31
1.0
s
2
Used
0.24
1.0
0.17
0.5
s
tWHQV1/
tEHQV1
Word Program Time
2
Not Used
11
200
9
185
µs
2
Used
7
100
5
90
µs
tWHOV1/
tEHOV1
OTP Program Time
2
Not Used
36
400
27
185
µs
tWHQV2/
tEHQV2
4K-Word Parameter Block
Erase Time
2
-
0.3
4
0.2
4
s
tWHQV3/
tEHQV3
32K-Word Main Block
Erase Time
2
-
0.6
5
0.5
5
s
Full Chip Erase Time
2
40
350
33
350
s
tWHRH1/
tEHRH1
(Page Buffer) Program Suspend
Latency Time to Read
4
-
5
10
5
10
µs
tWHRH2/
tEHRH2
Block Erase Suspend
Latency Time to Read
4
-
5
20
5
20
µs
tERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5
-
500
µs
500
NOTES:
1. Typical values measured at VCC=3.0V, VPP=3.0V or 12V, and TA=+25°C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than tERES and its sequence is repeated, the block erase operation may not be finished.
Rev. 2.44
LHF32FDJ
29
2 Related Document Information(1)
Document No.
FUM00701
Document Name
LH28F320BF series Appendix
NOTE:
1. International customers should contact their local SHARP or distribution sales offices.
Rev. 2.44
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
t2VPH
tPHQV
VIH
RP# (P)
(RST#)
VCCW *1 (V)
VIL
VCCWH1/2
(VPPH1/2)
GND
(VPP)
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tF
tR
tELQV
VIH
CE#
(E)
VIL
VIH
WE# (W)
VIL
tF
tR
tGLQV
VIH
OE#
(G)
VIL
VIH
WP#
(S)
VIL
VOH
DATA (D/Q)
VOL
High Z
Valid
Output
*1 To prevent the unwanted writes, system designers should consider the design, which applies VCCW (VPP)
to 0V during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
Min.
Max.
Unit
1
0.5
30000
µs/V
tVR
VCC Rise Time
tR
Input Signal Rise Time
1, 2
1
µs/V
tF
Input Signal Fall Time
1, 2
1
µs/V
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, VPP Electric Potential Switching Circuit
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
v
A-3 STATUS REGISTER READ OPERATIONS
If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the
status register bit SR.15 instead of SR.7 to determine when the erase or program operation has been completed.
Table A-3-1. Status Register Definition (SR.15 and SR.7)
NOTES:
SR.15 = WRITE STATE MACHINE STATUS: (DQ15)
1 = Ready in All Partitions
0 = Busy in Any Partition
SR.15 indicates the status of WSM (Write State
Machine). If SR.15="0", erase or program operation is in
progress in any partition.
SR.7 = WRITE STATE MACHINE STATUS
FOR EACH PARTITION: (DQ 7)
1 = Ready in the Addressed Partition
0 = Busy in the Addressed Partition
SR.7 indicates the status of the partition. If SR.7="0",
erase or program operation is in progress in the addressed
partition. Even if the SR.7 is "1", the WSM may be
occupied by the other partition.
Operation to Partition 2
Operation to Partition 0
Address (A)
CE# (E)
WE# (W)
DQ15-0 (D/Q)
VIH
VIL
VIH
VALID ADDRESS
within PARTITION 2
VALID ADDRESS
within PARTITION 0
VIL
VIH
VIL
VIH
VIL
VALID
COMMAND
VALID
COMMAND
tWHR0 (tEHR0)
SR.15
(R)
( Partition 0 )
SR.7
(R)
( Partition 0 )
SR.15
(R)
( Partition 1 )
SR.7
(R)
( Partition 1 )
SR.15
(R)
( Partition 2 )
SR.7
(R)
( Partition 2 )
SR.15
(R)
( Partition 3 )
SR.7
(R)
( Partition 3 )
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
tWHR0 (tEHR0)
"0"
"1"
"0"
"1"
"0"
"1"
"0"
PLANE0
PLANE1
PLANE2
PLANE3
PARTITION3 PARTITION2 PARTITION1 PARTITION0
Check SR.15 instead of
SR.7 in Partition 0
Check SR.15 instead of
SR.7 in Partition 2
Figure A-3-1. Example of Checking the Status Register
(In this example, the device contains four partitions.)
021211
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