T6K01 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6K01 COLUMN DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD The T6K01 is a column (segment) driver for a dot matrix graphic LCD. The T6K01 offers low power consumption, due to the CMOS Si-Gate process. It is designed to interface directly with a microprocessor unit (MPU). A program running on the MPU can drive the T6K01 asynchronously. The T6K01 stores data transferred from the MPU in its built-in RAM. The data stored in the built-in display RAM corresponds to the image on the LCD screen; the data is converted into the LCD drive signal. A configuration of two T6K01s and one T6C03 can be used to drive a 480 × 160-dot LCD. Features l Dot matrix graphic LCD column driver with display RAM l Display RAM capacity: 160 lines × 240 outputs = 38400 bits l LCD drive output: 240 l Interface: 8-bit MPU l Relation between RAM data and display RAM bit data = 1 → display ON RAM bit data = 0 → display OFF l Display OFF function l Low power consumption l Logic power supply: 2.7 to 3.3 V l LCD power supply: 8.0 to 26.0 V l CMOS Process l Package: TCP (Tape Carrier Package) 1 2002-01-07 T6K01 Block Diagram 2 2002-01-07 T6K01 Pin Assignment Note: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package. 3 2002-01-07 T6K01 Pin Functions Pin Name Pin No. I/O SEG1 to SEG240 46 to 285 Output CL 10 Input Shift clock pulse FP 11 Input Display synchronous signal FR Functions Column driver outputs 12 Input Frame signal DB0 to DB7 13 to 20 I/O Data bus AD0 to AD12 21 to 33 Input Address bus R/W 34 Input Read / write select R / W = H → Read selected R / W = L → Write selected / CE 35 Input Chip enable Data write: Data write enabled on rising edge of / CE Data read: Data read out while / CE is at L level / DSPOF 36 Input Display off. Usually connected to VDD. / DSPOF = H: Display−on mode. (SEG1 to SEG240) are operational. / DSPOF = L: Display−off mode. (SEG1 to SEG240) are at the VSS level. / RST 37 Input Reset signal: / RST = L → Reset state DIR 38 Input Data direction select / TEST1, 2 8, 9 Input Test pin. Usually connected to VDD VDD, VSS 7, 39 ― Power supply VCCL, VCCR VLC0L, VLC0R VLC2L, VLC2R VLC3L, VLC3R VLC5L, VLC5R HVSSL, HVSSR 1, 45 2, 44 3, 43 4, 42 5, 41 6, 40 ― Power supply for LCD drive 4 2002-01-07 T6K01 Function of Each Block ● RAM cell The RAM capacity is 160 lines × 240 outputs for a total of 38400 bits. ● DIR This circuit changes the data flow direction and page selection sequence. ● Address decoder This decoder selects one RAM address for read / write operation. ● 8-bit counter + decoder The decoder selects one RAM cell from the 160 address lines for display operation. ● Latch The data is latched from the display RAM on the falling edge of CL. ● Column driver circuit and LCD voltage generation circuit The T6K01 has 240 column drivers and four different LCD drive output voltage levels. The display data from the latch circuit and the M signal determine which of the four LCD drive voltages is selected. This circuit is shown in the following diagram. Relation Between FR, Data Input and Output Level / DSPOF FR Input Data (RAM Data) Output Level L * * VSS / VLC5 H L L VLC3 H L H VSS / VLC5 H H L VLC2 H H H VLC0 *: INVALID 5 2002-01-07 T6K01 ● The relation between DIR and the memory map (1) DIR = H 6 2002-01-07 T6K01 (2) DIR = L 7 2002-01-07 T6K01 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Supply Voltage (1) VDD (Note 2) −0.3 to 6.5 V Supply Voltage (2) (Note 1, 2) −0.3 to 28.0 V Input Voltage VIN (Note 2, 3) −0.3 to VDD +0.3 V Operating Temperature Topr −20 to 75 °C Storage Temperature Tstg −55 to 125 °C Note 1: Note 2: Note 3: Note 4: VCCL, VCCR, VLC0L, VLC0R, VLC2L, VLC2R, VLC3L, VLC3R, VLC5L and VLC5R Referenced to VSS, HVSSL and HVSSR Applies to all data bus and I / O pins. Ensure that the following condition is always maintained. VCCL / R ≥ VLC0L / R ≥ VLC2L / R ≥ VLC3L / R ≥ V LC5L / R ≥ HVSSL / R 8 2002-01-07 T6K01 Electrical Characteristics DC Characteristics Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ± 10%, VCCL / R = 23.0 V ± 10%, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Min Typ. Max Unit Operating Supply (1) VDD ― ― 2.7 ― 3.3 V VDD Operating Supply (2) VCC ― ― 8.0 ― 26.0 V VCCL, VCCR H Level VIH ― ― 0.7 VDD ― VDD V L Level VIL ― ― 0 ― 0.3 VDD V H Level VOH ― VDD −0.4 ― VDD V VSS ― 0.4 V ― ― 3.0 kΩ SEG1 to SEG160 Input Voltage Output Voltage L Level Column Driver Output Resistance VOL ― Rcol ― IOH = −400 µA IOL = 400 µA Load current = ±100 µA (Note 4) Pin Name DB0 to DB7 AD0 to AD7, / RST, / DSPOF, / CE, R / W, D / I, CL, FP, FR, DIR, / TEST DB0 to DB7 Input Leakage IIL ― VIN = VDD to VSS −1 ― 1 µA DB0 to DB7 AD0 to AD7, / RST, / DSPOF, / CE, R / W, D / I, CL, FP, FR, DIR, / TEST Operating Freq. fCL ― ― 10 ― 50 kHz CL Current Consumption (1) ISS1 ― (Note 1) ― 410 520 µA VSS, HVSSL, HVSSR, VLC5L, VLC5R Current Consumption (2) ISS2 ― (Note 2) ― 45 65 µA VSS, HVSSL, HVSSR, VLC5L, VLC5R Current Consumption (3) ISS3 ― (Note 3) −1 ― 1 µA VSS, HVSSL, HVSSR, VLC5L, VLC5R Note 1: Current consumption while internal data receiver is operating VDD = 3.0 V ±10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, 1 / 160 duty, no load, fFP = 70 Hz, f / CE = 5 MHz Note 2: Current consumption while internal data receiver is sleeping VDD = 3.0 V ±10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, 1 / 160 duty, no load, fFP = 70 Hz, f / CE = 0 Hz Note 3: Standby current consumption VDD = 3.0 V ±10%, VCCL / R = 23.0 V, Ta = 25°C, no load, fFP = 0 Hz, f / CE = 0 Hz Note 4: VCCL / R = VLC0L / R = 23.0 V, VLC2L / R = VCC × 11 / 13, VLC3L / R = VCC × 2 / 13, HVSSL / R = VLC5L / R = 0 V 9 2002-01-07 T6K01 AC Characteristics (1) Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ±10%, Ta = −20 to 75°C) Item Symbol Min Max Unit Enable Cycle Time tcycE 250 ― ns Enable Pulse Width PWEH 160 ― ns Enable Rise / Fall Time tEr, tEf ― 20 ns Address Set-up Time tAS 0 ― ns Address Hold Time tAH 10 ― ns Data Set-up Time tDS 100 ― ns Data Hold Time tDHW 20 ― ns Data Delay Time tDD (Note) ― 180 ns Data Hold Time tDHR (Note) 20 ― ns Load Circuit Note: With load circuit connected 10 2002-01-07 T6K01 AC Characteristics (2) display data Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = −20 to 75°C) Item Symbol Pin Name Min Max Unit CL Pulse Width H tCWH CL 500 ― ns CL Pulse Width L tCWL CL 500 ― ns CL Rise / Fall Time tr, tf CL ― 50 ns FP Set-up Time tFSU FP 100 ― ns FP Hold Time tFHD FP 100 ― ns AC Characteristics (3) Item Symbol Condition Min Max Unit CL-to-FP-margin time tCF 20 ― ns FP-to-CL-margin time tFC 0 ― ns 11 2002-01-07 T6K01 Application Circuit 12 2002-01-07 T6K01 RESTRICTIONS ON PRODUCT USE 000707EBE · TOSHIBA is continually working to improve the quality and reliability of its products. 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