Preliminary Revised February 2000 74LCXZ16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) General Description Features The LCXZ16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. When VCC is between 0 and 1.5V, the LCXZ16240 is in the high impedance state during power up or power down. This places the outputs in the high impedance (Z) state preventing intermittent low impedance loading or glitching in bus oriented applications. ■ 5V tolerant inputs and outputs The LCXZ16240 is designed for low voltage (2.7V or 3.3V) VCC applications with capacity of interfacing to a 5V signal environment. ■ Guaranteed power up/down high impedance ■ Supports live insertion/withdrawal ■ 2.7V–3.6V VCC specifications provided ■ 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ ±24 mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V The LCXZ16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Code: Order Number Package Number 74LCXZ16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74LCXZ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol Pin Descriptions Pin Names © 2000 Fairchild Semiconductor Corporation DS500257 Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 Outputs www.fairchildsemi.com 74LCXZ16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) February 2000 74LCXZ16240 Preliminary Truth Tables Inputs Outputs Inputs I0–I3 O0–O3 OE3 L L H L H L H X Z OE1 Inputs Outputs I8–I11 O8–O11 L L H L H L H X Z Outputs Inputs Outputs OE2 I4–I7 O4–O7 OE4 I12–I15 O12–O15 L L H L L H L H L L H L H X Z H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Functional Description The LCXZ16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram www.fairchildsemi.com 2 Preliminary Symbol Parameter Value Conditions VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Units V V Output in 3-STATE or VCC = 0–1.5V −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 2) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL (Note 3) Min Max 2.7 3.6 V 0 5.5 V HIGH or LOW State 0 VCC 3-STATE or VCC = OFF 0 5.5 Operating Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 Units V mA −40 85 °C 0 10 ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol Parameter Conditions VCC Min 2.0 VIH HIGH Level Input Voltage 2.7 − 3.6 VIL LOW Level Input Voltage 2.7 − 3.6 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage TA = −40°C to +85°C (V) Max V 0.8 IOH = −100 µA 2.7 − 3.6 VCC − 0.2 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 2.2 Units V V IOH = −24 mA 3.0 IOL = 100 µA 2.7 − 3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 0.55 V IOL = 24 mA 3.0 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.7 − 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 5.5V 2.7 − 3.6 ±5.0 µA IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µA IPU/PD Power Up/Down VO = 0.5V to VCC 3-STATE Output Current VI = GND or VCC 0 − 1.5 ±5.0 µA VI = V IH or VIL ICC ∆ICC Quiescent Supply Current Increase in ICC per Input VI = V CC or GND 2.7 − 3.6 225 3.6V ≤ VI, VO ≤ 5.5V (Note 4) 2.7 − 3.6 ±225 VIH = VCC −0.6V 2.7 − 3.6 500 µA µA Note 4: Outputs disabled or 3-STATE only. 3 www.fairchildsemi.com 74LCXZ16240 Absolute Maximum Ratings(Note 1) 74LCXZ16240 Preliminary AC Electrical Characteristics TA = −40°C to +85°C, RL = 500 Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V CL = 50 pF CL = 50 pF Units Min Max Min tPHL Propagation Delay 1.5 4.5 1.5 5.3 tPLH Data to Output 1.5 4.5 1.5 5.3 tPZL Output Enable Time 1.5 5.4 1.5 6.0 1.5 5.4 1.5 6.0 1.5 5.3 1.5 5.4 1.5 5.3 1.5 5.4 tPZH tPLZ Output Disable Time tPHZ tOSHL Output to Output Skew (Note 5) Max 1.0 tOSLH ns ns ns ns 1.0 Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol Parameter Conditions VCC (V) TA = 25°C Unit Typical VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF www.fairchildsemi.com Conditions 4 Preliminary 74LCXZ16240 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) VI CL 6V for VCC = 3.3V, 2.7V 50 pF VCC * 2 for VCC = 2.5V 30 pF Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V Vmi 1.5V 1.5V Vmo 1.5V 1.5V Vx VOL + 0.3V VOL + 0.3V Vy VOH − 0.3V VOH − 0.3V 5 www.fairchildsemi.com 74LCXZ16240 Preliminary Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 Preliminary 74LCXZ16240 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A 7 www.fairchildsemi.com 74LCXZ16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) Preliminary Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8