Intersil HI5762 Dual 10-bit, 60msps a/d converter with internal voltage reference Datasheet

HI5762
Data Sheet
February 1999
Dual 10-Bit, 60MSPS A/D Converter with
Internal Voltage Reference
Features
The HI5762 is a monolithic, dual 10-bit, 60MSPS analog-todigital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. Built by combining
two cores of the HI5767 single channel 10-bit 60MSPS
analog-to-digital converter, the HI5762 reaches a new level
of multi-channel integration. The fully pipeline architecture
and an innovative input stage enable the HI5762 to accept a
variety of input configurations, single-ended or fully
differential. Only one external clock is necessary to drive
both converters and an internal band-gap voltage reference
is provided. This allows the system designer to realize an
increased level of system integration resulting in decreased
cost and power dissipation.
• 8.8 Bits at fIN = 10MHz
The HI5762 has excellent dynamic performance while
consuming only 650mW of power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.
For those customers needing dual channel 8-bit resolution,
please refer to the HI5662. For single channel 10-bit
applications, please refer to the HI5767.
Ordering Information
• On-Chip Sample and Hold Amplifiers
• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V
• Fully Differential or Single-Ended Analog Inputs
• Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Sampling Clock Input
• CMOS Compatible Digital Outputs . . . . . . . . . . . . 3.0/5.0V
• Offset Binary Digital Data Output Format
• Dual 10-Bit A/D Converters on a Monolithic Chip
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging
• High Speed Data Acquisition
QVDC
QIN-
QIN+
AVCC1
VROUT
NC
VRIN
44 43 42 41 40 39 38 37 36 35 34
33
2
32
AVCC2
ID9
3
31
QD9
ID8
4
30
QD8
ID7
5
29
QD7
ID6
6
28
QD6
ID5
7
27
QD5
DVCC3
8
26
DVCC3
DGND
9
25
DGND
ID4
10
24
QD4
ID3
11
23
12 13 14 15 16 17 18 19 20 21 22
QD3
AGND
QD2
QD1
QD0
DGND
DVCC2
CLK
AVCC2
1
DVCC1
AGND
17
AGND
Evaluation Platform
IIN+
Q44.10x10
DGND
44 Ld MQFP
HI5762 (MQFP)
TOP VIEW
PKG. NO.
IIN-
PACKAGE
ID0
25
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
IVDC
HI5762EVAL2
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
Pinout
TEMP.
RANGE (oC)
-40 to 85
• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW
ID1
HI5762/6IN
4318.2
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS
ID2
PART
NUMBER
File Number
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HI5762
Functional Block Diagram
I/QIN-
I/QVDC
BIAS
I/QIN+
S/H
STAGE 1
2-BIT
FLASH
2-BIT
DAC
+
∑
DVCC3
X2
I/QD9 (MSB)
I/QD8
I/QD7
I/QD6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
I/QD5
I/QD4
I/QD3
2-BIT
FLASH
2-BIT
DAC
I/QD2
I/QD1
+
∑
I/QD0 (LSB)
-
X2
STAGE 9
2-BIT
FLASH
I or Q CHANNEL
VREFOUT
CLOCK
REFERENCE
VREFIN
AVCC1,2
18
AGND
DVCC1,2
DGND
CLK
HI5762
Typical Application Schematic
HI5762
IIN +
(42) IIN +
(44) IVDC
IIN -
(43) IIN -
QIN +
(36) QIN +
(34) QVDC
QIN -
(35) QIN -
(40) VRIN
(38) VROUT
(LSB) ID0 (14)
ID0
ID1 (13)
ID1
ID2 (12)
ID2
ID3 (11)
ID3
ID4 (10)
ID4
ID5 (7)
ID5
ID6 (6)
ID6
ID7 (5)
ID7
ID8 (4)
ID8
(MSB) ID9 (3)
ID9
(LSB) QD0 (20)
QD0
QD1 (21)
QD1
QD2 (22)
QD2
QD3 (23)
QD3
QD4 (24)
QD4
QD5 (27)
QD5
QD6 (28)
QD6
QD7 (29)
QD7
QD8 (30)
QD8
(MSB) QD9 (31)
QD9
0.1µF
CLK (17)
CLOCK
DVCC3 (8,26)
+
10µF
+5V or +3V
0.1µF
+
10µF
+5V
0.1µF
(39) NC
+5V
+
10µF
(37) AVCC1
DVCC2 (18)
(2,32) AVCC2
DVCC1 (16)
0.1µF
(1,33,41) AGND
BNC AGND DGND
19
DGND (9,15,19,25)
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
HI5762
Pin Descriptions
PIN NO.
NAME
1
AGND
2
AVCC2
3
DESCRIPTION
PIN NO.
NAME
Analog Ground
24
QD4
Analog Supply (+5.0V)
25
DGND
Digital Ground
ID9
I-Channel, Data Bit 9 Output (MSB)
26
DVCC3
4
ID8
I-Channel, Data Bit 8 Output
Digital Output Supply
(+3.0V or +5.0V)
5
ID7
I-Channel, Data Bit 7 Output
27
QD5
Q-Channel, Data Bit 5 Output
6
ID6
I-Channel Data Bit 6 Output
28
QD6
Q-Channel, Data Bit 6 Output
7
ID5
I-Channel, Data Bit 5 Output
29
QD7
Q-Channel, Data Bit 7 Output
8
DVCC3
30
QD8
Q-Channel, Data Bit 8 Output
31
QD9
Q-Channel, Data Bit 9 Output
(MSB)
32
AVCC2
Analog Supply (+5.0V)
33
AGND
Analog Ground
34
QVDC
Q-Channel DC Bias Voltage Output
35
QIN-
Q-Channel Negative Analog Input
36
QIN+
Q-Channel Positive Analog Input
37
AVCC1
Analog Supply (+5.0V)
38
VROUT
+2.5V Reference Voltage Output
39
NC
40
VRIN
+2.5V Reference Voltage Input
41
AGND
Analog Ground
42
IIN+
I-Channel Positive Analog Input
43
IIN-
I-Channel Negative Analog Input
44
IVDC
Digital Output Supply
(+3.0V or +5.0V)
9
DGND
Digital Ground
10
ID4
I-Channel, Data Bit 4 Output
11
ID3
I-Channel, Data Bit 3 Output
12
ID2
I-Channel, Data Bit 2 Output
13
ID1
I-Channel, Data Bit 1 Output
14
ID0
I-Channel, Data Bit 0 Output (LSB)
15
DGND
Digital Ground
16
DVCC1
Digital Supply (+5.0V)
17
CLK
18
DVCC2
Digital Supply (+5.0V)
19
DGND
Digital Ground
20
QD0
Q-Channel, Data Bit 0 Output (LSB)
21
QD1
Q-Channel, Data Bit 1 Output
22
QD2
Q-Channel, Data Bit 2 Output
23
QD3
Q-Channel, Data Bit 3 Output
Sample Clock Input
20
DESCRIPTION
Q-Channel, Data Bit 4 Output
No Connect
I-Channel DC Bias Voltage Output
HI5762
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
HI5762/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
Temperature Range
HI5762/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
10
-
-
Bits
Integral Linearity Error, INL
fIN = 10MHz
-
2
-
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 10MHz
-
±0.4
±1.0
LSB
Offset Error, VOS
fIN = DC
-40
-
+40
LSB
Full Scale Error, FSE
fIN = DC
-
4
-
LSB
Minimum Conversion Rate
No Missing Codes
-
1
-
MSPS
Maximum Conversion Rate
No Missing Codes
60
-
-
MSPS
Effective Number of Bits, ENOB
fIN = 10MHz
8.4
8.8
-
Bits
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
fIN = 10MHz
-
54.7
-
dB
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
fIN = 10MHz
-
54.7
-
dB
Total Harmonic Distortion, THD
fIN = 10MHz
-
-68
-
dBc
2nd Harmonic Distortion
fIN = 10MHz
-
-70
-
dBc
3rd Harmonic Distortion
fIN = 10MHz
-
-73
-
dBc
Spurious Free Dynamic Range, SFDR
fIN = 10MHz
-
70
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
64
-
dBc
I/Q Channel Crosstalk
-
-75
-
dBc
I/Q Channel Offset Match
-
10
-
LSB
I/Q Channel Full Scale Error Match
-
10
-
LSB
DYNAMIC CHARACTERISTICS
Transient Response
(Note 2)
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
1
-
Cycle
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-)
-
±0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
-
1
-
MΩ
ANALOG INPUT
Analog Input Resistance, RIN+ or RIN-
21
VIN+, VIN- = VREF, DC
HI5762
Electrical Specifications
AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
10
-
pF
VIN+, VIN- = VREF-, VREF+,DC
(Note 2, 3)
-10
-
10
µA
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
(Note 2, 3)
-0.5
-
+0.5
µA
Full Power Input Bandwidth, FPBW
(Note 2)
-
250
-
MHz
Analog Input Common Mode Voltage Range
(VIN+ + VIN-) / 2
Differential Mode (Note 2)
0.25
-
4.75
V
2.35
2.5
2.65
V
Analog Input Capacitance, CIN+ or CIN-
VIN+, VIN- = 2.5V, DC
Analog Input Bias Current, IB+ or IB-
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT (Loaded)
Reference Output Current, IROUT
-
2
4
mA
Reference Temperature Coefficient
-
-400
-
ppm/oC
REFERENCE VOLTAGE INPUT
-
2.5
-
V
Total Reference Resistance, RRIN
with VRIN = 2.5V
-
1.25
-
kΩ
Reference Current, IRIN
with VRIN = 2.5V
-
2
-
mA
DC Bias Voltage Output, VDC
-
3.0
-
V
Maximum Output Current
-
-
0.4
mA
Reference Voltage Input, VRIN
DC BIAS VOLTAGE
SAMPLING CLOCK INPUT
Input Logic High Voltage, VIH
CLK
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK
-
-
0.8
V
Input Logic High Current, IIH
CLK, VIH = 5V
-10.0
-
+10.0
µA
Input Logic Low Current, IIL
CLK, VIL = 0V
-10.0
-
+10.0
µA
Input Capacitance, CIN
CLK
-
7
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100µA; DVCC3 = 5V
4.0
-
-
V
Output Logic Low Voltage, VOL
IOL = 100µA; DVCC3 = 5V
-
-
0.8
V
Output Logic High Voltage, VOH
IOH = 100µA; DVCC3 = 3V
2.4
-
-
V
Output Logic Low Voltage, VOL
IOL = 100µA; DVCC3 = 3V
-
-
0.5
V
-
7
-
pF
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Hold, tH
-
10.7
-
ns
Data Output Delay, tOD
-
11.7
-
ns
Output Capacitance, COUT
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample (Note 2)
6
6
6
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
20
Cycles
Sample Clock Pulse Width (Low)
(Note 2)
7.5
8.3
-
ns
Sample Clock Pulse Width (High)
(Note 2)
7.5
8.3
-
ns
-
±5
-
%
4.75
5.0
5.25
V
Sample Clock Duty Cycle Variation
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
(Note 2)
22
HI5762
Electrical Specifications
AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)
MIN
TYP
MAX
UNITS
Digital Supply Voltage, DVCC1 and DVCC2
PARAMETER
(Note 2)
TEST CONDITIONS
4.75
5.0
5.25
V
Digital Output Supply Voltage, DVCC3
At 3.0V (Note 2)
2.7
3.0
3.3
V
At 5.0V (Note 2)
4.75
5.0
5.25
V
-
130
-
mA
-
650
670
mW
Supply Current, ICC
fS = 60MSPS
Power Dissipation
Offset Error Sensitivity, ∆VOS
AVCC or DVCC = 5V ±5%
-
±0.5
-
LSB
Gain Error Sensitivity, ∆FSE
AVCC or DVCC = 5V ±5%
-
±0.6
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
SN + 1
H N + 1 SN + 2
SN + 5 HN + 5
SN + 6 H N + 6 SN + 7
H N + 7 SN + 8
HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1 , N - 1
B2 , N - 2
9TH
STAGE
B1 , N
B2 , N - 1
B9 , N - 5
DATA
OUTPUT
B1 , N + 1
B1 , N + 5
B2 , N + 4
B2 , N
B9 , N - 4
DN - 6
B1 , N + 4
B9 , N
DN - 5
B2 , N + 5
B9 , N + 1
DN - 1
tLAT
NOTES:
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM , N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. HI5762 INTERNAL CIRCUIT TIMING
23
B1 , N + 6
B1 , N + 7
B2 , N + 6
B9 , N + 2
DN
B9 , N + 3
DN + 1
DN + 2
HI5762
Timing Waveforms
(Continued)
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
2.4V
DATA
OUTPUT
DATA N
DATA N-1
0.5V
FIGURE 2. HI5762 INPUT-TO OUTPUT TIMING
Typical Performance Curves
9
56
56
fS = 60MSPS
TA = 25oC
50
50
7
44
44
38
100
38
6
1
10
SNR (dB)
8
SINAD (dB)
ENOB (BITS)
fS = 60MSPS
TA = 25oC
1
10
INPUT FREQUENCY (MHz)
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND
SINAD vs INPUT FREQUENCY
FIGURE 4. SNR vs INPUT FREQUENCY
90
70
fS = 60MSPS
TA = 25oC
85
-2HD
100
INPUT FREQUENCY (MHz)
60
fS = 60MSPS
fIN = 10MHz
TA = 25oC
80
-3HD
50
70
dB
dBc
75
40
65
-THD (dBc)
-THD
60
30
SNR (dB)
55
50
SINAD (dB)
1
10
100
INPUT FREQUENCY (MHz)
FIGURE 5. -THD, -2HD AND -3HD vs INPUT FREQUENCY
24
20
-40
-30
-20
-10
INPUT LEVEL (dBFS)
FIGURE 6. SINAD, SNR AND -THD vs INPUT AMPLITUDE
0
HI5762
Typical Performance Curves
(Continued)
fS = 60MSPS
1MHz < fIN < 15MHz
TA = 25oC
ENOB (BITS)
8
7
6
5
40
42
44
46
48
50
52
54
56
58
60
SUPPLY CURRENT (mA)
9
150
140 1MHz < fIN < 15MHz
130 TA = 25oC
120
110
100
90
AICC
80
70
60
50
40
30
20
10
0
10
20
30
DUTY CYCLE (%, tHI /tCLK)
ENOB (BITS)
8.0
7.5
-20
0
20
40
60
80
INTERNAL REFERENCE VOLTAGE, VROUT (V)
fS = 60MSPS
fIN = 10MHz
8.5
7.0
-40
40
50
DICC2
60
70
2.50
2.49
2.48
2.47
2.46
VROUT
2.45
2.44
2.43
2.42
2.41
2.40
-40
-20
0
TEMPERATURE (oC)
20
40
60
80
TEMPERATURE (oC)
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE
FIGURE 10. INTERNAL REFERENCE VOLTAGE (VROUT) vs
TEMPERATURE
3.10
13.0
3.05
12.5
3.00
tOD (ns)
DC BIAS VOLTAGE, I/QVDC (V)
DICC3
FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK
FREQUENCY
9.0
I CHANNEL
DICC1
fS (MSPS)
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE
Q CHANNEL
ICC
QVDC
2.95
tOD
12.0
IVDC
11.5
2.90
2.85
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 11. DC BIAS VOLTAGE (I/QVDC) vs TEMPERATURE
25
11.0
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 12. DATA OUTPUT DELAY (tOD) vs TEMPERATURE
HI5762
Typical Performance Curves
(Continued)
0
140
ICC
fS = 60MSPS
1MHz < fIN < 15MHz
-20
100
-30
-40
80
AICC
dB
SUPPLY CURRENT (mA)
120
fS = 60MSPS
fIN = 10MHz
TA = 25oC
-10
60
-50
-60
-70
DICC1
40
-80
20
DICC2
DICC3
0
-40
-90
-100
-20
0
20
40
60
80
0
100
200
300
TEMPERATURE (oC)
400
500
600
700
800
900
1023
FREQUENCY (BIN)
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
FIGURE 14. 2048 POINT FFT PLOT
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL INPUT
VOLTAGE
(I/QIN+ - I/QIN-)
CODE CENTER
DESCRIPTION
+Full Scale (+FS) -1/4 LSB
+FS - 11/4 LSB
+3/4 LSB
-1/4 LSB
-FS + 13/4 LSB
-Full Scale (-FS) + 3/4 LSB
MSB
LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
0.499756V
1
1
1
1
1
1
1
1
1
1
0.498779V
1
1
1
1
1
1
1
1
1
0
732.422µV
1
0
0
0
0
0
0
0
0
0
-244.141µV
0
1
1
1
1
1
1
1
1
1
-0.498291V
0
0
0
0
0
0
0
0
0
1
-0.499268V
0
0
0
0
0
0
0
0
0
0
NOTE:
8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.
Detailed Description
Theory of Operation
The HI5762 is a dual 10-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a nonoverlapping two phase signal, Φ1 and Φ2 , derived from the
master sampling clock. During the sampling phase, Φ1 , the
input signal is applied to the sampling capacitors, CS . At the
same time the holding capacitors, CH , are discharged to
analog ground. At the falling edge of Φ1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, Φ2 , the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between CS and CH completing one
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
26
hold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the I/QIN pins see only the on-resistance of a
switch and CS . The relatively small values of these
components result in a typical full power input bandwidth of
250MHz for the converter.
Φ1
I/QIN+
Φ1
Φ1
Φ1
CS
Φ2
I/QIN-
CH
-+
VOUT+
+-
VOUT-
CS
Φ1
CH
Φ1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
HI5762
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VREFOUT
The HI5762 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. VROUT must be connected to VRIN when using the
internal reference voltage.
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference voltage
used by the converter. A band-gap reference circuit is used to
generate a precision +1.25V internal reference voltage. This
voltage is then amplified by a wide-band uncompensated
operational amplifier connected in a gain-of-two configuration.
An external, user-supplied, 0.1µF capacitor connected from the
VROUT output pin to analog ground is used to set the dominant
pole and to maintain the stability of the operational amplifier.
Reference Voltage Input, VREFIN
The HI5762 is designed to accept a +2.5V reference voltage
source at the VRIN input pin. Typical operation of the
converter requires VRIN to be set at +2.5V. The HI5762 is
tested with VRIN connected to VROUT yielding a fully
differential analog input voltage range of ±0.5V.
27
The user does have the option of supplying an external +2.5V
reference voltage. As a result of the high input impedance
presented at the VRIN input pin, 1.25kΩ typically, the external
reference voltage being used is only required to source 2mA
of reference input current. In the situation where an external
reference voltage will be used an external 0.1µF capacitor
must be connected from the VROUT output pin to analog
ground in order to maintain the stability of the internal
operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VRIN .
Analog Input, Differential Connection
The analog input of the HI5762 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.
I/QIN+
VIN
R
HI5762
I/QVDC
R
-VIN
I/QIN-
FIGURE 16. AC COUPLED DIFFERENTIAL INPUT
Since the HI5762 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, I/QVDC , equal to 3.0V (typical), is
made available to the user to help simplify circuit design
when using an AC coupled differential input. This low output
impedance voltage source is not designed to be a reference
but makes an excellent DC bias source and stays well within
the analog input common mode voltage range over
temperature.
For the AC coupled differential input (Figure 16) and with VRIN
connected to VROUT, full scale is achieved when the VIN and
-VIN input signals are 0.5VP-P, with -VIN being 180 degrees
out of phase with VIN . The converter will be at positive full
scale when the I/QIN+ input is at VDC + 0.25V and the I/QINinput is at VDC - 0.25V (I/QIN+ - I/QIN- = +0.5V). Conversely,
the converter will be at negative full scale when the I/QIN+
input is equal to VDC - 0.25V and I/QIN- is at
VDC + 0.25V (I/QIN+ - I/QIN- = -0.5V).
HI5762
The analog input can be DC coupled (Figure 17) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 4.75V).
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
VIN
I/QIN+
VDC
R
C
HI5762
I/QVDC
R
-VIN
VDC
I/QIN-
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
Analog Input, Single-Ended Connection
The configuration shown in Figure 18 may be used with a
single ended AC coupled input.
The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
VIN
I/QIN+
VDC
R
HI5762
C
VDC
I/QIN-
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5762.
Sampling Clock Requirements
I/QIN+
VIN
The HI5762 sampling clock input provides a standard highspeed interface to external TTL/CMOS logic families.
R
HI5762
VDC
I/QIN-
FIGURE 18. AC COUPLED SINGLE ENDED INPUT
Again, with VRIN connected to VROUT, if VIN is a 1VP-P
sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at positive
full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ - I/QIN- = +0.5V)
and will be at negative full scale when I/QIN+ is equal to
VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient headroom must
be provided such that the input voltage never goes above +5V
or below AGND. In this case, VDC could range between 0.5V
and 4.5V without a significant change in ADC performance.
The simplest way to produce VDC is to use the DC bias source,
I/QVDC, output of the HI5762.
In order to ensure rated performance of the HI5762, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL/CMOS levels.
Performance of the HI5762 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must be performed
before valid data is available.
Supply and Ground Considerations
The HI5762 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DVCC3 , which can be powered from a 3.0V or 5.0V
supply. This allows the outputs to interface with 3.0V logic if
so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5762 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
28
HI5762
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input
that is 3/4 LSB below Positive Full Scale (+FS) with the
offset error removed. Full scale error is defined as the
deviation of the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5762. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is typically -0.5dB down
from full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers
are quoted in dBc (decibels with respect to carrier) and DO
NOT include any correction factors for normalizing to full
scale.
The Effective Number of Bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
where:
VCORR = 0.5dB (Typ).
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is backed off from full scale.
29
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS
sum of all the other spectral components below the Nyquist
frequency, fS/2, excluding DC.
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS /2
excluding the fundamental, the first five harmonics and DC.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable
harmonic component to the RMS value of the fundamental
input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS /2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2 , are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below
full scale.
Transient Response
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
Over-Voltage Recovery
Over-Voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
HI5762
I/Q Channel Crosstalk
Data Output Delay Time (tOD)
I/Q Channel Crosstalk is a measure of the amount of
channel separation or isolation between the two A/D
converter cores contained within the dual converter
package. The measurement consists of stimulating one
channel of the converter with a fullscale input signal and
then measuring the amount that signal is below, in dBc, a
fullscale signal on the opposite channel.
Data output delay time is the time to where the new data (N)
is valid.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Latency (tLAT)
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus
following the 6th cycle of the clock after the analog sample is
taken. This is due to the pipeline nature of the converter
where the analog sample has to ripple through the internal
subconverter stages. This delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 6 sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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30
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