ICSI IS61C512-25J 64k x 8 high-speed cmos static ram Datasheet

IS61C512
IS61C512
64K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
•
•
•
•
•
•
•
•
Pin compatible with 128K x 8 devices
High-speed access time: 15, 20, 25, 35 ns
Low active power: 500 mW (typical)
Low standby power
— 250 µW (typical) CMOS standby
Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V (±10%) power supply
DESCRIPTION
The ICSI IS61C512 is a very high-speed, low power, 65,536
word by 8-bit CMOS static RAMs. They are fabricated using
ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields higher performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 1 mW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C512 is available in 32-pin 300mil DIP, SOJ and
8*20mm TSOP-1 packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
512 X 1024
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR011-0B
1
IS61C512
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin DIP and SOJ
32-Pin TSOP-1
NC
1
32
VCC
NC
2
31
A15
A14
3
30
CE2
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
GND
16
17
I/O3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN DESCRIPTIONS
A0-A15
CE1
CE2
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CE1
CE2
OE
I/O Operation
Vcc Current
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High-Z
High-Z
High-Z
DOUT
DIN
ISB1, ISB2
ISB1, ISB2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
2
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–10 to +85
–65 to +150
1.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed
under ABSOLUTE MAXIMUM
RATINGS may cause permanent
damage to the device. This is a
stress rating only and functional
operation of the device at these or
any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc.
SR011-0B
IS61C512
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.5
V
–0.3
0.8
V
(1)
VIL
Input LOW Voltage
ILI
Input Leakage
GND ≤ VIN ≤ VCC
–2
2
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–2
2
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-15 ns
Min. Max.
-20 ns
Min. Max.
-25 ns
Min. Max.
-35 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC1
Vcc Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
—
—
70
—
—
—
70
90
—
—
70
90
—
—
70
90
mA
ICC2
Vcc Dynamic Operating
Supply Current
VCC = Max.,
Com.
IOUT = 0 mA, f = fMAX Ind.
—
—
125
—
—
—
115
135
—
—
105
125
—
—
90
115
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE1 ≥ VIH or
CE2 ≤ VIL, f = 0
Com.
Ind.
—
—
25
—
—
—
25
30
—
—
25
30
—
—
25
30
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
CE1 ≥ VCC – 0.2V,
Ind.
CE2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
—
—
750
—
—
—
750
1
—
—
750
1
—
—
750
1
µA
mA
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Circuit Solution Inc.
SR011-0B
3
IS61C512
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-15 ns
Min. Max.
Parameter
-20 ns
Min. Max.
Min.
-25 ns
Max.
-35 ns
Min. Max.
Unit
tRC
Read Cycle Time
15
—
20
—
25
—
35
—
ns
tAA
Address Access Time
—
15
—
20
—
25
—
35
ns
tOHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
tACE1
CE1 Access Time
—
15
—
20
—
25
—
35
ns
tACE2
CE2 Access Time
—
15
—
20
—
25
—
35
ns
tDOE
OE Access Time
—
7
—
8
—
9
—
12
ns
(2)
OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
(2)
OE to High-Z Output
0
6
0
9
0
10
0
12
ns
tLZCE1(2) CE1 to Low-Z Output
2
—
3
—
3
—
3
—
ns
CE2 to Low-Z Output
2
—
3
—
3
—
3
—
ns
CE1 or CE2 to High-Z Output
0
8
0
9
0
10
0
12
ns
CE1 or CE2 to Power-Up
0
—
0
—
0
—
0
—
ns
CE1 or CE2 to Power-Down
—
12
—
18
—
20
—
20
ns
tLZOE
tHZOE
(2)
tLZCE2
tHZCE
tPU
(3)
tPD(3)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
1213 Ω
1213 Ω
3.3V
3.3V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
Figure 1a.
4
1378 Ω
5 pF
Including
jig and
scope
1378 Ω
Figure 1b.
Integrated Circuit Solution Inc.
SR011-0B
IS61C512
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CE1
tHZOE
tLZOE
tACE1/tACE2
CE2
tLZCE1/tLZCE2
DOUT
HIGH-Z
HIGH-Z
DATA VALID
tPU
SUPPLY
CURRENT
tHZCE
tPD
50%
ICC
50%
ISB
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
SR011-0B
5
IS61C512
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
-15 ns
Min. Max.
Parameter
-20 ns
Min. Max.
Min.
-25 ns
Max.
-35 ns
Min. Max.
Unit
tWC
Write Cycle Time
15
—
20
—
25
—
35
—
ns
tSCE1
CE1 to Write End
12
—
15
—
20
—
30
—
ns
tSCE2
CE2 to Write End
12
—
15
—
20
—
30
—
ns
tAW
Address Setup Time to Write End
12
—
15
—
20
—
30
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
tPWE(4)
WE Pulse Width
10
—
12
—
15
—
20
—
ns
tSD
Data Setup to Write End
8
—
10
—
12
—
15
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE LOW to High-Z Output
—
7
—
10
—
12
—
8
ns
tLZWE(2) WE HIGH to Low-Z Output
2
—
2
—
2
—
2
—
ns
tHD
(2)
tHZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE
WE Controlled)(1,2)
tWC
ADDRESS
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
6
tHD
DATA-IN VALID
Integrated Circuit Solution Inc.
SR011-0B
IS61C512
WRITE CYCLE NO. 2 (CE1
CE1, CE2 Controlled)(1,2)
CE1
tWC
ADDRESS
tSA
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE
WE
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = HIGH.
Integrated Circuit Solution Inc.
SR011-0B
7
IS61C512
ORDERING INFORMATION: IS61C512
Commercial Range: 0°C to + 70°C
Speed (ns) Order Part No.
Package
ORDERING INFORMATION: IS61C512
Industrial Range: –40°C to + 85°C
Speed (ns) Order Part No.
Package
15
15
15
IS61C512-15J
IS61C512-15N
IS61C512-15T
300mil SOJ
300mil DIP
8*20mm TSOP-1
15
15
15
IS61C512-15JI
IS61C512-15NI
IS61C512-15TI
300mil SOJ
300mil DIP
8*20mm TSOP-1
20
20
20
IS61C512-20J
IS61C512-20N
IS61C512-20T
300mil SOJ
300mil DIP
8*20mm TSOP-1
20
20
20
IS61C512-20JI
IS61C512-20NI
IS61C512-20TI
300mil SOJ
300mil DIP
8*20mm TSOP-1
25
25
25
IS61C512-25J
IS61C512-25N
IS61C512-25T
300mil SOJ
300mil DIP
8*20mm TSOP-1
25
25
25
IS61C512-25JI
IS61C512-25NI
IS61C512-25TI
300mil SOJ
300mil DIP
8*20mm TSOP-1
35
35
35
IS61C512-35J
IS61C512-35N
IS61C512-35T
300mil SOJ
300mil DIP
8*20mm TSOP-1
35
35
35
IS61C512-35JI
IS61C512-35NI
IS61C512-35TI
300mil SOJ
300mil DIP
8*20mm TSOP-1
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
SR011-0B
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