TA2170FLG TOSHIBA Bipolar Linear IC Silicon Monolithic TA2170FLG Low Current Consumption Headphone Amplifier (Built-in Input Selector) The TA2170FLG is a stereo headphone amplifier built-in selector switch for three inputs. The mute switch is built into each of the three inputs, and a single or mixer output can be selected for the output. Features • Low current consumption VCC = 3 V, f = 1 kHz, RL = 32 Ω, typ. • No signal mode Weight: 0.05 g (typ.) ICCQ = 0.9 mA (1-input mode) ICCQ = 1.0 mA (2-input mode) Marking: 2170G ICCQ = 1.1 mA (3-input mode) • 0.1 mW × 2 ch ICC = 2.2 mA (1-input mode) ICC = 2.3 mA (2-input mode) ICC = 2.4 mA (3-input mode) • 0.5 mW × 2 ch ICC = 4.1 mA (1-input mode) ICC = 4.2 mA (2-input mode) ICC = 4.3 mA (3-input mode) • GV = −0.3 dB (1-input mode, typ.) • Built-in signal level adjustment circuit to eliminate any perceptible change in volume whether single or mixer output is used. • Built-in power switch • Built-in all mute switch • Built-in mute switch at each buffer amplifier • Built-in one side mute switch at buffer amplifier 1 • Operating supply voltage range (Ta = 25°C): VCC1 (opr) = 1.8 to 4.5 V VCC2 (opr) = 0.9 to 4.5 V 1 2006-04-19 TA2170FLG Block Diagram VCC1 18 VCC RF IN 17 GND 16 VCC1 15 BIAS OUT 14 BIAS IN 13 OUT ADJ PW SW ON IN1A BIAS 19 12 BUF1A ON IN1 IN1B 11 MUTE1-A BUF1B MUTE3 21 ON MUTE2 22 ON MUTE1A 23 MUTE1 PW SW MUTE SW ON ALL MUTE 20 IN2A 10 BUF2A IN2 IN2B 9 BUF2B MUTE2 IN3A 8 BUF3A PW A ON IN3 PW B IN3B MUTE1 24 7 ALL MUTE BUF3B MUTE3 1 EQA 2 OUTA 3 PW GND 4 OUTA OUTB 5 EQB 6 VCC2 VCC2 OUTB RL RL 2 2006-04-19 TA2170FLG Pin Descriptions Pin Voltage: Typical pin voltage for a test circuit when no input signal is applied, VCC1 = VCC2 = 3 V, Ta = 25°C Pin No. & Name 1 Function Pin Voltage (V) Internal Circuit EQA 2 Low-pass compensation pins 15 kΩ 5 kΩ 5 1.15 EQB 43 kΩ 1 BIAS OUT 2 OUTA 4 OUTB 3 PW GND GND for power drive stage 6 VCC2 VCC for power drive stage 3 7 IN3B Inputs to buffer amplifier 3 1.15 8 IN3A 9 IN2B Outputs from power amplifier 6 VCC2 2 OUT 1.15 0 3 10 kΩ 8 10 IN2A 11 IN1B BIAS OUT Inputs to buffer amplifier 1 12 1.15 10 kΩ Inputs to buffer amplifier 2 1.15 IN1A 3 2006-04-19 TA2170FLG OUT ADJ DC output voltage adjustment Either connect this pin or leave it open, depending on the level of VCC2. If the power supply of a 1.5-V system is applied to VCC2, connect this pin to BIAS IN (pin 14). If the power supply of a 3-V system is applied to VCC2, leave this pin open. 14 BIAS IN Bias circuit input 15 BIAS OUT Bias circuit output 16 VCC1 VCC for everything other than the power drive stage 18 RF IN Ripple filter input 17 GND Pin Voltage (V) Internal Circuit VCC2 1.85 47 kΩ 15 kΩ 13 Function 18 13 16 14 15 62 kΩ Pin No. & Name VCC1 1.15 1.15 3 2.7 ⎯ ⎯ 0 VCC1 100 kΩ ALL MUTE All mute switch Mute ON: L level Mute OFF : H level Refer to Application Note 4. 10 kΩ PW SW 19 3 39 kΩ 19 Power switch IC ON: H level IC OF : L level Refer to Application Note 4. 20 21 22 MUTE3 Mute switch of buffer amplifier 3 Mute ON: L level Mute OFF: H level Refer to Application Note 4. MUTE2 Mute switch of buffer amplifier 2 Mute ON: L level Mute OFF: H level Refer to Application Note 4. 23 MUTE1A Mute switch of buffer amplifier 1A Mute ON: L level Mute OFF: H level This switch is used for turning on A channel mutes for buffer amplifier 1. Refer to Application Note 4. 24 MUTE1 Mute switch of buffer amplifier 1 Mute ON: L level Mute OFF: H level Refer to Application Note 4. VCC 10 kΩ 20 kΩ ⎯ 20 ⎯ ⎯ VCC 10 kΩ 21 ⎯ ⎯ 4 2006-04-19 TA2170FLG Application Notes 1. Mute switch and voltage gain This IC is designed to ensure there is no perceptible change in volume whether a single output or several outputs are used. When the input signal to the three buffer amplifiers is the same and in a linear domain, the relation between the mute switches and voltage gain is as follows: Test condition: VCC = 3 V, f = 1 kHz, Vin = −20 dBV, theoretical value. (1) 1-input mode MUTE SW MUTE1 MUTE1A MUTE2 MUTE3 Attenuation to an input signal (dB) BUF1 BUF2 BUF3 Ach Bch Ach Bch Ach Bch Total gain (dB) Ach Bch Input signal is applied to BUF 1. OFF OFF ON ON 0 0 ⎯ ⎯ ⎯ ⎯ 0 0 OFF OFF OFF ON −6 −6 ⎯ ⎯ ⎯ ⎯ −6 −6 OFF OFF ON OFF −6 −6 ⎯ ⎯ ⎯ ⎯ −6 −6 OFF OFF OFF OFF −9.5 −9.5 ⎯ ⎯ ⎯ ⎯ −9.5 −9.5 OFF ON ON ON ⎯ 0 ⎯ ⎯ ⎯ ⎯ ⎯ 0 OFF ON OFF ON ⎯ −6 ⎯ ⎯ ⎯ ⎯ ⎯ −6 OFF ON ON OFF ⎯ −6 ⎯ ⎯ ⎯ ⎯ ⎯ −6 OFF ON OFF OFF ⎯ −9.5 ⎯ ⎯ ⎯ ⎯ ⎯ −9.5 Input signal is applied to BUF 2 ON ON/OFF OFF ON ⎯ ⎯ 0 0 ⎯ ⎯ 0 0 ON ON/OFF OFF OFF ⎯ ⎯ −6 −6 ⎯ ⎯ −6 −6 OFF OFF OFF ON ⎯ ⎯ −6 −6 ⎯ ⎯ −6 −6 OFF ON OFF ON ⎯ ⎯ 0 −6 ⎯ ⎯ 0 −6 OFF OFF OFF OFF ⎯ ⎯ −9.5 −9.5 ⎯ ⎯ −9.5 −9.5 OFF ON OFF OFF ⎯ ⎯ −6 −9.5 ⎯ ⎯ −6 −9.5 OFF ⎯ ⎯ ⎯ ⎯ 0 0 0 0 Input signal is applied to BUF 3. ON ON/OFF ON ON ON/OFF OFF OFF ⎯ ⎯ ⎯ ⎯ −6 −6 −6 −6 OFF OFF ON OFF ⎯ ⎯ ⎯ ⎯ −6 −6 −6 −6 OFF ON ON OFF ⎯ ⎯ ⎯ ⎯ 0 −6 0 −6 OFF OFF OFF OFF ⎯ ⎯ ⎯ ⎯ −9.5 −9.5 −9.5 −9.5 OFF ON OFF OFF ⎯ ⎯ ⎯ ⎯ −6 −9.5 −6 −9.5 5 2006-04-19 TA2170FLG (2) 2-input mode Attenuation to an input signal (dB) BUF1 BUF2 BUF3 Ach Bch Ach Bch Ach Bch MUTE SW MUTE1 MUTE1A MUTE2 MUTE3 Total gain (dB) Ach Bch Input signal is applied to BUF 1 and BUF 2. OFF ON −6 −6 −6 −6 ⎯ ⎯ 0 0 OFF OFF OFF −9.5 −9.5 −9.5 −9.5 ⎯ ⎯ −3.5 −3.5 ON OFF ON ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ON OFF OFF ⎯ −6 −9.5 −6 ⎯ ⎯ −3.5 0 OFF OFF OFF OFF OFF Input signal is applied to BUF 1 and BUF 3. OFF OFF ON OFF −6 −6 ⎯ ⎯ −6 −6 0 0 OFF OFF OFF OFF −9.5 −9.5 ⎯ ⎯ −9.5 −9.5 −3.5 −3.5 OFF ON ON OFF ⎯ −6 ⎯ ⎯ −6 −6 −6 0 OFF ON OFF OFF ⎯ −9.5 ⎯ ⎯ −9.5 −9.5 −9.5 −3.5 −6 −6 −6 −6 0 0 Input signal is applied to BUF 2 and BUF 3. ON/OFF OFF OFF ⎯ ⎯ OFF ON OFF OFF ⎯ ⎯ −6 −9.5 −6 −9.5 0 −3.5 OFF OFF OFF OFF ⎯ ⎯ −9.5 −9.5 −9.5 −9.5 −3.5 −3.5 ON (3) 3-input mode Attenuation to an input signal (dB) BUF1 BUF2 BUF3 Ach Bch Ach Bch Ach Bch MUTE SW MUTE2 MUTE3 Total gain (dB) Ach Bch MUTE1 MUTE1A OFF OFF OFF OFF −9.5 −9.5 −9.5 −9.5 −9.5 −9.5 0 0 OFF ON OFF OFF ⎯ −9.5 −9.5 −9.5 −9.5 −9.5 −3.5 0 2. Low-cut compensation The low-frequency range can be decreased using an output-coupling capacitor and a load (fc = 50 Hz at C = 100 µF, R = 32 Ω). However, since the capacitor is connected between the IC’s output pin (pin 2/4) and EQ pin (pin 1/5), the low-frequency gain of the power amplifier increases, enabling low-cut compensation to be performed. For the response of capacitors of different values, refer to Figure 1. RES – f 4.0 0.1 µF 2.0 0.15 µF Response (dB) 0.0 −2.0 −4.0 0.22 µF −6.0 No compensation −8.0 Coupling C = 100 µF −10.0 −12.0 10 RL = 32 Ω 50 100 500 1000 Frequency f 5000 (Hz) Figure 1. Capacitor Response 6 2006-04-19 TA2170FLG 3. Adjustment of DC output voltage Perform the following with the OUT ADJ pin (pin 13) using the power supply of VCC1 and VCC2: • If a boost voltage is applied to VCC1, VCC2 is connected to a battery and the difference between VCC1 and VCC2 is greater than or equal to 0.7 V, short pins 13 and 14 together. In this case the DC output voltage will be as follows: VCC2 . 2 • If the difference between VCC1 and VCC2 is less than 0.7 V, or if VCC1 and VCC2 are connected to the same power supply, leave pin 13 open. In these cases, the DC output voltage will be VCC2 − 0.7 V . 2 4. Switch (1) Timing chart Refer to Figure 2 for the IC timing chart. ON PW SW OFF OFF ALL MUTE ON OFF MUTE ON OUT 200 ms 100 ms Figure 2. Timing Chart (2) (3) PW SW The device is ON when this pin is set to High. To prevent the IC being turned ON by external noise, it is necessary to connect an external pull-down resistor to the PW SW pin. The pin is highly sensitive. Mute smoothing Ensure that the smoothing resistor used for the mute pin is 100 kΩ or less. The switch circuit will not operate normally if the value is greater than this. 7 2006-04-19 TA2170FLG (4) Switch sensitivity (Ta = 25°C) 5 5 (V) 4.5 V 4 Applied voltage V20~24 Applied voltage V19 (V) 4.5 V 3 H 2 1.5 V 1 0.3 V 0 0 2 Supply voltage 3 H 2 1 0.8 V 0.1 V L 1 4 3 VCC1 4 0 0 5 L 1 (V) 2 Supply voltage PW SW 3 VCC1 4 5 (V) MUTE H level IC ON H level Mute OFF L level IC OFF L level Mute ON Figure 3: Switch Sensitivity 5. Capacitor The following capacitors must have excellent temperature and frequency characteristics. Absolute Maximum Ratings (Ta = 25°C) Characteristic Symbol Rating Unit Supply voltage 1 VCC1 4.5 Supply voltage 2 VCC2 4.5 Output current Io (peak) 100 mA Power dissipation PD (Note) 350 mW V Operating temperature Topr −25~75 °C Storage temperature Tstg −55~150 °C Note: Derated by 2.8 mW/°C above Ta = 25°C 8 2006-04-19 TA2170FLG Electrical Characteristics (Unless otherwise specified, VCC1 = VCC2 = 3 V, Rg = 600 Ω, RL = 32 Ω, f = 1 kHz, Ta = 25°C, SW1~SW5: a, SW6~SW8: a) Characteristic Quiescent supply current Symbol Min. Typ. Max. Unit µA ICCQ1 IC OFF mode SW1~5: b ⎯ ⎯ 5 ICCQ2 1 input on mode BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) ⎯ 0.9 1.6 ICCQ3 2 input on mode BUF1/2: ON (SW4/5: a, SW3: b) BUF1/3: ON (SW3/5: a, SW4: b) BUF2/3: ON (SW3/4: a, SW5: b) ⎯ 1.0 1.8 ICCQ4 3 input on mode ⎯ 1.1 2.0 ICCQ5 1 input on mode VCC1 = 2.4 V, VCC2 = 1.2 V BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) ⎯ 0.9 1.6 ICC1 1 input on mode 0.1 mW/32 Ω × 2 ch BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) ⎯ 2.2 ⎯ ICC2 2 input on mode 0.1 mW/32 Ω × 2 ch BUF1/2: ON (SW4/5: a, SW3: b) BUF1/3: ON (SW3/5: a, SW4: b) BUF2/3: ON (SW3/4: a, SW5: b) ⎯ 2.3 ⎯ ICC3 3 input on mode 0.1 mW/32 Ω × 2 ch ⎯ 2.4 ⎯ GV1 1 input on mode Vo = −20 dBV BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) −1.8 −0.3 1.2 GV2 2 input on mode Vo = −20 dBV BUF1/2: ON (SW4/5: a, SW3: b) BUF1/3: ON (SW3/5: a, SW4: b) BUF2/3: ON (SW3/4: a, SW5: b) −1.0 0.5 2.0 GV3 3 input on mode Vo = −20 dBV −0.8 0.7 2.2 CB Vo = −20 dBV −1.5 0 1.5 Power supply current during drive Voltage gain Channel balance Test condition mA mA dB dB Po1 THD = 10% 15 20 ⎯ Po2 VCC1 = 2.4 V, VCC2 = 1.2 V THD = 10% 3 6 ⎯ Total harmonic distortion THD Po = 1 mW ⎯ 0.1 0.3 % Output noise voltage Vno Rg = 600 Ω, Filter: IHF-A, SW6~8: b ⎯ −100 −96 dBV Output power mW Cross talk CT Vo = −20 dBV −53 −60 ⎯ dB Ripple rejection ratio RR fr = 100 Hz, Vr = −20 dBV −70 −80 ⎯ dB ATT1 ALL MUTE SW: ON, Vo = −20 dBV −75 −90 ⎯ ATT2 MUTE SW: ON, Vo = −20 dBV −47 −62 ⎯ Muting attenuation dB PW SW ON current I19 VCC1 = 1.8 V, VCC2 = 0.9 V 5 ⎯ ⎯ µA PW SW OFF voltage V19 VCC1 = 1.8 V, VCC2 = 0.9 V 0 ⎯ 0.3 V MUTE SW OFF current I20-24 VCC1 = 1.8 V, VCC2 = 0.9 V 5 ⎯ ⎯ µA MUTE SW ON voltage V20-24 VCC1 = 1.8 V, VCC2 = 0.9 V 0 ⎯ 0.1 V 9 2006-04-19 TA2170FLG Test Circuit 18 VCC RF IN 17 GND 16 4.7 µF 10 µF 22 µF 4.7 µF VCC1 VCC1 15 BIAS OUT 14 BIAS IN 13 OUT ADJ SW1 PW SW (a) 19 (b) 0.1 µF 0.1 µF TA2170FLG IN2B MUTE2 22 9 (a) 100 kΩ MUTE1A 23 IN3A 7 0.22 µF OUTA 2 OUTA RL 3 4 PW GND 10 OUTB 5 0.22 µF EQB 6 (b) SW8b 1 µF (b) SW7a 1 µF (b) SW7b (b) SW6a SW6b 1 µF (b) (a) 600 Ω Rg = 600 Ω (a) 600 Ω Rg = 600 Ω (a) 600 Ω Rg = 600 Ω (a) 600 Ω Rg = 600 Ω (a) 600 Ω Rg = 600 Ω (a) 600 Ω VCC2 VCC2 22 µF EQA 100 µF 1 1 µF 1 µF (b) IN3B MUTE1 24 4.7 Ω 0.22 µF (a) 100 kΩ Rg = 600 Ω SW8a 1 µF 8 4.7 Ω 0.22 µF SW5a (b) IN2A 10 MUTE3 21 100 µF SW5b (b) (a) 100 kΩ IN1B 11 0.1 µF SW4 (b) (a) 100 kΩ ALL MUTE 20 0.1 µF SW3 (b) 12 0.1 µF SW2 (b) (a) 100 kΩ IN1A OUTB RL 2006-04-19 TA2170FLG Markings Markings (example) *1 9 *1 *2 0 1 K A *1 Product name: 2152 *2 Weekly code: 9 0 1 K A Toshiba internal management code Weekly code Year (last digit only) Orientation marking *2 11 2006-04-19 TA2170FLG Package Dimensions Weight: 0.05 g (typ.) 12 2006-04-19 TA2170FLG RESTRICTIONS ON PRODUCT USE 060116EBA • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux 13 2006-04-19