LINER LTC1412 12-bit, 3msps, sampling a/d converter Datasheet

LTC1412
12-Bit, 3Msps,
Sampling A/D Converter
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FEATURES
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DESCRIPTION
The LTC ®1412 is a 12-bit, 3Msps, sampling A/D converter. This high performance device includes a high
dynamic range sample-and-hold and a precision reference. Operating from ±5V supplies it draws only 150mW.
Sample Rate: 3Msps
72dB S/(N + D) and 82dB SFDR at Nyquist
±0.35LSB INL and ±0.25LSB DNL (Typ)
Power Dissipation: 150mW
External or Internal Reference Operation
True Differential Inputs Reject Common Mode Noise
40MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
No Pipeline Delay
28-Pin SSOP Package
The ±2.5V input range is optimized for low noise and low
distortion. Most high performance op amps also perform
best over this range, allowing direct coupling to the analog
inputs and eliminating the need for special translation
circuitry. Outstanding AC performance includes 72dB
S/(N + D) and 82dB SFDR at the Nyquist input frequency
of 1.5MHz.
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APPLICATIONS
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The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 40MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
Telecommunications
Digital Signal Processing
Mulitplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
The ADC has a high speed 12-bit parallel output port. There
is no pipeline delay in the conversion results. A separate
convert start input and converter status signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors. A
digital output driver power supply pin allows direct connection to 3V logic.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
5V
OPTIONAL
3V LOGIC
SUPPLY
10µF
AVDD
DVDD
OVDD
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
AIN+
12
S/H
12-BIT ADC
AIN–
•
•
•
D11 (MSB)
D0 (LSB)
4.0625V
COMP
BUFFER
10µF
2k
VREF
VSS
10µF
2.5V
REFERENCE
AGND
BUSY
CS
CONVST
TIMING AND
LOGIC
DGND
74
68
10
62
56
8
6
4
2
0
OGND
1k
1412 TA01
– 5V
12
S/(N + D) (dB)
OUTPUT
BUFFERS
EFFECTIVE NUMBER OF BITS
LTC1412
10k
100k
1M
INPUT FREQUENCY (Hz)
10M
1412 G01
1
LTC1412
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = DVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 6V
Negative Supply Voltage (VSS) ................................ – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V
Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1412C ............................................... 0°C to 70°C
LTC1412I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
AIN+
AIN–
1
28 AVDD
2
27 DVDD
VREF
3
26 VSS
REFCOMP
4
25 BUSY
AGND
5
24 CS
D11 (MSB)
6
23 CONVST
D10
7
22 OGND
D9
8
21 OVDD
D8
9
20 DVDD
D7 10
19 DGND
D6 11
18 D0
D5 12
17 D1
D4 13
16 D2
DGND 14
15 D3
LTC1412CG
LTC1412IG
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/ W
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
PARAMETER
With internal reference (Notes 5, 6)
CONDITIONS
Resolution (No Missing Codes)
MIN
●
Integral Linearity Error
(Note 7)
Differential Linearity Error
Offset Error
TYP
12
●
±0.35
±1
LSB
●
±0.25
±1
LSB
±2
±6
±8
LSB
LSB
(Note 8)
±15
Full-Scale Error
Full-Scale Tempco
IOUT(REF) = 0
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A ALOG I PUT
±15
●
LSB
ppm/°C
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions
During Conversions
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Delay Time
tjitter
Sample-and-Hold Aperture Delay Time Jitter
2
UNITS
Bits
●
CMRR
MAX
Analog Input Common Mode Rejection Ratio
MIN
TYP
±1
20
– 0.5
– 2.5V < (AIN = AIN) < 2.5V
UNITS
V
10
4
●
–
MAX
±2.5
µA
pF
pF
50
ns
ns
1
psRMS
63
dB
LTC1412
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DY A IC ACCURACY
(Note 5)
SYMBOL PARAMETER
CONDITIONS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
100kHz Input Signal
1.465MHz Input Signal
MIN
TYP
70
72.5
72
MAX
UNITS
dB
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
1.465MHz Input Signal, First 5 Harmonics
– 90
– 80
dB
dB
SFDR
Spurious Free Dynamic Range
1.465MHz Input Signal
82
dB
IMD
Intermodulation Distortion
fIN1 = 29.37kHz, fIN2 = 32.446kHz
– 84
dB
40
MHz
4
MHz
Full Power Bandwidth
S/(N + D) ≥ 68dB
Full Linear Bandwidth
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I TER AL REFERE CE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.480
2.500
2.520
V
VREF Output Tempco
IOUT = 0
±15
ppm/°C
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.01
0.01
LSB/ V
LSB/ V
VREF Output Resistance
0.1mA ≤ IOUT ≤ 0.1mA
COMP Output Voltage
IOUT = 0
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DIGITAL I PUTS AND OUTPUTS
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CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
Low Level Output Voltage
MIN
VDD = 4.75V, IO = – 10µA
VDD = 4.75V, IO = – 200µA
●
VDD = 4.75V, IO = 160µA
VDD = 4.75V, IO = 1.6mA
●
●
IOZ
Hi-Z Output Leakage D11 to D0
VOUT = 0V to VDD, CS High
COZ
Hi-Z Output Capacitance D11 to D0
CS High (Note 9)
ISOURCE
Output Source Current
VOUT = 0V
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POWER REQUIRE E TS
V
(Note 5)
SYMBOL PARAMETER
VOL
kΩ
4.06
TYP
MAX
2.4
4.0
UNITS
V
0.8
V
±10
µA
1.4
pF
4.75
4.71
V
V
0.05
0.10
0.4
V
V
±10
µA
7
pF
– 10
mA
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
VDD
Positive Supply Voltage
(Note 10)
4.75
VSS
Negative Supply Voltage
(Note 10)
IDD
Positive Supply Current
CS High
●
12
16
mA
ISS
Negative Supply Current
CS High
●
18
28
mA
PD
Power Dissipation
●
150
220
mW
– 4.75
MAX
UNITS
5.25
V
– 5.25
V
3
LTC1412
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TI I G CHARACTERISTICS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
fSAMPLE(MAX)
Maximum Sampling Frequency
●
tTHROUGHPUT
Throughput Time (Acquisition + Conversion)
●
tCONV
Conversion Time
●
tACQ
Acquisition Time
t1
CS↓ to CONVST↓ Setup Time
(Notes 9, 10)
●
5
ns
t2
CONVST Low Time
(Note 10)
●
20
ns
t3
CONVST to BUSY Delay
CL = 25pF
3
MHz
●
ns
240
283
ns
20
50
ns
5
Data Ready Before BUSY↑
t5
Delay Between Conversions
(Note 10)
t6
Data Access Time After CS↓
CL = 25pF
20
ns
ns
●
– 20
– 25
0
20
25
ns
ns
●
50
10
35
45
ns
ns
8
30
35
40
ns
ns
ns
ns
●
t7
Bus Relinquish Time
LTC1412C
LTC1412I
t8
CONVST High Time
t9
Aperture Delay of Sample-and-Hold
●
●
●
20
ns
–1
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 3MHz and tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
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TI I G DIAGRA
CS
tCONV
t1
t2
CONVST
t3
t5
BUSY
t6
DATA
4
UNITS
333
●
t4
MAX
t4
DATA (N – 1)
DB11 TO DB0
t7
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
1412 TD
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LTC1412
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TYPICAL PERFOR A CE CHARACTERISTICS
Signal-to-Noise Ratio
vs Input Frequency
74
68
10
62
56
6
4
0
70
S/(N + D) (dB)
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Distortion vs Input Frequency
80
2
– 20
60
DISTORTION (dB)
12
SIGNAL-TO-NOISE RATIO (dB)
EFFECTIVE NUMBER OF BITS
S/(N + D) and Effective Number of
Bits vs Input Frequency
50
40
30
0
100k
1M
10k
INPUT FREQUENCY (Hz)
– 80
THD
–100
10M
–120
100k
1M
INPUT FREQUENCY (Hz)
10M
10
0
Nonaveraged, 4096 Point FFT,
Input Frequency = 1.45kHz
0
0
fSMPL = 3Msps
fIN = 97.412kHz
SFDR = 93.3dB
SINAD = 73dB
–10
–20
AMPLITUDE (dB)
– 50
– 60
– 70
– 80
– 40
– 60
– 80
fSMPL = 3Msps
fIN = 1.419kHz
SFDR = 83dB
SINAD = 72.5dB
SNR = 73db
–20
AMPLITUDE (dB)
– 20
10k
1412 G03
Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
– 40
100
1k
INPUT FREQUENCY (Hz)
1412 G02
Spurious-Free Dynamic Range
vs Input Frequency
– 30
3RD
2ND
0
10k
1412 G01
SPURIOUS-FREE DYNAMIC RANGE (dB)
– 60
20
10
1k
– 40
– 40
– 60
– 80
–100
–100
– 90
–100
10K
–120
100K
1M
FREQUENCY (Hz)
10M
–120
0
200
400 600 800 1000 1200 1400
FREQUENCY (kHz)
1412 G04
1.0
1.0
0.5
0.5
DNL (LSBs)
– 50
– 60
– 70
– 80
INL (LSBs)
– 30
AMPLITUDE (dB)
Integral Nonlinearity
vs Output Code
fSMPL = 3MHz
fIN1 = 85.693359kHz
fIN2 = 114.990234kHz
– 40
400 600 800 1000 1200 1400
FREQUENCY (kHz)
1412 F02B
Differential Nonlinearity
vs Output Code
0
–20
200
1412 F02a
Intermodulation Distortion Plot
–10
0
0
– 0.5
0
– 0.5
– 90
–100
–110
–1.0
0
200
400 600 800 1000 1200 1400
FREQUENCY (kHz)
1412 G05
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
1412 G06
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
1412 G07
5
LTC1412
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Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
0
80
– 20
COMMON MODE REJECTION (dB)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
TYPICAL PERFOR A CE CHARACTERISTICS
– 40
– 60
VSS
– 80
VDD
DGND
–100
–120
70
60
50
40
30
20
10
0
1k
10k
100k
1M
RIPPLE FREQUENCY (Hz)
10M
1412 G08
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
10M
1412 G09
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PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. ±2.5V input range
when AIN– is grounded. ±2.5V differential if AIN– is
driven.
OVDD (Pin 21): Positive Supply for the Output Drivers. Tie
to Pin 28 when driving 5V logic. Tie to 3V when driving
3V logic.
AIN– (Pin 2): Negative Analog Input. Can be grounded or
driven differentially with AIN+.
OGND (Pin 22): Digital Ground for the Output Drivers.
VREF (Pin 3): 2.5V Reference Output.
REFCOMP (Pin 4): 4.06V Reference Bypass Pin.
Bypass to AGND with 10µF ceramic (or 10µF tantalum in
parallel with 0.1µF ceramic).
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
DGND (Pin 19): Digital Ground for Internal Logic.
DVDD (Pin 20): 5V Positive Supply. Tie to Pin 28. Bypass
to AGND with 0.1µF ceramic.
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CONVST (Pin 23): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. This input must be low for the
ADC to recognize the CONVST inputs.
BUSY (Pin 25): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with
10µF ceramic (or 10µF tantalum in parallel with 0.1µF
ceramic).
DVDD (Pin 27): 5V Positive Supply. Tie to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with
10µF ceramic (or 10µF tantalum in parallel with 0.1µF
ceramic).
LTC1412
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FUNCTIONAL BLOCK DIAGRA
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CSAMPLE
AIN+
AVDD
CSAMPLE
DVDD
AIN–
2k
VREF
ZEROING SWITCHES
2.5V REF
+
REF AMP
COMP
12-BIT CAPACITIVE DAC
–
REFCOMP
(4.06V)
12
SUCCESSIVE APPROXIMATION
REGISTER
AGND
•
•
•
D11
D0
OVDD
INTERNAL
CLOCK
DGND
OUTPUT
LATCHES
CONTROL LOGIC
OGND
1412 BD
CONVST
CS
BUSY
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
DBN
1k
DBN
1k
CL
DBN
CL
1k
B) HI-Z TO VOL AND VOH TO VOL
A) HI-Z TO VOH AND VOL TO VOH
DBN
1412 TC01
A) VOH TO HI-Z
100pF
100pF
B) VOL TO HI-Z
1412 TC02
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APPLICATIONS INFORMATION
Conversion Details
The LTC1412 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 50ns will provide enough time for the
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LTC1412
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APPLICATIONS INFORMATION
HOLD
AIN–
ZEROING SWITCHES
CSAMPLE–
SAMPLE
HOLD
HOLD
HOLD
CDAC+
+
+
VDAC
CDAC–
– 40
– 60
– 80
–100
COMP
–
VDAC–
12
SAR
–120
• D11
•
• D0
OUTPUT
LATCHES
1412 F01
Dynamic Performance
The LTC1412 has excellent high speed sampling capability. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1412 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
200 400 600 800 1000 1200 1400
FREQUENCY (kHz)
Figure 2a. LTC1412 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
0
fSMPL = 3Msps
fIN = 1.419kHz
SFDR = 83dB
SINAD = 72.5dB
SNR = 73db
–20
AMPLITUDE (dB)
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 12-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 12-bit output latches.
0
1412 F02a
Figure 1. Simplified Block Diagram
8
fSMPL = 3Msps
fIN = 97.412kHz
SFDR = 93.3dB
SINAD = 73dB
–20
AMPLITUDE (dB)
AIN+
0
CSAMPLE+
SAMPLE
– 40
– 60
– 80
–100
–120
0
200
400 600 800 1000 1200 1400
FREQUENCY (kHz)
1412 F02B
Figure 2b. LTC1412 Nonaveraged, 4096 Point FFT,
Input Frequency = 1.45MHz
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 3MHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 1.5MHz.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 3MHz the LTC1412 maintains near ideal ENOBs up
to the Nyquist input frequency of 1.5MHz. Refer to
Figure␣ 3.
LTC1412
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68
10
62
56
8
6
4
2
0
1k
100k
1M
10k
INPUT FREQUENCY (Hz)
10M
1412 G01
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20 log
V22 + V32 + V42 + . . .Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1412 has good distortion
performance up to the Nyquist frequency and beyond.
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
(
)
IMD fa + fb = 20 log
(
)
Amplitude at fa ± fb
Amplitude at f a
0
fSMPL = 3MHz
fIN1 = 85.693359kHz
fIN2 = 114.990234kHz
–10
–20
– 30
AMPLITUDE (dB)
12
S/(N + D) (dB)
EFFECTIVE NUMBER OF BITS
APPLICATIONS INFORMATION
– 40
– 50
– 60
– 70
– 80
– 90
–100
–110
0
200
400 600 800 1000 1200 1400
FREQUENCY (kHz)
1412 G05
Figure 5. Intermodulation Distortion Plot
0
Peak Harmonic or Spurious Noise
DISTORTION (dB)
– 20
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
– 40
– 60
– 80
THD
–100
Full Power and Full Linear Bandwidth
3RD
2ND
–120
10
100
1k
INPUT FREQUENCY (Hz)
10k
1412 G03
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1412 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
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LTC1412
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APPLICATIONS INFORMATION
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1412 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any unwanted
signal that is common mode to both inputs will be reduced
by the common mode rejection of the sample-and-hold
circuit. The inputs draw only one small current spike while
charging the sample-and-hold capacitors at the end of
conversion. During conversion, the analog inputs draw
only a small leakage current. If the source impedance of
the driving circuit is low then the LTC1412 inputs can be
driven directly. As source impedance increases so will
acquisition time (see Figure 6). For minimum acquisition
time, with high source impedance, a buffer amplifier must
be used. The only requirement is that the amplifier driving
the analog input(s) must settle after the small current
spike before the next conversion starts (settling time must
be 50ns for full throughput rate).
The best choice for an op amp to drive the LTC1412 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1412. More detailed information is
available in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
LT®1223: 100MHz Video Current Feedback Amplifier.
6mA supply current. ±5V to ±15V supplies. Low Noise.
Good for AC applications.
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current. ±5V to ±15V supplies. Low Noise. Best for
AC applications.
LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. ±2V to ±15V supplies. Low Noise. Good
AC specifications, 6mA supply current each amplifier.
10
ACQUISITION TIME (µs)
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
The second requirement is that the closed-loop bandwidth
must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.
1
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. ±5V to ±15V supplies. Good AC and DC
specifications. 70ns settling to 0.5LSB.
0.1
0.01
10
100
1k
10k
SOURCE RESISTANCE (Ω)
100k
1412 F06
Figure 6. Acquisition Time vs Source Resistance
LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply current. Good AC and DC specifications. 60ns settling to
0.5LSB.
LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op
Amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
Choosing an Input Amplifier
Input Filtering
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1412 noise and distortion. The small-signal band-
10
LinearView is a trademark of Linear Technology Corporation.
LTC1412
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width of the sample-and-hold circuit is 40MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.
For example, Figure 7 shows a 500pF capacitor from AIN+
to ground and a 100Ω source resistor to limit the input
bandwidth to 3.2MHz. The 500pF capacitor also acts as a
charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch-sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO and
silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.
When high amplitude unwanted signals are close in
frequency to the desired signal frequency, a multiple pole
100Ω
ANALOG INPUT
1
AIN+
2
AIN–
500pF
LTC1412
3
4
VREF
REFCOMP
10µF
5
AGND
1412 F07a
Figure 7a. RC Input Filter
1
VIN
1
8
7
2
3
6
3
4
5
4
2
LTC1560-1
– 5V
0.1µF
AIN+
0.1µF
The ±2.5V input range of the LTC1412 is optimized for low
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation
circuitry.
Some applications may require other input ranges. The
LTC1412 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference
and input circuitry and how they affect the input range.
Internal Reference
The LTC1412 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at VREF (Pin 3), see Figure 8a. A
2k resistor is in series with the output so that it can be
easily overdriven by an external reference or other circuitry, see Figure 8b. The reference amplifier gains the
voltage at the VREF pin by 1.625 to create the required
internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The
reference amplifier compensation pin, REFCOMP (Pin 4)
must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater.
For the best noise performance, a 10µF ceramic or 10µF
tantalum in parallel with a 0.1µF ceramic is recommended.
R1
2k
3 VREF
BANDGAP
REFERENCE
AIN–
4.0625V
4 REFCOMP
VREF
REFERENCE
AMP
R2
40k
10µF
REFCOMP
10µF
5
Input Range
2.500V
LTC1412
5V
filter is required. Figure 7b shows a simple implementation using an LTC1560-1 fifth-order elliptic continuous
time filter.
5 AGND
AGND
R3
64k
LTC1412
1412 F07b
Figure 7b. 1MHz Fifth-Order Elliptic Lowpass Filter
1412 F08a
Figure 8a. LTC1412 Reference Circuit
11
LTC1412
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1
AIN+
2
AIN–
ANALOG INPUT
5V
LTC1412
VIN
3
VOUT
LT1019A-2.5
4
VREF
REFCOMP
10µF
5
AGND
1412 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1412 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
ANALOG INPUT
1.25V TO 3V
DIFFERENTIAL
1
AIN+
2
AIN–
1.25V TO 3V 3
4
0
– 20
– 40
– 60
VSS
– 80
DGND
–100
–120
1k
10k
100k
1M
RIPPLE FREQUENCY (Hz)
10M
1412 G08
Figure 10. CMRR vs Input Frequency
mode voltage. THD will degrade as the inputs approach
either power supply rail, from – 86dB with a common
mode of 0V to –75dB with a common mode of 2.5V
or – 2.5V.
Full-Scale and Offset Adjustment
VREF
REFCOMP
111...111
10µF
111...110
AGND
111...101
1412 F09
Figure 9. Driving VREF with a DAC
Differential Inputs
The LTC1412 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – (AIN– ) independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies, see Figure 10. The
only requirement is that both inputs cannot exceed the
AVDD or AVSS power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
OUTPUT CODE
5
12
VDD
Figure 11a shows the ideal input/output characteristics for
the LTC1412. The code transitions occur midway between
successive integer LSB values (i.e., – FS/2 + 0.5LSB,
– FS/2 + 1.5LSB, – FS/2 + 2.5LSB,...FS/2 – 1.5LSB, FS/2 –
0.5LSB). The output is two’s complement binary with
1LSB = FS – (– FS)/4096 = 5V/4096 = 1.22mV.
LTC1412
LTC1450
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
APPLICATIONS INFORMATION
000...010
000...001
000...000
FS – 1LSB
FS – 1LSB
INPUT VOLTAGE (V)
1412 F11a
Figure 11a. LTC1412 Transfer Characteristics
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error apply
LTC1412
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APPLICATIONS INFORMATION
– 5V
R3
24k
R1
50k
ANALOG INPUT
R4
100Ω
1
AIN+
2
AIN–
plane to the power supply should be low impedance.
Digital circuitry grounds must be connected to the digital
supply common. Low impedance analog and digital power
supply lines are essential to low noise operation of the
ADC. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as
possible.
LTC1412
R5 R2
47k 50k
3
R6
24k
4
VREF
REFCOMP
10µF
5
AGND
1412 F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
– 0.61mV (i.e., – 0.5LSB) at AIN+ and adjust the offset at
the AIN– input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to AIN+ and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
The LTC1412 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN – leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1412
will hold and convert the difference voltage between AIN+
and AIN– . The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN+ and AIN– traces should be run side
by side to equalize coupling.
Supply Bypassing
Board Layout and Bypassing
To obtain the best performance from the LTC1412, a
printed circuit board with ground plane is required. Layout
for the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital line
alongside an analog signal line.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pins 19 and 14 (DGND) and Pin 22 (OGND)
and all other analog grounds should be connected to this
single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane, see Figure 12. All
analog circuitry grounds should be terminated to this
analog ground plane. The ground return from the ground
1
AIN+
+
–
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
DIGITAL
SYSTEM
LTC1412
AIN–
ANALOG
INPUT
CIRCUITRY
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10µF tantalum capacitors
in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
REFCOMP
2
AGND
4
+
10µF
26
+
0.1µF
AVDD OVDD DVDD
VSS
5
10µF
28
+
0.1µF
10µF
21
20, 27
DGND
14, 19
OGND
22
0.1µF
ANALOG GROUND PLANE
1412 F12
POWER
SUPPLY
GROUND
Figure 12. Power Supply Grounding Practice
13
J3
J2
8
1
R18
10k
C10
1µF
16V
GND
2
R16
51Ω
LIM4
7
2
OUT
SENSE
C6
470pF
R15
51Ω
+
3
4
U5A
74HC14
2
LIM2
INPUT
3
D13
SS12
C11
10µF
16V
GND
U4
LT1175
6
5
SHDN
VOUT
1 JP6 2
1
JP7
R19
51Ω
1
2
TAB
4
VIN
INPUT
R17
10k
1
3
D14
SS12
VSS
1
2
C12
22µF
10V
JP8
VSS
2 –
4
VSS
C19
0.1µF
28
27
26
19
20
25
24
23
14
5
4
3
2
1
C14
0.1µF
VCC
C3
0.1µF
U5
DECOUPLING
OVDD
C13
0.1µF
C7
0.1µF
C9
0.1µF
8
1
6
C2
0.1µF
3.3V
2 JP3 1
R14
20Ω
2 JP4 1
VCC
VCC
U3
LT1363
3 7 5
+
C1
22µF
10V
U5B
74HC14
4
1 JP5 2
+
VCC
AVDD
DVDD
VSS
DGND
DVDD
BUSY
CS
CONVST
DGND
AGND
13
5
OVDD
OGND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 (MSB)
REFCOMP
VREF
–AIN
+AIN
C5
10µF
10V
U1
LTC1412
C4
0.1µF
+
OVDD
B10
B9
B8
7
8
9
R13
1k
Q5
Q6
D5
D6
Q7
D7
GND
10
Q4
Q3
Q2
Q1
D4
D3
D2
D1
Q0
C8
0.1µF
U5F
74HC14
12
U5C
74HC14
6
21
22
18 B0
17 B1
16 B2
15 B3
8
9
7
6
B6
B4
5
B7
B5
4
3
2
B8
B9
11
Q6
Q5
Q4
Q3
Q2
Q1
Q0
C20
15pF
Q7
D7
GND
10
D6
D5
D4
D3
D2
D1
D0
CLK
0E
20
B10
CLK
D0
13 B4
1
9
8
7
6
B2
B11
4
5
3
B1
B3
2
B0
0E
OVDD
OVDD
1
11
12 B5
11 B6
10 B7
B11
6
B[00:11]
20
OVDD
D11
D3
D2
D1
D0
12
13
14
15
16
17
18
19
9
D4
D5
D6
D7
D8
D9
D10
U7
74HC574
12
13
14
15
16
17
18
19
U6
74HC574
U5D
74HC14
8
11
RDY
D11
U5E
74HC14
10
D[0:11]
D11
D0
D2
D4
D6
D8
D10
D11
D9
D7
D5
D3
D1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
15
13
11
9
7
5
3
1
1412 F13a
16
14
12
10
8
6
4
2
JP2
HEADER
R12, 1.2k
R11, 1.2k
R10, 1.2k
R9, 1.2k
R8, 1.2k
R7, 1.2k
R6, 1.2k
R5, 1.2k
R4, 1.2k
R3, 1.2k
R2, 1.2k
R1, 1.2k
Figure 13a. LTC1412 Demonstration Board Features Analog Input Signal Buffer, 3Msps, Parallel Data Output 12-Bit ADC,
Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 16-Pin Header, P2
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES 1/8W, 5% SMT
2. ALL CAPACITOR VALUES 50V, 20% SMT
E1
–7V TO
–15V
CLK
A–
A+
J1
E2
GND
E3
7V TO
15V
U2
LT1121-5
JP1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
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APPLICATIONS INFORMATION
U
14
+
E4
OPTIONAL
LTC1412
LTC1412
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Figure 13b. Component Side Silkscreen
Figure 13c. Component Side
Figure 13d. Solder Side
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1412
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.301 – 0.311
(7.65 – 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.005 – 0.009
(0.13 – 0.22)
0.0256
(0.65)
BSC
0.022 – 0.037
(0.55 – 0.95)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
G28 SSOP 0694
RELATED PARTS
PART NUMBER
RESOLUTION
SPEED
COMMENTS
LTC1604
16
333ksps
±2.5V Input Range, ±5V Supply
LTC1605
16
100ksps
±10V Input Range, Single 5V Supply
LTC1419
14
800ksps
150mW, 81.5dB SINAD and 95dB SFDR
LTC1416
14
400ksps
75mW, Low Power with Excellent AC Specs
LTC1418
14
200ksps
15mW, Single 5V, Serial/Parallel I/O
LTC1410
12
1.25Msps
150mW, 71.5dB SINAD and 84dB THD
LTC1415
12
1.25Msps
55mW, Single 5V Supply
LTC1409
12
800ksps
80mW, 71.5dB SINAD and 84dB THD
LTC1279
12
600ksps
60mW, Single 5V or ±5V Supply
LTC1404
12
600ksps
High Speed Serial I/O in SO-8 Package
LTC1278-5
12
500ksps
75mW, Single 5V or ±5V Supply
16-Bit
14-Bit
12-Bit
LTC1278-4
12
400ksps
75mW, Single 5V or ±5V Supply
LTC1400
12
400ksps
High Speed Serial I/O in SO-8 Package
16
Linear Technology Corporation
sn1412 1412fs LT/TP 0798 4K • PRINTED IN
1630 McCarthy Blvd., Milpitas, CA 95035-7417
USA
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1998
●
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