MOTOROLA MC74HC174AD Hex d flip-flop with common clock and reset with lsttl compatible input Datasheet

 SEMICONDUCTOR TECHNICAL DATA
# " " ! High–Performance Silicon–Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
The MC74HCT174A is identical in pinout to the LS174. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
This device consists of six D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active–low.
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 178 FETs or 44.5 Equivalent Gates
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD
DATA
INPUTS
2 Q0
5
Q1
7 Q2
D2 6
D3 11
RESET
1
16
VCC
Q0
2
15
Q5
D0
3
14
D5
D1
4
13
D4
Q1
5
12
Q4
D4 13
14
D5
15
D2
6
11
D3
Q2
7
10
Q3
GND
8
9
NONINVERTING
OUTPUTS
10 Q3
12 Q4
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
D0 3
D1 4
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
CLOCK
Q5
FUNCTION TABLE
CLOCK 9
Inputs
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PIN 16 = VCC
PIN 8 = GND
RESET 1
Design Criteria
Value
Units
Internal Gate Count*
44.5
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
0.005
µW
Speed Power Product
0.0075
pJ
* Equivalent to a two–input NAND gate.
10/95
 Motorola, Inc. 1995
1
REV 6
Output
Reset
Clock
D
Q
L
H
H
H
H
X
X
H
L
X
X
L
H
L
No Change
No Change
L
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MC74HCT174A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
3.98
3.84
3.70
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
0.26
0.33
0.4
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
4.0
40
160
µA
∆ICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
VOH
VOL
Iin
Maximum Low–Level Output
Voltage
5.5
≥ – 55_C
25_C to 125_C
2.9
2.4
V
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HCT174A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
85_C
125_C
Unit
fMAX
Maximum Clock Frequency (50% Duty Cycle)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
24
30
36
ns
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
23
28
35
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Symbol
Cin
Parameter
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
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CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
79
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
Symbol
Parameter
Fig.
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
3
10
13
15
ns
th
Minimum Hold Time, Clock to Data
3
5.0
6.0
8.0
ns
Minimum Recovery Time, Reset Inactive to Clock
2
5.0
6.0
8.0
ns
tw
Minimum Pulse Width, Clock
1
15
19
22
ns
tw
Minimum Pulse Width, Reset
2
15
19
22
ns
Maximum Input Rise and Fall Times
1
trec
tr, tf
High–Speed CMOS Logic Data
DL129 — Rev 6
3
500
500
500
ns
MOTOROLA
MC74HCT174A
SWITCHING WAVEFORMS
tr
2.7 V
1.3 V
0.3 V
tw
CLOCK
tf
VCC
tw
GND
Q
GND
tPHL
1/fmax
tPLH
3.0 V
1.3 V
RESET
tPHL
1.3 V
Q
90%
1.3 V
10%
trec
CLOCK
tTLH
3.0 V
1.3 V
GND
tTHL
Figure 1.
Figure 2.
TEST POINT
VALID
OUTPUT
3.0 V
DATA
DEVICE
UNDER
TEST
1.3 V
GND
tsu
CL*
th
3.0 V
CLOCK
1.3 V
* Includes all probe and jig capacitance
GND
Figure 3.
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
CLOCK
9
D0
3
RESET
1
D1
4
D2
6
C
D
Q
2
Q
5 Q1
C
D
R
C
Q
D
D
13
D
Q
10
Q
12
MOTOROLA
D
Q
15 Q5
4
Q3
Q4
R
C
D5 14
Q2
R
C
D4
7
R
C
D3 11
Q0
R
R
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT174A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
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JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: [email protected] –TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
5
*MC74HCT174A/D*
MC74HCT174A/D
MOTOROLA
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