Kersemi IRFR010 Power mosfet Datasheet

IRFR010, SiHFR010
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
50
RDS(on) ()
VGS = 10 V
0.20
Qg (Max.) (nC)
10
Qgs (nC)
2.6
Qgd (nC)
4.8
Configuration
D
DPAK
(TO-252)
G
G
S
Low Drive Current
Surface Mount
Fast Switching
Ease of Paralleling
Excellent Temperature Stability
Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Single
D
•
•
•
•
•
•
S
N-Channel MOSFET
The Power MOSFET technology is the key to Vishay’s
advanced line of Power MOSFET transistors. The efficient
geometry and unique processing of this latest “State of the
Art” design achieves: very low on-state resistance
combined with high transconductance; superior reverse
energy and diode recovery dV/dt capability.
The Power MOSFET transistors also feature all of the well
established advantages of MOSFET’S such as voltage
control, very fast switching, ease of paralleling and
temperature stability of the electrical parameters.
Surface mount packages enhance circuit performance by
reducing stray inductances and capacitance. The DPAK
(TO-252) surface mount package brings the advantages of
Power MOSFET’s to high volume applications where PC
Board surface mounting is desirable. The surface mount
option IRFR9012, SiHFR9012 is provided on 16 mm tape.
The straight lead option IRFU9012, SiHFU9012 of the device
is called the IPAK (TO-251).
They are well suited for applications where limited heat
dissipation is required such as, computers and peripherals,
telecommunication equipment, dc-to-dc converters, and a
wide range of consumer products.
ORDERING INFORMATION
Package
DPAK (TO-252)
IRFR010PbF
SiHFR010-E3
IRFR010
SiHFR010
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
SYMBOL
LIMIT
VDS
VGS
50
± 20
8.2
5.2
33
1.5
0.20
25
2.0
- 55 to + 150
300d
ID
Pulsed Drain Currenta
IDM
Avalanche Currentb
IAS
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
PD
Peak Diode Recovery dV/dtc
dV/dt
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 100 μH, Rg = 25 .
c. ISD  8.2 A, dI/dt  130 A/μs, VDD  40 V, TJ  150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
UNIT
V
A
W/°C
W
V/ns
°C
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IRFR010, SiHFR010
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
-
110
Case-to-Sink
RthCS
-
1.7
-
Maximum Junction-to-Case (Drain)
RthJC
-
-
5.0
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 μA
50
-
-
V
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
nA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 20 V
-
-
± 500
VDS = 50 V, VGS = 0 V
-
-
250
VDS = 40 V, VGS = 0 V, TJ = 125 °C
-
-
1000
ID = 4.6 Ab
VGS = 10 V
VDS  50 V, ID = 3.6 A
μA
-
0.16
0.20

2.1
3.1
-
S
-
250
-
-
150
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 10
VGS = 10 V
ID = 7.3 A, VDS = 40 V,
see fig. 6 and 13b
VDD = 25 V, ID = 7.3 A,
Rg = 24 , RD = 3.3 , see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contactc
-
29
-
-
6.7
10
-
1.8
2.6
-
3.2
4.8
-
11
17
-
33
50
-
12
18
-
23
35
-
4.5
-
-
7.5
-
-
-
8.2
-
-
33
-
-
1.6
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
A
G
S
TJ = 25 °C, IS = 8.2 A, VGS = 0 Vb
TJ = 25 °C, IF = 7.3 A, dI/dt = 100 A/μsb
V
41
86
190
ns
0.15
0.33
0.78
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
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D
IRFR010, SiHFR010
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFR010, SiHFR010
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFR010, SiHFR010
VDS
VGS
RD
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
Fig. 9 - Maximum Drain Current vs. Case Temperature
10 %
VGS
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 10 - Breakdown Voltage vs. Temperature
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IRFR010, SiHFR010
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
D.U.T
RG
+
-
I AS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 12b - Unclamped Inductive Waveforms
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V DD
IRFR010, SiHFR010
Fig. 12c - Typical Transconductance vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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IRFR010, SiHFR010
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
Body diode forward drop
Ripple ≤ 5 %
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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VDD
ISD
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