Renesas HD74AC164RPEL Serial-in, parallel-out shift register Datasheet

HD74AC164/HD74ACT164
Serial-In, Parallel-Out Shift Register
REJ03D0253–0200Z
(Previous ADE-205-373 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC164/HD74ACT164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through
a 2-input AND gate synchronous with the Low-to-High transition of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs Low independent of the clock.
Features
• Outputs Source/Sink 24 mA
• HD74ACT164 has TTL-Compatible Inputs
• Ordering Information
Part Name
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC164P
DIP-14 pin
DP-14, -14AV
P
—
HD74AC164FPEL
SOP-14 pin (JEITA)
FP-14DAV
FP
EL (2,000 pcs/reel)
HD74AC164RPEL
SOP-14 pin (JEDEC)
FP-14DNV
RP
EL (2,500 pcs/reel)
HD74AC164TELL
TSSOP-14 pin
TTP-14DV
T
ELL (2,000 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
A 1
14 VCC
B 2
13 Q7
Q0 3
12 Q6
Q1 4
11 Q5
Q2 5
10 Q4
Q3 6
9 MR
GND 7
8 CP
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 8
HD74AC164/HD74ACT164
Logic Symbol
A
B
CP
MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Pin Names
A, B
CP
MR
Q0 to Q7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active Low)
Outputs
Functional Description
The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each
of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an
active High Enable for data entry through the other inputs. An unused input must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical
AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the Master Reset (MR)
input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.
Mode Select Table
Inputs
MR
Operating Mode
Reset (Clear)
Shift
H
L
X
qn
:
:
:
:
Outputs
A
L
H
H
H
H
B
X
L
L
H
H
Q0
X
L
H
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
L
L
L
L
H
High Voltage Level
Low Voltage Level
Immaterial
Lower case letters indicate the state of the referenced input or output one setup time prior to the Low-to-High
clock transition.
Logic Diagram
A
B
Q
D
D
Q
D
CD
CD
Q
D
CD
Q
D
CD
Q
D
CD
Q
D
CD
Q
D
CD
Q
CD
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 2 of 8
HD74AC164/HD74ACT164
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Condition
Supply voltage
DC input diode current
VCC
IIK
–0.5 to 7
–20
V
mA
VI
20
–0.5 to Vcc+0.5
mA
V
VI = Vcc+0.5V
DC input voltage
DC output diode current
IOK
–50
50
mA
mA
VO = –0.5V
VO = Vcc+0.5V
DC output voltage
DC output source or sink current
VO
IO
–0.5 to Vcc+0.5
±50
V
mA
DC VCC or ground current per output pin
Storage temperature
ICC, IGND
Tstg
±50
–65 to +150
mA
°C
VI = –0.5V
Recommended Operating Conditions: HD74AC164
Item
Symbol
Ratings
Unit
Supply voltage
Input and output voltage
VCC
VI, VO
2 to 6
0 to VCC
V
V
Operating temperature
Input rise and fall time
(except Schmitt inputs)
VIN 30% to 70% VCC
Ta
tr, tf
–40 to +85
8
°C
ns/V
Condition
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
DC Characteristics: HD74AC164
Item
Input Voltage
Symbol
Unit
Condition
min.
2.1
typ.
1.5
max.
—
min.
2.1
max.
—
4.5
5.5
3.15
3.85
2.25
2.75
—
—
3.15
3.85
—
—
3.0
4.5
—
—
1.50
2.25
0.9
1.35
—
—
0.9
1.35
5.5
3.0
—
2.9
2.75
2.99
1.65
—
—
2.9
1.65
—
4.5
5.5
4.4
5.4
4.49
5.49
—
—
4.4
5.4
—
—
3.0
4.5
2.58
3.94
—
—
—
—
2.48
3.80
—
—
5.5
3.0
4.94
—
—
0.002
—
0.1
4.80
—
—
0.1
4.5
5.5
—
—
0.001
0.001
0.1
0.1
—
—
0.1
0.1
3.0
4.5
—
—
—
—
0.32
0.32
—
—
0.37
0.37
IIN
5.5
5.5
—
—
—
—
0.32
±0.1
—
—
0.37
±1.0
µA
VIN = VCC or GND
IOLD
IOHD
5.5
5.5
—
—
—
—
—
—
86
–75
—
—
mA
mA
VOLD = 1.1 V
VOHD = 3.85 V
—
80
µA
VIN = VCC or ground
VOH
VOL
Input leakage
current
Dynamic output
current*
Ta = –40 to
+85°°C
3.0
VIH
VIL
Output voltage
Ta = 25°°C
Vcc
(V)
Quiescent supply
5.5
—
—
8.0
ICC
current
*Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 3 of 8
V
VOUT = 0.1 V or VCC –0.1 V
VOUT = 0.1 V or VCC –0.1 V
V
VIN = VIL or VIH
IOUT = –50 µA
VIN = VIL or VIH
IOH = –12 mA
IOH = –24 mA
IOH = –24 mA
VIN = VIL or VIH
IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
HD74AC164/HD74ACT164
Recommended Operating Conditions: HD74ACT164
Item
Symbol
Ratings
Unit
Supply voltage
Input and output voltage
VCC
VI, VO
2 to 6
0 to VCC
V
V
Operating temperature
Input rise and fall time
(except Schmitt inputs)
VIN 0.8 to 2.0 V
Ta
tr, tf
–40 to +85
8
°C
ns/V
Condition
VCC = 4.5V
VCC = 5.5V
DC Characteristics: HD74ACT164
Item
Input voltage
Output voltage
Symbol
Ta = 25°°C
VCC
(V)
Ta = –40 to
+85°°C
VIH
4.5
min.
2.0
VIL
5.5
4.5
2.0
—
1.5
1.5
—
0.8
2.0
—
—
0.8
VOH
5.5
4.5
—
4.4
1.5
4.49
0.8
—
—
4.4
0.8
—
5.5
4.5
5.4
3.94
5.49
—
—
—
5.4
3.80
—
—
5.5
4.5
4.94
—
—
0.001
—
0.1
4.80
—
—
0.1
5.5
4.5
—
—
0.001
—
0.1
0.32
—
—
0.1
0.37
VOL
typ.
1.5
max.
—
min.
2.0
max.
—
Unit
V
Condition
VOUT = 0.1 V or Vcc–0.1 V
VOUT = 0.1 V or Vcc–0.1 V
V
VIN = VIL or VIH
IOUT = –50 µA
VIN = VIL
IOH = –24 mA
IOH = –24 mA
VIN = VIL or VIH
IOUT = 50 µA
VIN = VIL
IOL = 24 mA
Input current
IIN
5.5
5.5
—
—
—
—
0.32
±0.1
—
—
0.37
±1.0
µA
VIN = VCC or GND
ICC/input current
Dynamic output
current*
ICCT
IOLD
5.5
5.5
—
—
0.6
—
—
—
—
86
1.5
—
mA
mA
VIN = VCC–2.1 V
VOLD = 1.1 V
IOHD
ICC
5.5
5.5
—
—
—
—
—
8.0
–75
—
—
80
mA
µA
VOHD = 3.85 V
VIN = VCC or ground
Quiescent supply
current
IOL = 24 mA
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC164
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
fmax
VCC (V)*1
Min
3.3
125
Typ
—
Max
—
100
—
MHz
tPLH
5.0
3.3
150
1.0
—
8.5
—
13.0
125
1.0
—
13.5
ns
CP to Qn
Propagation delay
tPHL
5.0
3.3
1.0
1.0
6.5
8.5
10.0
13.0
1.0
1.0
10.5
14.5
CP to Qn
Propagation delay
tPHL
5.0
3.3
1.0
1.0
6.5
9.5
10.0
16.0
1.0
1.0
10.5
18.0
1.0
7.5
11.5
1.0
13.5
Item
Maximum clock
frequency
Propagation delay
Symbol
5.0
MR to Qn
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 8
Min
Max
Unit
HD74AC164/HD74ACT164
AC Operating Requirements: HD74AC164
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Setup time A or B to CP
Symbol VCC (V)*1
Typ
tsu
3.3
3.0
Hold time CP to A or B
th
5.0
3.3
2.0
–1.5
4.0
0.0
4.5
0.0
Pulse width CP or MR
tw
5.0
3.3
–1.5
2.0
0.0
5.5
0.0
7.0
Recovery time MR or CP
trec
5.0
3.3
2.0
0.0
4.5
2.0
5.0
2.0
5.0
0.0
2.0
2.0
Note:
Guaranteed Minimum
5.5
6.0
Unit
ns
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT164
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
Maximum clock
fmax
5.0
frequency
Propagation delay
tPLH
5.0
CP to Qn
Propagation delay
tPHL
5.0
CP to Qn
Propagation delay
tPHL
5.0
MR to Qn
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C to +85°C
CL = 50 pF
Min
100
Typ
—
Max
—
Min
Max
Unit
80
—
MHz
1.0
9.0
11.5
1.0
12.5
ns
1.0
9.0
11.5
1.0
12.5
1.0
9.5
13.0
1.0
14.5
AC Operating Requirements: HD74AC164
Item
Ta = –40°C
to +85°C
Ta = +25°C
CL = 50 pF
CL = 50 pF
Typ
Guaranteed Minimum
Symbol VCC (V)*1
Setup time A or B to CP
Hold time CP to A or B
tsu
th
5.0
5.0
2.5
0.0
7.0
1.5
8.0
1.5
Pulse width CP or MR
Recovery time MR or CP
tw
trec
5.0
5.0
4.5
0.0
7.0
2.0
8.0
2.0
Note:
Unit
ns
1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Power dissipation capacitance
Rev.2.00, Jul.16.2004, page 5 of 8
Symbol
CIN
CPD
Typ
4.5
20.0
Unit
pF
pF
Condition
VCC = 5.5 V
VCC = 5.0 V
HD74AC164/HD74ACT164
Package Dimensions
As of January, 2003
Unit: mm
19.20
20.32 Max
8
6.30
7.40 Max
14
1.30
7
2.54 ± 0.25
0.48 ± 0.10
0.51 Min
2.39 Max
2.54 Min 5.06 Max
1
7.62
+ 0.10
0.25 – 0.05
0˚ – 15˚
Package Code
JEDEC
JEITA
Mass (reference value)
DP-14
Conforms
Conforms
0.97 g
Unit: mm
19.20
20.32 Max
8
6.30
7.40 Max
14
1.30
7
2.54 ± 0.25
*0.48 ± 0.08
0.51 Min
2.39 Max
2.54 Min 5.06 Max
1
7.62
*0.25 ± 0.06
0˚ – 15˚
*NI/Pd/AU Plating
Rev.2.00, Jul.16.2004, page 6 of 8
Package Code
JEDEC
JEITA
Mass (reference value)
DP-14AV
Conforms
Conforms
0.97 g
HD74AC164/HD74ACT164
As of January, 2003
Unit: mm
10.06
10.5 Max
8
5.5
14
1
1.42 Max
*0.20 ± 0.05
2.20 Max
7
*0.40 ± 0.06
1.15
0˚ – 8 ˚
0.10 ± 0.10
1.27
0.20
7.80 +– 0.30
0.70 ± 0.20
0.15
0.12 M
Package Code
JEDEC
JEITA
Mass (reference value)
*Ni/Pd/Au plating
FP-14DAV
—
Conforms
0.23 g
As of January, 2003
Unit: mm
8.65
9.05 Max
8
1
7
*0.20 ± 0.05
0.635 Max
1.75 Max
3.95
14
+ 0.10
6.10 – 0.30
1.08
*0.40 ± 0.06
0.11
0.14 +– 0.04
0˚ – 8˚
1.27
0.67
0.60 +– 0.20
0.15
0.25 M
*Ni/Pd/Au plating
Rev.2.00, Jul.16.2004, page 7 of 8
Package Code
JEDEC
JEITA
Mass (reference value)
FP-14DNV
Conforms
Conforms
0.13 g
HD74AC164/HD74ACT164
As of January, 2003
Unit: mm
4.40
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
*Ni/Pd/Au plating
Rev.2.00, Jul.16.2004, page 8 of 8
0.07 +0.03
–0.04
0.10
*0.15 ± 0.05
1.10 Max
0.83 Max
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-14DV
—
—
0.05 g
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