IRF D5001R803R3P High reliability radiation tolerant,low power,dc-dc converter Datasheet

PD-97809
HIGH RELIABILITY,
RADIATION TOLERANT,
LOW POWER,
DC-DC CONVERTER
D5001R803R3P
26 to 55V Input, Regulated Dual Outputs
(+1.8V and +3.3V)
Description
The D-Series of DC-DC converters are low power
radiation hardened, high reliability devices designed
for radiation environments such as those encountered
by geostationary earth orbit satellites, deep space
probes and communication systems. Features include
small size, high efficiency, low weight and a high
tolerance to total ionizing dose, single event effects,
and environmental stresses such as temperature
extremes, mechanical shock, and vibration. All
components are fully derated to meet the requirements
of EEE-INST-002. Extensive documentation including
worst case analysis, radiation susceptibility, thermal
analysis, stress analysis, and reliability analysis are
available.
.
The D-Series converters have two outputs, each is
independently regulated. The outputs can be both
positive or one positive and one negative. The D-Series
converters incorporate a fixed frequency flyback power
stage topology and internal EMI filter. The converters
include an enhanced input EMI filter that meets most
major satellite power buses. The converters can be
remotely turned on and off via an Inhibit pin. Additional
Inhibit pins are also provided to control the outputs
individually. This feature facilitates turn-on outputs
sequencing if desired. Each converter is encased in a
cold rolled steel hermetic package. The package
measures 1.80"L x 1.40"W x 0.42"H and weighs less
than 55 grams.The package utilizes rugged ceramic
feed-through copper core pins and is hermetically sealed
using parallel seam welding. Two package options are
available. Please refer to page 8 for I/O configurations.
Environmental screening includes temperature cycling,
constant acceleration, fine and gross leak, and burn-in
as specified by MIL-PRF-38534 for class H hybrids.
Features
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Total Dose > 50K Rad(Si)
SEE > 40MeV.cm2/mg
Low Weight < 55 grams
26V to 55V DC Input Range
Up to 10W Output Power
Independently Regulated Outputs:
+1.8V and +3.3V and Other Outputs Available
-55°C to +80°C Operating Temperature Range
100MΩ @ 100VDC Isolation
Input Under-Voltage Protection
Meets Conducted Emission Requirements
of Most Major Power Buses:
100Hz - 100KHz: 80dBµArms
100KHz - 10MHz: Log-linear Decrease
10MHz - 50MHz: 40dBµArms
Short Circuit and Overload Protection
Meets the Derating Requirments of
EEE-INST-002
Synchronization Input / Output
On/Off Control via Converters’s Inhibit Pin
and Individual Output’s Inhibit Pin
High CS Damping
Applications
n Launch Vehicles
n Communication Systems
n Geostationary or Low Earth Orbit Satellites
Non-flight versions of the D-Series converters are
available for system development purposes. Variations
in electrical specifications and screening to meet custom
requirements can be accommodated.
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1
05/24/13
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Circuit Description
The D-Series DC-DC converters utilize two-stage
regulation with a flyback topology with a switching
frequency of 250KHz for primary regulation and linear
post regulation in the secondary for each of the
outputs.
Output power is limited under any load fault
condition to approximately 110% of rated output.
An overload condition causes the converter output
to behave like a constant current source with the
output voltage dropping below nominal. The
converter will resume normal operation when the
load current is reduced below the current limit point.
This protects the converter from both overload and
short circuit conditions. There are no latching
elements to eliminate the possibility of falsely
triggering the protection circuits during single event
radiation exposure.
An under-voltage protection circuit prohibits the
converter from operating when the line voltage is
too low for safe operation. The converter will not
start until the line voltage rises to approximately 20V.
2
An inhibit pin is provided to control converter operation.
This inhibit pin is intended for operation with an open
collector transistor drive or a relay closure to the
input return. The pin may be left open for normal
operation and has a nominal open circuit voltage of
4.0V. Also provided are the individual output on/off
control pins (Pin 10, Output 1 Inhibit and Pin 9, Output
2 Inhibit).
Synchronization input pin is included allowing
multiple converters to operate at a common switching
frequency. Converters can be synchronized to a
common frequency with an external clock. This may
be used to eliminate beat frequency noise or to avoid
generating noise at certain frequencies for noise
sensitive systems.
Design Methodology
The D-Series is developed using a proven conservative
design methodology, which includes selecting
radiation tolerant and established reliability
components and fully derating to the requirements
of EEE-INST-002. Heavy derating of the radiationhardened power MOSFET virtually eliminates the
possibility of SEGR and SEB.
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Specifications
Absolute Maximum Ratings
Recommended Operating Conditions
Input voltage range
-0.5Vdc to +80Vdc Input voltage range (Note 13)
26Vdc to 55Vdc
Output power
Internally limited
0 to Max. Rated
Lead temperature
Output power
+300°C for 10sec
Operating temperature
-55°C to +115°C
Operating case temperature (Note 12) -55°C to +125°C
Operating temperature,
-55°C to +80°C
Storage temperature
derated (Note 13)
-55°C to +135°C
Electrical Performance Characteristics
Parameter
Group A
Subgroup
Conditions
-55°C ≤ TC ≤ +85°C
VIN = 42V DC ± 5%, CL = 0
unless otherwise specified
Input Voltage
Limits
Unit
Min
Nom
Max
26
42
55
V
1.782
1.800
1.818
V
3.267
3.300
3.333
1.746
1.800
1.854
3.200
3.300
3.399
Note 1
Output voltage (VOUT)
(Out 1 / Out 2)
1.8V
1
3.3V
1
1.8V
2.3
3.3V
2,3
IOUT = 100% rated load
IOUT = 100% rated load
V
Output power (POUT)
(Out 1/ Out 2)
1.8V
1,2,3
2.7
VIN = 26, 42, 55V, Notes 2, 11
W
5.0
Either Output
3.3V
Output power (IOUT)
(Out 1/ Out 2)
1.8V
1,2,3
3.3V
VIN = 26, 42, 55V, Notes 2, 11
0
1.5
Either Output
0
1.5
-0.2
0.2
%
-0.5
1.5
%
VIN = 26, 42, 55V, Note 1
5.0
mV
IOUT = 0, Pin 6 open
35
mA
Pin 6 connected to Pin 2
10
Line regulation (VRLINE )
Each output
1,2,3
VIN = 26, 42, 55V
Load regulation (VRLOAD )
Each output
1,2,3
IOUT = 0%, 50%, 100% rated
Cross regulation (VRCROSS )
Input current
IOUT = 0%, 50%, 100% rated
VIN = 26, 42, 55V
1,2,3
1,2,3
Switching frequency (FS)
1,2,3
Synchronization Input
1,2,3
Frequency range
A
225
250
275
KHz
External clock on sync In (Pin 4)
450
550
KHz
Pulse high level
Note 1
2.5
5.0
V
Pulse low level
-0.5
0.5
Pulse transition time
40
V
V/µs
Pulse duty cycle
20
80
%
For Notes to Electrical Performance Characteristic Table, refer to page 5
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3
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Electrical Performance Characteristics
Parameter
Group A
Subgroup
(continued)
Conditions
-55°C ≤ TC ≤ +85°C
VIN = 42V DC ± 5%, CL = 0
unless otherwise specified
Output ripple (VRIP)
VIN = 26, 42, 55V
Each output
IOUT = 100% rated load
1.8V
1,2,3
3.3V
Limits
Unit
Min
Nom
Max
50
Note 3
mV p-p
50
Output ripple @ switch
frequency
1,2,3
Efficiency (EFF)
1,2,3
IOUT = 100% rated load
45
1,2,3
Note 1
0
0.5
VIN = 26, 42, 55V
0.75
mV rms
IOUT = 100% rated load, Note 1
47
%
Enable Input (Inhibit)
Open circuit voltage
4
V
600
µA
-0.5
50
V
105
105
145
145
%
24
W
15
mV pk
Drive current (sink)
Voltage range
VOUT = 90% of Nominal
Note 10
Current Limit Point
Each output
1.8V
3.3V
1,2,3
Power dissipation load fault
(PD)
1,2,3
Short Circuit, Overload, Note 5
4,5,6
Half Load to/ from Full Load, Note 6
Output response to
step load changes (VTLD)
1.8V
3.3V
Recovery time,
step load changes (TTLD)
1.8V
3.3V
4,5,6
Half Load to/from Full Load, Notes 6, 7
Recovery time,
step line changes ( TTLN)
4,5,6
26V to/from 55V
IOUT = 100% rated load, Notes 1, 7, 8
Turn-on Response
Overshoot (VOS)
1.8V
3.3V
Turn-on Delay (TDLY)
4,5,6
Capacitive Load (CL )
1.8V
3.3V
1
-15
-15
10% Load, Full Load
Note 9
0.2
IOUT = 100% rated load
No effect on DC performance, Notes 1, 4
Each output
15
500
500
µs
100
µs
25
25
10
mV
220
220
µF
ms
For Notes to Electrical Performance Characteristic Table, refer to page 5
4
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Electrical Performance Characteristics
Parameter
EMC conducted
susceptibility
(Line rejection)
Electromagnetic Interference
(EMI), conducted emission
(CE)
Isolation
(continued)
Group A
Subgroup
Conditions
-55°C ≤ TC ≤ +85°C
VIN = 42V DC ± 5%, CL = 0
unless otherwise specified
1
IOUT = 100% rated load
Primary power sine wave injection of
2Vp-p, 100Hz to 50MHz, Note 1
1
1
Limits
Unit
Min
Nom
80
90
IOUT = 100% rated load, Note 1
Input to Output or Any Pin to Case
except pin 3, test @ 50VDC
dB
Limits per Figure 1
100
MΩ
Device Weight
MTBF
Max
55
MIL-HDBK-217F2, SF, 35°C
1 x 10
5
g
hours
Notes: Specification and Electrical Performance Characteristics
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Parameter is tested as part of design characterization or after design changes. Thereafter, parameter shall be
guaranteed to the limits specified.
Parameter verified during line and load regulation tests.
Guaranteed for a D.C. to 20MHz bandwidth. Tested using a 20KHz to 10MHz bandwidth.
Capacitive load may be any value from 0 to the maximum limit without compromising dc performance.
A capacitive load in excess of the maximum limit may interfere with the proper operation of the converter’s overload
protection, causing erratic behavior during turn-on.
Overload power dissipation is defined as the device power dissipation with the load set such that both outputs are in a
short circuit mode.
Load step transition time ≤ 10 µsec.
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady
state value.
Line step transition time ≤100 µsec.
Turn-on delay time from either a step application of input power or a logic low to a logic high transition on the inhibit pin
(pin 6) to the point where VOUT = 90% of nominal.
Current limit point expressed as a percentage of full rated load current.
For models with two positive outputs the envelope specification for the design is that each output voltage is limited to the
range 1V to 5V.
Although operation at temperatures between +85°C and +125°C is guaranteed, no parameter limits are specified.
Meets the derating requirements of EEE-INST-002 – except for ceramic capacitors with voltage stress below 10V will
minimum be rated at 50V and a minimum load of 20mA on each output.
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5
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Device Screening
Test / Inspection
Element Evaluation
Method
/EM Suffix Flight (No Suffix)
MIL-STD-38534 Class K equivalent with SEM
N/A
X
Nondestructive Bond Pull
MIL-STD-883, Method 2023
N/A
X
Internal Visual
MIL-STD-883, Method 2017
Note 1
X
Temperature Cycling
MIL-STD-883, Method 1010
N/A
Condition C
Constant Acceleration
MIL-STD-883, Method 2001, Y1 Axis
N/A
3000 G’s
PIND
MIL-STD-883, Method 2020
N/A
A
Burn-in (2 x 220 hours)
MIL-STD-883, Method 1015
48 Hours
440 Hours
@ 115°C
@ 115°C
In accordance with device specification
X
X
MIL-STD-883, Method 1014
Condition A
Final Electrical (Group A)
Seal
Fine Leak
A1
Gross Leak
C
Radiographic
MIL-STD-883, Method 2012
N/A
N/A
External Visual
MIL-STD-883, Method 2009
Note 1
Yes
Notes:
1. Best commercial practice
Radiation Performance Characteristics
Test
Conditions
Min
Unit
Total Ionizing Dose (Gamma) *
MIL-STD-883, Method 1019.5
Operating bias applied during exposure,
50
KRads (Si)
40
MeV·cm /mg
Full Rated Load, VIN = 50V
Heavy Ions (LET)
Single Event Effects *
Operating bias applied during exposure,
SEU, SEL, SEGR, SEB
Full Rated Load, VIN = 26, 42, 55V
2
* Test performed at TAMU
International Rectifier currently does not have a DSCC certified Radiation Hardness Assurance Program.
6
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Fig. 1 - EMI Conducted Emission Performance Limit
Fig. 2 - A Typical input EMI Conducted Emission Performance
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7
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Mechanical Outline - Option A (Straight Pins)
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š
5HI
3LQš
All dimensions are in inch.
.XX: ±0.01
.XXX: ±0.005
0D[
Mechanical Outline - Option B (Down Pins)
Ø 0.140
0.050
0.400
1.30 1.550 1.800
0.200 Typ.
Non-cum
1.000
Ref.
Pin Ø
0.040
0.220
1.400
0.41
1.650
1.90
1.70
0.15
0.420 Max.
8
All dimensions are in inch.
.XX: ±0.01
.XXX: ±0.005
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Block Diagram
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Pin Designation
Pin #
P
(Both Outputs Positive)
1
Input
2
Input Return
3
Case
4
Sync In
5
Sync Out
6
Inhibit
7
Output 2
8
Output 2 Return
9
Output 2 Inhibit
10
Output 1 Inhibit
11
Output 1 Return
12
Output 1
Note: Pins 8 and 11 are internally connected
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9
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Part Numbering
D 50 01R8 03R3 P A A /EM
Model
D = Two Outputs,
5W Max each,
RadiationTolerant Design
Input Voltage
50 = 50V
Output 1
01R8 = 1.8V
Output 2
03R3 = 3.3V
Quality Level
EM = Engineering Model
H = Class H per MIL-PRF-38534
Lead Finish
A = Solder Dipped
C = Gold Plated
Blank = for EM, Lead Finish as available
I/O Pin Option
A = Straight Pins
B = Down Pins
Output Configuration
P = Both Positive
WORLD HEADQUARTERS: 101 N, Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105
IR SAN JOSE: 2520 Junction Avenue, San Jose, California 95134, USA Tel: (408) 434-5000
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 05/2013
10
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