Fairchild FST16210MTD 20-bit bus switch Datasheet

FST16210 20-Bit Bus Switch
November 1998
Revised June 2005
FST16210
20-Bit Bus Switch
General Description
Features
The Fairchild Switch FST16210 provides 20-Bits of highspeed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
■ 4: switch connection between two ports.
The device is organized as a 10-bit or 20-Bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B.
■ Control inputs compatible with TTL level.
■ Minimal propagation delay through the switch.
■ Low lCC.
■ Zero bounce in flow-through mode.
Ordering Code:
Order Number
Package Number
Package Description
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FST16210MTD
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Truth Table
Pin Descriptions
Inputs
Inputs/Outputs
Description
OE1
OE2
OE1, OE2
Bus Switch Enables
L
1A, 2A
Bus A
L
1B, 2B
Bus B
H
L
Z
H
H
Z
Pin Name
© 2005 Fairchild Semiconductor Corporation
DS500193
1A, 1B
2A, 2B
L
1A
1B
2A
H
1A
1B
2B
Z
2B
2A
Z
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FST16210
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Switch Voltage (VS)
DC Input Voltage (VIN ) (Note 2)
DC Input Diode Current (lIK) VIN 0V
0.5V to 7.0V
0.5V to 7.0V
0.5V to 7.0V
50mA
DC Output (IOUT ) Sink Current
DC VCC/GND Current (ICC/IGND)
Storage Temperature Range (TSTG)
Recommended Operating
Conditions (Note 3)
4.0V to 5.5V
Power Supply Operating (VCC)
128mA
Input Voltage (VIN)
0V to 5.5V
Output Voltage (VOUT)
0V to 5.5V
Input Rise and Fall Time (tr, tf)
/ 100mA
65qC to 150 qC
Switch Control Input
0nS/V to 5nS/V
Switch I/O
0nS/V to DC
-40 qC to 85 qC
Free Air Operating Temperature (TA)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held high or low. They may not float.
DC Electrical Characteristics
Symbol
VCC
(V)
Parameter
40 qC to 85 qC
TA
Min
Typ
(Note 4)
Max
1.2
Clamp Diode Voltage
HIGH Level Input Voltage
4.0–5.5
VIL
LOW Level Input Voltage
4.0–5.5
0.8
V
II
Input Leakage Current
5.5
r1.0
PA
0d VIN d5.5V
0
10
PA
VIN
5.5
r1.0
PA
0 dA, B dVCC
RON
OFF-STATE Leakage Current
IIN
18mA
VIK
2.0
V
Conditions
VIH
IOZ
4.5
Units
V
5.5V
Switch On Resistance
4.5
4
7
:
VIN
0V, IIN
64mA
(Note 5)
4.5
4
7
:
VIN
0V, IIN
30mA
4.5
8
12
:
VIN
2.4V, IIN
15mA
4.0
11
20
:
VIN
2.4V, IIN
15mA
VCC or GND, IOUT
ICC
Quiescent Supply Current
5.5
3
PA
VIN
' ICC
Increase in ICC per Input
5.5
2.5
mA
One input at 3.4V
0
Other inputs at VCC or GND
Note 4: Typical values are at VCC
5.0V and T A
25qC
Note 5: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
TA
Symbol
Parameter
tPHL,tPLH
Propagation Delay Bus to Bus
(Note 6)
tPZH, tPZL
Output Enable Time
tPHZ, tPLZ
CL
Output Disable Time
40 qC to 85 qC,
50pF, RU
VCC
4.5 – 5.5V
Min
Max
1.5
1.5
RD
500:
VCC
Min
Units
Conditions
4.0V
Figure
No.
Max
0.25
0.25
ns
VI
OPEN
Figures
1, 2
6.0
6.5
ns
VI
7V for tPZL
VI
OPEN for tPZH
Figures
1, 2
VI
7V for tPLZ
VI
OPEN for tPHZ
7.0
7.2
ns
Figures
1, 2
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 7)
Symbol
CIN
CI/O
Note 7: TA
Parameter
Typ
Max
Units
Conditions
Control Pin Input Capacitance
3
pF
VCC
Input/Output Capacitance
6
pF
VCC, OE
25qC, f
5.0V
5.0V
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 : source terminated in 50 :
Note: C L includes load and stray capacitance
Note: Input PRR
1.0 MHz, tW
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FST16210
AC Electrical Characteristics
FST16210 20-Bit Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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4
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