TI1 OPA342 Low-cost, low-power, rail-to-rail operational amplifier Datasheet

OPA
OPA342
OPA2342
OPA4342
434
2
OPA
342
OPA
234
2
OPA
®
342
OPA
434
2
www.ti.com
Low-Cost, Low-Power, Rail-to-Rail
OPERATIONAL AMPLIFIERS
MicroAmplifier ™ Series
FEATURES
DESCRIPTION
LOW QUIESCENT CURRENT: 150µA typ
RAIL-TO-RAIL INPUT
RAIL-TO-RAIL OUTPUT (within 1mV)
SINGLE SUPPLY CAPABILITY
LOW COST
MicroSIZE PACKAGE OPTIONS:
SOT23-5
MSOP-8
TSSOP-14
● BANDWIDTH: 1MHz
● SLEW RATE: 1V/µs
● THD + NOISE: 0.006%
The OPA342 series rail-to-rail CMOS operational
amplifiers are designed for low-cost, low-power, miniature applications. They are optimized to operate on
a single supply as low as 2.5V with an input commonmode voltage range that extends 300mV beyond the
supplies.
Rail-to-rail input/output and high-speed operation make
them ideal for driving sampling Analog-to-Digital Converters (ADC). They are also well suited for generalpurpose and audio applications and providing I/V conversion at the output of Digital-to-Analog Converters
(DAC). Single, dual, and quad versions have identical
specs for design flexibility.
The OPA342 series offers excellent dynamic response
with a quiescent current of only 250µA max. Dual and
quad designs feature completely independent circuitry
for lowest crosstalk and freedom from interaction.
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APPLICATIONS
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COMMUNICATIONS
PCMCIA CARDS
DATA ACQUISITION
PROCESS CONTROL
AUDIO PROCESSING
ACTIVE FILTERS
TEST EQUIPMENT
CONSUMER ELECTRONICS
PACKAGE
SINGLE
OPA342
SOT23-5
✔
QUAD
OPA4342
✔
MSOP-8
SO-8
DUAL
OPA2342
✔
✔
TSSOP-14
✔
SO-14
✔
DIP-14
✔
SPICE MODEL available at www.burr-brown.com.
Copyright © 2000, Texas Instruments Incorporated
SBOS106A
Printed in U.S.A. August, 2000
SPECIFICATIONS: VS = 2.7V to 5.5V
At TA = +25°C, RL = 10kΩ connected to VS /2 and VOUT = VS /2, unless otherwise noted.
Boldface limits apply over the temperature range, TA = –40°C to +85°C.
OPA342NA, UA
OPA2342EA, UA
OPA4342EA, UA, PA
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
TA = –40°C to +85°C
vs Temperature
vs Power Supply
TA = –40°C to +85°C
Channel Separation, dc
f = 1kHz
CONDITION
VOS
dVOS/dT
PSRR
VCM = VS /2
VS = 2.7V to 5.5V, VCM < (V+) -1.8V
VS = 2.7V to 5.5V, VCM < (V+) -1.8V
±6
±6
mV
mV
µV/°C
µV/V
µV/V
µV/V
dB
200
250
8
30
0.5
VCM
CMRR
CMRR
CMRR
AOL
FREQUENCY RESPONSE
Gain-Bandwidth Product
GBW
Slew Rate
SR
Settling Time, 0.1%
0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise, f = 1kHz THD+N
OUTPUT
Voltage Output Swing from Rail(2)
TA = –40°C to +85°C
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance
SOT23-5 Surface Mount
MSOP-8 Surface Mount
SO-8 Surface Mount
TSSOP-14 Surface Mount
SO-14 Surface Mount
DIP-14
±1
±1
±3
30
en
in
TA = –40°C to +85°C
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current (per amplifier)
TA = –40°C to +85°C
UNITS
IOS
VS = +5.5V, –0.3V < VCM < (V+) - 1.8
VS = +5.5V, –0.3V < VCM < (V+) - 1.8
VS = +5.5V, –0.3V < VCM < 5.8V
VS = +5.5V, –0.3V < VCM < 5.8V
VS = +2.7V, –0.3V < VCM < 3V
VS = +2.7V, –0.3V < VCM < 3V
–0.3
76
74
66
64
62
60
INPUT IMPEDANCE
Differential
Common-Mode
TA = –40°C to +85°C
Short-Circuit Current
Capacitive Load Drive
MAX
±0.2
See Typical Curve
±0.2
IB
NOISE
Input Voltage Noise, f = 0.1Hz to 50kHz
Input Voltage Noise Density, f = 1kHz
Current Noise Density, f = 1kHz
OPEN-LOOP GAIN
Open-Loop Voltage Gain
TA = –40°C to +85°C
TYP
0.2
132
INPUT BIAS CURRENT
Input Bias Current
TA = –40°C to +85°C
Input Offset Current
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
TA = –40°C to +85°C
Common-Mode Rejection Ratio
TA = –40°C to +85°C
Common-Mode Rejection Ratio
TA = –40°C to +85°C
MIN
ISC
CLOAD
RL = 100kΩ, 10mV < VO < (V+) – 10mV
RL = 100kΩ, 10mV < VO < (V+) – 10mV
RL = 5kΩ, 400mV < VO < (V+) – 400mV
RL = 5kΩ, 400mV < VO < (V+) – 400mV
CL = 100pF
G=1
RL = 100kΩ, AOL ≥ 96dB
RL = 100kΩ, AOL ≥ 104dB
RL = 100kΩ, AOL ≥ 100dB
RL = 5kΩ, AOL ≥ 96dB
RL = 5kΩ, AOL ≥ 90dB
Per Channel
pA
pA
pA
±10
µVrms
nV/√Hz
fA/√Hz
(V+) + 0.3
V
dB
dB
dB
dB
dB
dB
88
78
74
1013 || 3
1013 || 6
Ω || pF
Ω || pF
124
dB
dB
dB
dB
114
1
1
5
8
2.5
0.006
VS = 5.5V, 2V Step
VS = 5.5V, 2V Step
VIN • G = VS
VS = 5.5V, VO = 3Vp-p(1), G = 1
VS
IQ
104
100
96
90
±10
MHz
V/µs
µs
µs
µs
%
1
3
mV
mV
mV
mV
mV
mA
10
10
400
400
20
±15
See Typical Curve
2.7
5.5
2.5 to 5.5
150
IO = 0A
–40
–55
–65
θJA
250
300
V
V
µA
µA
+85
+125
+150
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
200
150
150
100
100
100
NOTES: (1) VOUT = 0.25V to 3.25V. (2) Output voltage swings are measured between the output and power-supply rails.
2
OPA342, 2342, 4342
SBOS106A
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage, V+ to V- ................................................................... 7.5V
Signal Input Terminals, Voltage(2) ..................... (V–) –0.5V to (V+) +0.5V
Current(2) .................................................... 10mA
Output Short-Circuit(3) .............................................................. Continuous
Operating Temperature .................................................. –55°C to +125°C
Storage Temperature ..................................................... –65°C to +150°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C
ESD Tolerance (Human Body Model) ............................................ 4000V
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only. Functional operation of the device at these conditions, or beyond the specified operating
conditions, is not implied. (2) Input terminals are diode-clamped to the power
supply rails. Input signals that can swing more than 0.5V beyond the supply
rails should be current-limited to 10mA or less. (3) Short-circuit to ground,
one amplifier per package.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
OPA342NA
SOT23-5
331
–40°C to +85°C
B42
"
"
"
"
OPA342UA
"
OPA342UA
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
OPA342NA/250
OPA342NA /3K
OPA342UA
OPA342UA /2K5
Tape and Reel
Tape and Reel
Rails
Tape and Reel
OPA2342EA /250
OPA2342EA /2K5
OPA2342UA
OPA2342UA /2K5
Tape and Reel
Tape and Reel
Rails
Tape and Reel
OPA4342EA /250
OPA4342EA /2K5
OPA4342UA
OPA4342UA /2K5
OPA4342PA
Tape and Reel
Tape and Reel
Rails
Tape and Reel
Rails
SO-8
182
–40°C to +85°C
"
"
"
"
"
OPA2342EA
MSOP-8
337
–40°C to +85°C
C42
"
"
"
"
"
OPA2342UA
SO-8
182
–40°C to +85°C
OPA2342UA
"
"
"
"
"
OPA4342EA
TSSOP-14
357
–40°C to +85°C
OPA4342EA
"
"
"
"
"
OPA4342UA
SO-14
235
–40°C to +85°C
OPA4342UA
"
"
"
"
"
OPA4342PA
DIP-14
010
–40°C to +85°C
OPA4342PA
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /3K indicates 3000 devices per reel). Ordering 3000 pieces
of “OPA342NA/3K” will get a single 3000-piece Tape and Reel.
PIN CONFIGURATIONS
OPA342
Out
1
V–
2
+In
3
5
4
OPA4342
V+
–In
Out A
1
–In A
2
A
14
Out D
13
–In D
D
+In A
3
12
+In D
+V
4
11
–V
+In B
5
10
+In C
SOT23-5
OPA342
OPA2342
NC
1
8
NC
Out A
1
–In
2
7
V+
–In A
2
+In
3
6
Out
+In A
3
V–
4
5
NC
V–
4
A
B
B
C
8
V+
–In B
6
9
–In C
7
Out B
Out B
7
8
Out C
6
–In B
5
+In B
TSSOP-14, SO-14, DIP-14
SO-8
OPA342, 2342, 4342
SBOS106A
SO-8, MSOP-8
3
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.
POWER SUPPLY AND COMMON-MODE
REJECTION RATIO vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
100
100
30
80
+PSRR
Phase
80
60
60
90
40
120
Phase (°)
Gain (dB)
0
Gain
20
Rejection Ratio (dB)
120
0.1
10
1
100
1k
10k
100k
1M
60
40
20
150
0
CMRR
–PSRR
10
180
10M
10
100
Channel Separation (dB)
Maximum Output Voltage (Vp-p)
VS = +5.5V
5
VS = +5V
4
3
VS = +2.7V
2
1
120
100
Dual and quad devices.
G = 1, all channels.
Quad measured channel
A to D or B to C—other
combinations yield improved
rejection.
80
60
100k
10k
100
1M
100k
VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
VN
100
1
10
100
1k
10k
Frequency (Hz)
100k
1M
0.1
10M
0.1
THD+N (%)
10
1M
1
Current Noise (fA/√Hz)
IN
1000
10
10k
Frequency (Hz)
100
1
1k
Frequency (Hz)
10000
Voltage Noise (nV/√Hz)
100k
140
0
4
10k
CHANNEL SEPARATION vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
6
1k
Frequency (Hz)
Frequency (Hz)
0.010
0.001
20
100
1k
10k
20k
Frequency (Hz)
OPA342, 2342, 4342
SBOS106A
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.
OPEN-LOOP GAIN, COMMON-MODE REJECTION RATIO,
AND POWER SUPPLY REJECTION vs TEMPERATURE
INPUT BIAS CURRENT vs TEMPERATURE
140
10000
AOL
Input Bias Current (pA)
AOL, CMRR, PSRR (dB)
120
100
CMRR
80
PSRR
60
40
20
0
1000
100
10
1
0.1
–75
–50
–25
0
25
50
75
100
125
150
–75
–50
–25
Temperature (°C)
0
25
50
75
100
125
Temperature (°C)
QUIESCENT CURRENT AND
SHORT-CIRCUIT CURRENT vs TEMPERATURE
SLEW RATE vs TEMPERATURE
200
40
1.2
175
35
1
30
135
25
+ISC
100
20
–ISC
75
15
50
10
25
5
0
–75
–50
25
0
–25
50
75
100
Slew Rate (V/µs)
IQ
150
Short-Circuit Current (mA)
Quiescent Current (µA)
–SR
0.8
+SR
0.6
0.4
0.2
0
0
125
–75
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
INPUT BIAS CURRENT
vs COMMON-MODE VOLTAGE
QUIESCENT CURRENT AND
SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE
125
160
6
20
V–
Supply
2
V+
Supply
Quiescent Current (µA)
Input Bias Current (pA)
4
0
–2
Input voltage ≤ –0.3V
can cause op amp output
to lock up. See text.
–4
155
15
–ISC
150
10
IQ
145
5
140
–6
–1
0
1
2
3
4
Common-Mode Voltage (V)
OPA342, 2342, 4342
SBOS106A
5
6
Short-Circuit Current (mA)
+ISC
0
2
3
4
5
6
Supply Voltage (V)
5
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.
OPEN-LOOP GAIN vs OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
V+
120
–40°C
(V+) – 2
2
85°C
25°C
≈
≈
25°C
–40°C
1
85°C
Open-Loop Gain (dB)
Output Voltage (V)
(V+) – 1
0
RL = 100kΩ
100
RL = 5kΩ
90
80
5
0
10
15
120
20
100
80
60
40
20
Output Current (mA)
Output Voltage Swing from Rail (mV)
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
24
16
12
8
4
0
18
Typical production
distribution of
packaged units.
16
Percent of Amplifiers (%)
Typical production
distribution of
packaged units.
20
Percent of Amplifiers (%)
110
14
12
10
8
6
4
2
0
–6
–5.4
–4.8
–4.2
–3.6
–3
–2.4
–1.8
–1.2
–0.6
0
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
10
0
Offset Voltage (mV)
Offset Voltage Drift (µV/°C)
QUIESCENT CURRENT
PRODUCTION DISTRIBUTION
SETTLING TIME vs CLOSED-LOOP GAIN
400
350
20
300
Settling Time (µs)
Percent of Amplifiers (%)
24
16
12
8
250
0.01%
200
150
100
0.1%
4
50
0
<250
<225
<200
<175
<150
<125
<100
<75
<50
<25
<0
0
1
10
100
1000
Closed-Loop Gain (V/V)
Quiescent Current (µA)
6
OPA342, 2342, 4342
SBOS106A
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
G = +1, RL = 10kΩ, CL = 100pF
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
50
40
35
G = +1
30
1V/div
Small-Signal Overshoot (%)
45
G = +5
25
G = –1
20
15
10
G = –5
5
0
1
10
100
1k
10k
5µs/div
Load Capacitance (pF)
20mV/div
SMALL-SIGNAL STEP RESPONSE
G = +1, RL = 10kΩ, CL = 100pF
5µs/div
OPA342, 2342, 4342
SBOS106A
7
APPLICATIONS INFORMATION
OPA342 series op amps are unity gain stable and can operate
on a single supply, making them highly versatile and easy to
use.
Rail-to-rail input and output swing significantly increases
dynamic range, especially in low supply applications. Figure
1 shows the input and output waveforms for the OPA342 in
unity-gain configuration. Operation is from VS = +5V with
a 10kΩ load connected to VS /2. The input is a 5Vp-p
sinusoid. Output voltage is approximately 4.997Vp-p.
Power supply pins should be by passed with 0.01µF ceramic
capacitors.
G = +1, VS = +5V
Input
1V/div
5V
0V
Output (inverted on scope)
OPERATING VOLTAGE
OPA342 series op amps are fully specified and guaranteed
from +2.7V to +5.5V. In addition, many specifications apply
from –40ºC to +85ºC. Parameters that vary significantly
with operating voltages or temperature are shown in the
Typical Performance Curves.
RAIL-TO-RAIL INPUT
The input common-mode voltage range of the OPA342
series extends 300mV beyond the supply rails. This is
achieved with a complementary input stage—an N-channel
input differential pair in parallel with a P-channel differential pair (see Figure 2). The N-channel pair is active for input
voltages close to the positive rail, typically (V+) – 1.3V to
300mV above the positive supply, while the P-channel pair
is on for inputs from 300mV below the negative supply to
approximately (V+) –1.3V. There is a small transition region, typically (V+) – 1.5V to (V+) – 1.1V, in which both
pairs are on. This 400mV transition region can vary 300mV
with process variation. Thus, the transition region (both
stages on) can range from (V+) – 1.8V to (V+) – 1.4V on the
low end, up to (V+) – 1.2V to (V+) – 0.8V on the high end.
Within the 400mV transition region PSRR, CMRR, offset
voltage, offset drift, and THD may be degraded compared to
operation outside this region. For more information on
designing with rail-to-rail input op amps, see Figure 3
“Design Optimization with Rail-to-Rail Input Op Amps.”
5µs/div
FIGURE 1. Rail-to-Rail Input and Output.
V+
Reference
Current
VIN+
VIN–
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V–
(Ground)
FIGURE 2. Simplified Schematic.
8
OPA342, 2342, 4342
SBOS106A
DESIGN OPTIMIZATION WITH RAIL-TO-RAIL INPUT OP AMPS
With a unity-gain buffer, for example, signals will traverse
this transition at approximately 1.3V below V+ supply
and may exhibit a small discontinuity at this point.
The common-mode voltage of the non-inverting amplifier is equal to the input voltage. If the input signal always
remains less than the transition voltage, no discontinuity
will be created. The closed-loop gain of this configuration can still produce a rail-to-rail output.
Inverting amplifiers have a constant common-mode voltage equal to VB. If this bias voltage is constant, no
discontinuity will be created. The bias voltage can generally be chosen to avoid the transition region.
Rail-to-rail op amps can be used in virtually any op amp
configuration. To achieve optimum performance, however, applications using these special double-input-stage
op amps may benefit from consideration of their special
behavior.
In many applications, operation remains within the common-mode range of only one differential input pair.
However some applications exercise the amplifier through
the transition region of both differential input stages.
Although the two input stages are laser trimmed for
excellent matching, a small discontinuity may occur in
this transition. Careful selection of the circuit configuration, signal levels and biasing can often avoid this transition region.
G = 1 Buffer
Non-Inverting Gain
V+
Inverting Amplifier
V+
VB
VO
VIN
V+
VIN
VO
VO
VIN
VB
VCM = VIN = VO
VCM = VIN
VCM = VB
FIGURE 3. Design Optimization with Rail-to-Rail Input Op Amps.
COMMON-MODE REJECTION
The CMRR for the OPA342 is specified in several ways so
the best match for a given application may be used. First, the
CMRR of the device in the common-mode range below the
transition region (VCM < (V+) – 1.8V) is given. This specification is the best indicator of the capability of the device
when the application requires use of one of the differential
input pairs. Second, the CMRR at VS = 5.5V over the entire
common-mode range is specified. Third, the CMRR at VS =
2.7V over the entire common-mode range is provided. These
last two values include the variations seen through the
transition region.
INPUT VOLTAGE BEYOND THE RAILS
If the input voltage can go more than 0.3V below the
negative power supply rail (single-supply ground), special
precautions are required. If the input voltage goes sufficiently negative, the op amp output may lock up in an
inoperative state. A Schottky diode clamp circuit will prevent this—see Figure 4. The series resistor prevents excessive current (greater than 10mA) in the Schottky diode and
in the internal ESD protection diode, if the input voltage can
exceed the positive supply voltage. If the signal source is
limited to less than 10mA, the input resistor is not required.
RAIL-TO-RAIL OUTPUT
A class AB output stage with common-source transistors is
used to achieve rail-to-rail output. This output stage is
capable of driving 600Ω loads connected to any potential
OPA342, 2342, 4342
SBOS106A
between V+ and ground. For light resistive loads (> 50kΩ),
the output voltage can typically swing to within 1mV from
supply rail. With moderate resistive loads (2kΩ to 50kΩ),
the output can swing to within a few tens of milli-volts from
the supply rails while maintaining high open-loop gain. See
the typical performance curve “Output Voltage Swing vs
Output Current.”
V+
IOVERLOAD
10mA max
OPA342
VOUT
VIN
1kΩ
IN5818
Schottky diode is required only
if input voltage can go more
than 0.3V below ground.
FIGURE 4. Input Current Protection for Voltages Exceeding the Supply Voltage.
CAPACITIVE LOAD AND STABILITY
The OPA342 in a unity-gain configuration can directly drive
up to 250pF pure capacitive load. Increasing the gain enhances the amplifier’s ability to drive greater capacitive
loads. See the typical performance curve “Small-Signal
9
DRIVING A/D CONVERTERS
The OPA342 series op amps are optimized for driving
medium-speed sampling ADCs. The OPA342 op amps buffer
the ADC’s input capacitance and resulting charge injection
while providing signal gain.
Overshoot vs Capacitive Load.” In unity-gain configurations, capacitive load drive can be improved by inserting a
small (10Ω to 20Ω) resistor, RS, in series with the output, as
shown in Figure 5. This significantly reduces ringing while
maintaining dc performance for purely capacitive loads.
However, if there is a resistive load in parallel with the
capacitive load, a voltage divider is created, introducing a dc
error at the output and slightly reducing the output swing.
The error introduced is proportional to the ratio RS /RL, and
is generally negligible.
Figures 6 shows the OPA342 in a basic noninverting configuration driving the ADS7822. The ADS7822 is a 12-bit,
micro-power sampling converter in the MSOP-8 package.
When used with the low-power, miniature packages of the
OPA342, the combination is ideal for space-limited, lowpower applications. In this configuration, an RC network at
the ADC’s input can be used to filter charge injection.
V+
Figure 7 shows the OPA2342 driving an ADS7822 in a
speech bandpass filtered data acquisition system. This small,
low-cost solution provides the necessary amplification and
signal conditioning to interface directly with an electret
microphone. This circuit will operate with VS = +2.7V to
+5V with less than 500µA quiescent current.
RS
VOUT
OPA342
10Ω to
20Ω
VIN
RL
CL
FIGURE 5. Series Resistor in Unity-Gain Configuration
Improves Capacitive Load Drive.
+5V
0.1µF
0.1µF
1 VREF
8 V+
DCLOCK
500Ω
+In
OPA342
ADS7822
12-Bit A/D
2
VIN
DOUT
–In
CS/SHDN
3
3300pF
7
6
Serial
Interface
5
GND 4
VIN = 0V to 5V for
0V to 5V output.
NOTE: A/D Input = 0 to VREF
RC network filters high frequency noise.
FIGURE 6. OPA342 in Noninverting Configuration Driving ADS7822.
V+ = +2.7V to 5V
Passband 300Hz to 3kHz
R9
510kΩ
R1
1.5kΩ
R2
1MΩ
R4
20kΩ
C3
33pF
C1
1000pF
1/2
OPA2342
Electret
Microphone(1)
R3
1MΩ
R6
100kΩ
R7
51kΩ
R8
150kΩ
VREF 1
8 V+
7
C2
1000pF
1/2
OPA2342
+IN
ADS7822 6
12-Bit A/D
5
2
–IN
DCLOCK
DOUT
CS/SHDN
Serial
Interface
3
4
NOTE: (1) Electret microphone
powered by R1.
R5
20kΩ
G = 100
GND
FIGURE 7. Speech Bandpass Filtered Data Acquisition System.
10
OPA342, 2342, 4342
SBOS106A
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2342EA/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
C42
OPA2342EA/250G4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
C42
OPA2342EA/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
C42
OPA2342UA
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2342UA
OPA2342UA/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2342UA
OPA2342UA/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2342UA
OPA2342UAG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2342UA
OPA342NA/250
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B42
OPA342NA/250G4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B42
OPA342NA/3K
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B42
OPA342NA/3KG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B42
OPA342UA
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
342UA
OPA342UAG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
342UA
OPA4342EA/250
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
4342EA
OPA4342PA
LIFEBUY
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA4342UA
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4342UA
OPA4342UAG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4342UA
Addendum-Page 1
OPA4342PA
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2016
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2342EA/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2342EA/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2342UA/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4342EA/250
TSSOP
PW
14
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2342EA/250
VSSOP
DGK
OPA2342EA/2K5
VSSOP
DGK
8
250
210.0
185.0
35.0
8
2500
367.0
367.0
35.0
OPA2342UA/2K5
SOIC
D
8
2500
367.0
367.0
35.0
OPA4342EA/250
TSSOP
PW
14
250
210.0
185.0
35.0
Pack Materials-Page 2
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