MOTOROLA MC74HC163AD Presettable counters high-performance silicon-gate cmo Datasheet

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HCT161A and HCT163A are identical in pinout to the LS161A
and LS163A. These devices may be used as level converters for interfacing
TTL or NMOS outputs to high speed CMOS inputs.
The HCT161A and HCT163A are programmable 4–bit binary counters with
asynchronous and synchronous reset, respectively.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL, NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
Operating Voltage Range: 4.5 to 5.5 V
1
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 200 FETs or 50 Equivalent Gates
1
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
LOGIC DIAGRAM
P0
Preset
Data
Inputs
P1
P2
P3
Clock
Reset
Load
Count
Enables
Enable P
Enable T
3
14
4
13
5
12
6
11
2
15
Ceramic
Plastic
SOIC
Q0
Q1
BCD or Binary
Outputs
Q2
Q3
Device
Count Mode
Reset Mode
HCT161A
HCT163A
Binary
Binary
Asynchronous
Synchronous
Ripple
Carry Out
Pinout: 16–Lead Package (Top View)
1
VCC RCO*
Pin 16 = VCC
Pin 8 = GND
9
7
16
15
1
2
Q0
Q1
Q2
Q3
14
13
12
11
Enable
T
Load
10
9
10
FUNCTION TABLE
Inputs
Clock
Reset*
L
H
H
H
H
Load
X
L
H
H
H
Enable P
X
X
H
L
X
Enable T
X
X
H
X
L
Output
Q
Reset
Load Preset Data
Count
No Count
No Count
Reset Clock
10/95
1
4
5
6
P1
P2
P3
* RCO = Ripple Carry Out
H = High Level; L = Low Level; X = Don’t Care
* = HCT163A only. HCT161A is an “Asynchronous–Reset” device.
 Motorola, Inc. 1995
3
P0
REV 2
7
8
Enable GND
P
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MC54/74HCT161A MC54/74HCT163A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Positive DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature Range
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
Ceramic DIP
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
VCC
Symbol
Parameter
Guaranteed Limit
Test Conditions
V
– 55 to 25_C
≤ 85°C
≤ 125°C
Unit
v
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
v
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC = –1.0V
|Iout|
20 µA
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V
|Iout|
20 µA
4.5
5.5
0.80
0.80
0.80
0.80
0.80
0.80
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
3.98
3.84
3.70
V
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.10
0.10
0.10
0.10
0.10
0.10
V
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
0.26
0.33
0.40
V
VOH
v
v
VOL
Maximum Low–Level Output
Voltage
v
v
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.10
± 1.00
± 1.00
µA
ICC
Maximum Quiescent Supply
Current (Per Package)
Vin = VCC or GND
Iout – 0 µA
5.5
4
40
160
µA
ICC
Additional Quiescent Supply
Current
Vin = 2.4V,
Any One Input
VIN = VCC or GND
Other Inputs Iout – 0 µA
Iin
≥–55°C
25 to +125°C
2.9
2.4
mA
5.5
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Fig
– 55 to 25_C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)*
1,7
30
24
20
MHz
tPLH
Maximum Propagation Delay Clock to Q
1,7
20
23
28
ns
1,7
25
30
32
ns
tPHL
tPHL
Maximum Propagation Delay Reset to Q (HCT161A Only)
2,7
25
29
33
ns
tPLH
Maximum Propagation Delay Enable T to Ripple Carry Out
3,7
16
18
20
ns
3,7
21
24
28
ns
1,7
22
25
28
ns
tPHL
tPLH
Maximum Propagation Delay Clock to Ripple Carry Out
tPHL
1,7
28
33
35
ns
tPHL
Maximum Propagation Delay Reset to Ripple Carry Out
(HCT161A Only)
2,7
24
28
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
2,7
15
19
22
ns
Maximum Input Capacitance
1,7
10
10
10
pF
Cin
* Applies to noncascaded/nonsynchronous clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable. See
Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
pF
60
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Fig.
– 55 to
25_C
≤85°C
≤125°C
Unit
Minimum Setup Time, Preset Data Inputs to Clock
5
12
18
20
ns
Minimum Setup Time, Load to Clock
5
12
18
20
ns
4
12
18
20
ns
Minimum Setup Time, Enable T or Enable P to Clock
6
12
18
20
ns
Minimum Hold Time, Clock to Preset Data Inputs
5
3
3
3
ns
Minimum Hold Time, Clock to Load
5
3
3
3
ns
4
3
3
3
ns
6
3
3
3
ns
2
12
17
23
ns
2
12
17
23
ns
1
12
15
18
ns
1
12
15
18
ns
500
500
500
ns
Symbol
tsu
Parameter
Minimum Setup Time, Reset to Clock
th
Minimum Hold Time, Clock to Reset
(HCT163A Only)
(HCT163A Only)
Minimum Hold Time, Clock to En T or En P
trec
Minimum Recovery Time, Reset Inactive to Clock
(HCT161A Only)
Minimum Recovery Time, Load Inactive to Clock
tw
Minimum Pulse Width, Clock
Minimum Pulse Width, Reset
tr, tf
(HCT161A Only)
Maximum Input Rise and Fall Times
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
FUNCTION DESCRIPTION
CONTROL FUNCTIONS
The HCT161A/163A are programmable 4–bit synchronous
counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and count–enable
controls.
The HCT161A and HCT163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.
Resetting
A low level on the Reset pin (pin 1) resets the internal flip–
flops and sets the outputs (Q0 through Q3) to a low level. The
HCT161A resets asynchronously, and the HCT163A resets
with the rising edge of the Clock input (synchronous reset).
Loading
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
INPUTS
Clock (Pin 2)
The internal flip–flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading occur with the
rising edge of the Clock input. In addition, control functions,
such as resetting (HCT163A) and loading occur with the rising
edge of the Clock Input.
Count Enable/Disable
These devices have two count–enable control pins: Enable
P (Pin 7) and Enable T (Pin 10). The devices count when these
two pins and the Load pin are high. The logic equation is:
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
Count Enable = Enable P • Enable T • Load
These are the data inputs for programmable counting. Data
on these pins may be synchronously loaded into the internal
flip–flops and appear at the counter outputs. P0 (Pin 3) is the
least–significant bit and P3 (Pin 6) is the most–significant bit.
The count is either enabled or disabled by the control inputs
according to Table 1. In general, Enable P is a count–enable
control: Enable T is both a count–enable and a Ripple–Carry
Output control.
OUTPUTS
Table 1. Count Enable/Disable
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
Control Inputs
These are the counter outputs. Q0 (Pin 14) is the least–significant bit and Q3 (Pin 11) is the most–significant bit.
Load
Ripple Carry Out (Pin 15)
When the counter is in its maximum state 1111, this output
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count state.
The logic equation for this output is:
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3
Result at Outputs
Enable Enable
P
T
Q0–Q3
Ripple Carry Out
H
H
H
Count
High when Q0–Q3
L
H
H
No Count
are maximum*
X
L
H
No Count
High when Q0–Q3
are maximum*
X
X
L
No Count
L
Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
OUTPUT STATE DIAGRAM
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
Binary Counters
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A
SWITCHING WAVEFORMS
tr
tf
tw
90%
1.3V
10%
Clock
3.0V
3.0V
Reset
1.3V
GND
GND
tw
tPHL
1/fMAX
tPHL
tPLH
Any
Output
Any
Output
90%
1.3V
10%
1.3V
trec
tTLH
3.0V
Clock
tTHL
1.3V
GND
Figure 1.
tr
Figure 2.
tf
3.0V
90%
1.3V
10%
Enable T
3.0V
Reset
1.3V
GND
tPLH
GND
tPHL
tsu
90%
1.3V
10%
Ripple
Carry Out
Clock
3.0V
1.3V
GND
tTLH
tTHL
Figure 3.
Figure 4. HCT163A Only
3.0V
Inputs P0,
P1, P2, P3
1.3V
Valid
GND
tsu
3.0V
Enable T
or
Enable P
th
3.0V
Load
1.3V
GND
1.3V
tsu
Clock
th
th
tsu
GND
trec
Clock
3.0V
th
3.0V
1.3V
GND
1.3V
GND
Figure 5.
Figure 6.
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
P0
P1
P2
P3
T0
R
C
C
Load
Load
P0
3
T1
R
C
C
Load
Load
P1
4
T2
R
C
C
Load
Load
P2
5
T3
R
C
C
Load
Load
P3
6
14
Q0
Q0
Q0
13
Q1
Q1
Q1
12
Q2
Q2
Q2
11
Q3
Q3
15 Ripple
Carry Out
Enable P
Enable T
Reset
Load
7
10
1
9
R
Load
Load
Clock
2
C
C
The flip–flops shown in the circuit diagrams are Toggle–
Enable flip–flops. A Toggle–Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data
from Preset inputs P0, P1, P2 and P3, the Load signal is
used to disable the Toggle input (Tn) of the flip–flop. The
logic level at the Pn input is then clocked to the Q output of
the flip–flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal
clock (C) high and resets the Q output of the flip–flop low.
Figure 8. 4–Bit Binary Counter with Asynchronous Reset (MC54/74HCT161A)
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A
Reset (HCT161A)
(Asynchronous)
Reset (HCT163A)
(Synchronous)
Load
P0
Preset
Data
Inputs
P1
P2
P3
Clock (HCT161A)
Clock (HCT163A)
Count
Enables
Enable P
Enable T
Q0
Q1
Outputs
Q2
Q3
Ripple Carry Out
12
Reset
13
14
15
0
Count
1
2
Inhibit
Load
Figure 9. Timing Diagram
High–Speed CMOS Logic Data
DL129 — Rev 6
7
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
P0
P1
P2
P3
T0
R
C
C
Load
Load
P0
3
T1
R
C
C
Load
Load
P1
4
T2
R
C
C
Load
Load
P2
5
T3
R
C
C
Load
Load
P3
6
14
Q0
Q0
Q0
13
Q1
Q1
Q1
12
Q2
Q2
Q2
11
Q3
Q3
15 Ripple
Carry Out
Enable P
Enable T
Reset
Load
7
10
1
9
R
Load
Load
Clock
2
C
C
The flip–flops shown in the circuit diagrams are Toggle–
Enable flip–flops. A Toggle–Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data
from Preset inputs P0, P1, P2 and P3, the Load signal is
used to disable the Toggle input (Tn) of the flip–flop. The
logic level at the Pn input is then clocked to the Q output of
the flip–flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal
clock (C) high and resets the Q output of the flip–flop low.
Figure 10. 4–Bit Binary Counter with Synchronous Reset (MC54/74HCT163A)
MOTOROLA
8
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A
TYPICAL APPLICATIONS CASCADING
Load
Inputs
Load
H=Count
L=Disable
H=Count
L=Disable
Inputs
Q0 Q1 Q2 Q3
Enable P
Enable T
Q0 Q1 Q2 Q3
Enable P
Ripple
Carry
Out
Clock
Reset
Load
Enable T
Reset
Load
Q0 Q1 Q2 Q3
Enable P
Ripple
Carry
Out
Clock
Q0 Q1 Q2 Q3
Inputs
Enable T
Ripple
Carry
Out
To More
Significant
Stages
Clock
Q0 Q1 Q2 Q3
Reset
Q0 Q1 Q2 Q3
Reset
Outputs
Outputs
Outputs
Clock
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will
depend on number of stages. This limitation is due to set–up times between Enable (port) and clock.
Figure 11. N–Bit Synchronous Counters
Inputs
Inputs
Inputs
Load
Enable P
Enable T
Load
Q0 Q1 Q2 Q3
Enable P
Enable T
Clock
Q0 Q1 Q2 Q3
Enable P
Ripple
Carry
Out
Clock
Reset
Load
Enable T
Reset
Q0 Q1 Q2 Q3
Enable P
Ripple
Carry
Out
Clock
Q0 Q1 Q2 Q3
Load
Enable T
Ripple
Carry
Out
To More
Significant
Stages
Clock
Q0 Q1 Q2 Q3
Reset
Q0 Q1 Q2 Q3
Reset
Outputs
Outputs
Outputs
Figure 12. Nibble Ripple Counter
High–Speed CMOS Logic Data
DL129 — Rev 6
9
MOTOROLA
MC54/74HCT161A MC54/74HCT163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HCT163A
Other
Inputs
HCT163A
Q0
Q1
Other
Inputs
Optional Buffer
for Noise Rejection
Q2
Q0
Q1
Optional Buffer
for Noise Rejection
Q2
Output
Q3
Output
Q3
Reset
Reset
Figure 13. Modulo–5 Counter
Figure 14. Modulo–11 Counter
The HCT163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–
free due to the synchronous Reset.
MOTOROLA
10
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
High–Speed CMOS Logic Data
DL129 — Rev 6
M
T
B
S
A
S
11
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
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MC54/74HCT161A MC54/74HCT163A
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MC54/74HCT161A/D
High–Speed CMOS Logic Data
DL129 — Rev 6
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