Rhombus FECL-6 10k ecl logic buffered delay 16-pin module Datasheet

10K ECL Logic Buffered Delay 16-Pin Modules
5-Tap: DECL • Single: FECL • Triple: MECL
Electrical Specifications at 25OC
Delay
Single
Triple
(ns)
10K P/N
10K P/N
FECL-3
MECL-3
3 ± 0.5
FECL-4
MECL-4
4 ± 0.5
FECL-5
MECL-5
5 ± 0.5
FECL-6
MECL-6
6 ± 0.75
FECL-7
MECL-7
7 ± 0.75
FECL-8
MECL-8
8 ± 0.8
FECL-9
MECL-9
9 ± 1.0
FECL-10
MECL-10
10 ± 1.0
FECL-15
MECL-15
15 ± 1.5
FECL-20
MECL-20
20 ± 1.5
FECL-25
MECL-25
25 ± 1.5
FECL-50
MECL-50
50 ± 2.5
FECL-60
---60 ± 3.0
FECL-75
---75 ± 3.75
FECL-100
---100 ± 5.0
Electrical Specifications at 25OC
Tap Delay Tolerances +/- 5% or 1.5ns (+/- 0.8ns <10ns)
10K ECL
5 Tap P/N
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
2.0
2.0
3.0
4.0
5.0
6.0
8.0
9.0
10.0
15.0
20.0
25.0
30.0
40.0
50.0
DECL-6
DECL-10
DECL-15
DECL-20
DECL-25
DECL-30
DECL-40
DECL-45
DECL-50
DECL-75
DECL-100
DECL-125
DECL-150
DECL-200
DECL-250
3.0
4.0
6.0
8.0
10.0
12.0
16.0
18.0
20.0
30.0
40.0
50.0
60.0
80.0
100.0
4.0
6.0
9.0
12.0
15.0
18.0
24.0
27.0
30.0
45.0
60.0
75.0
90.0
120.0
150.0
5.0
8.0
12.0
16.0
20.0
24.0
32.0
36.0
40.0
60.0
80.0
100.0
120.0
160.0
200.0
Tap-to-Tap
(ns)
6 ± 0.8
10 ± 1.0
15 ± 1.5
20 ± 1.5
25 ± 1.5
30 ± 1.5
40 ± 2.0
45 ± 2.25
50 ± 2.5
75 ± 3.75
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
∗∗ 1 ± 0.4
2 ± 0.6
3 ± 0.8
4 ± 1.0
5 ± 1.0
6 ± 1.5
8 ± 2.0
9 ± 2.0
10 ± 2.0
15 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
** This part numbers does not have 5 equal taps.
Specified Tap-to-Tap Delays are referenced to Tap 1.
OPERATING SPECIFICATIONS (10K ECL)
VEE Supply Voltage .............................................. -5.20 ± 0.25 VDC
Supply Current, IEE , DECL .......................... 60 mA typ., 75 mA max.
Supply Current, IEE , FECL .......................... 40 mA typ., 65 mA max.
Supply Current, IEE , MECL ....................... 85 mA typ., 105 mA max.
Logic “1” Input:
VIH ................................................ -0.98 V min.
IIH .................................................. 265 µA max.
Logic “0” Input:
VIL ................................................. -1.63 V max.
IIL .................................................. 0.5 mA max.
VOH Logic “1” Voltage Out .............................................. -0.96 V min.
VOL Logic “0” Voltage Out .............................................. -1.65V max.
TRO Output Rise Time .................................................. < 3.00 ns typ.
Input Pulse Width, PWI (DECL,FECL) ......... 40% of total delay, min.
Input Pulse Width, PWI (MECL) ................ 100% of total delay, min.
Operating Temperature Range ................................... -30 O to +85OC
Storage Temperature Range ..................................... -65O to +150OC
TEST CONDITIONS
(Measurements made at 25OC)
VEE Supply Voltage ................................................................. -5.20VDC
Input Pulse Voltage ....................................................... -.80V to -1.80V
Input Pulse Rise Time ......................................................... 3.00ns max.
Input Pulse Period ....................................................... 4.0 x Total Delay
Input Pulse Duty Cycle .................................................................... 50%
Outputs terminated through 100 Ω to -2.00 Vdc.
Dimensions in Inches (mm) -- Unused Leads Removed Per Schematic
DECL Style Schematic
Vcc Tap1 Tap3 Tap5
16
15
1
Vcc
13
3
4
Tap2 Tap4
5
8
IN
Vee
FECL Style Schematic
Vcc
OUT
OUT
16
15
9
1
4
8
Vcc
IN
Vee
.400
(10.16)
MAX.
.810
(20.57)
MAX.
14
MECL Style Schematic
Vcc OUT1 OUT2 OUT3
16
.260 .300
(6.60) (7.62)
TYP. MAX.
.100
(2.54)
TYP.
.020
(0.51)
TYP.
14
13
.010
(0.25)
TYP.
.120
(3.05)
MIN.
.050
(1.27)
TYP.
15
.300
(7.62)
1
5
6
Vcc
IN 1
IN 2
7
8
IN 3 Vee
Also Available in 10KH ECL Versions: DECLH, FECLH & MECLH Series
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[email protected]
26
TEL: (714) 898-0960
FAX: (714) 896-0971
DECL_FM 2001-01
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