PHILIPS HEF4070BT Quadruple exclusive-or gate Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4070B
gates
Quadruple exclusive-OR gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4070B
gates
Quadruple exclusive-OR gate
DESCRIPTION
The HEF4070B provides the positive quadruple
exclusive-OR function. The outputs are fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.
Fig.2 Pinning diagram.
HEF4070BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4070BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4070BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
TRUTH TABLE
APPLICATION INFORMATION
Some examples of applications for the HEF4070B are:
I1
I2
O1
• Logical comparators
L
L
L
• Parity checkers and generators
H
L
H
L
H
H
H
H
L
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
January 1995
2
Philips Semiconductors
Product specification
HEF4070B
gates
Quadruple exclusive-OR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
In → On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Output transition times
HIGH to LOW
5
10
tTHL
15
5
LOW to HIGH
10
tTLH
15
VDD
V
Dynamic power
5
85
175
ns
58 ns
+
(0,55 ns/pF) CL
35
75
ns
24 ns
+
(0,23 ns/pF) CL
30
55
ns
21 ns
+
(0,16 ns/pF) CL
75
150
ns
48 ns
+
(0,55 ns/pF) CL
30
65
ns
19 ns
+
(0,23 ns/pF) CL
25
50
ns
17 ns
+
(0,16 ns/pF) CL
60
120
ns
10 ns
+
(1,0 ns/pF) CL
30
60
ns
9 ns
+
(0,42 ns/pF) CL
20
40
ns
6 ns
+
(0,28 ns/pF) CL
60
120
ns
10 ns
+
(1,0 ns/pF) CL
30
60
ns
9 ns
+
(0,42 ns/pF) CL
20
40
ns
6 ns
+
(0,28 ns/pF) CL
TYPICAL FORMULA FOR P (µW)
1100 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
dissipation per
10
4900 fi + ∑ (foCL) ×
package (P)
15
14 400 fi + ∑ (foCL) ×
VDD2
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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