Micrel MICRF500 700mhz to 1.1ghz radiowire rf transceiver Datasheet

MICRF500
Micrel
MICRF500
700MHz to 1.1GHz RadioWire™ RF Transceiver
Final
General Description
The MICRF500 is a single chip UHF transceiver designed for
spread spectrum communication (FHSS) intended for ISM
(Industrial, Scientific and Medical) and SRD (Short Range
Device) frequency bands from 700MHz to 1100MHz with
FSK data rates up to 128k baud.
The transmitter consists of a PLL frequency synthesizer and
a power amplifier. The frequency synthesizer consists of a
voltage-controlled oscillator (VCO), a crystal oscillator, dualmodulus prescaler, programmable frequency dividers and a
phase-detector. The loop filter is external for flexibility and
can be a simple passive circuit. The VCO is a Colpitts
oscillator which requires an external resonator and varactor.
FSK modulation can be applied externally to the VCO. The
synthesizer has two different N, M and A frequency dividers.
FSK modulation can also be implemented by switching
between these dividers (max. 2400bps). The lengths of the N
and M and A registers are 12, 10 and 6 bits respectively. For
all types of FSK modulation, data is entered at the DATAIXO
pin (see application circuit). The output power of the power
amplifier can be programmed to eight levels. A lock detect
circuit detects when the PLL is in lock.
In receive mode the PLL synthesizer generates the local
oscillator (LO) signal. The N, M and A values that give the LO
frequency are stored in the N0, M0 and A0 registers. The
receiver is a zero intermediate frequency (IF) type in order to
make channel filtering possible with low-power integrated
low-pass filters. The receiver consists of a low-noise amplifier
(LNA) that drives a quadrature mixer pair. The mixer outputs
feed two identical signal channels in phase quadrature. Each
channel includes a preamplifier, a third order Sallen-Key RC
low pass filter that protects the following gyrator filter from
strong adjacent channel signals and finally, a limiter. The
main channel filter is a gyrator capacitor implementation of a
seven-pole elliptic low pass filter. The elliptic filter minimizes
the total capacitance required for a given selectivity and
dynamic range. The cut-off frequency of the Sallen-Key RC
filter can be programmed to four different frequencies: 10kHz,
30kHz, 60kHz and 200kHz. An external resistor adjusts the
cut-off frequency of the gyrator filter. The demodulator demodulates the I and Q channel outputs and produces a digital
data output. It detects the relative phase of the I and the Q
channel signal. If the I channel signal lags the Q channel, the
FSK tone frequency lies above the LO frequency (data ‘1’). If
the I channel leads the Q channel, the FSK tone lies below the
LO frequency (data ‘0’). The output of the receiver is available
on the DATAIXO pin. A RSSI (Receive Signal Strength
Indicator) circuit indicates the received signal level.
RadioWire™
A two pin serial interface is used to program the circuit.
External components are necessary for RF input and output
impedance matching and decoupling of power. Other external components are the VCO resonator circuit with varactor,
crystal, feedback capacitors and components for FSK modulation with the VCO, loop filter, bias resistors for the power
amplifier and gyrator filters. A T/R switch can be implemented
with 2-pin diodes. This gives maximum input sensitivity and
transmit output power.
Features
•
•
•
•
•
Frequency range: 700MHz to 1100MHz
Modulation: FSK
RF output power: 10dBm
Sensitivity (19.2k bauds, BER=10-3): –104dBm
Maximum data rate: 128k bauds
Applications
•
•
•
•
•
•
•
Telemetry
Remote metering
Wireless controller
Wireless data repeaters
Remote control systems
Wireless modem
Wireless security system
Ordering Information
Part Number
MICRF500BLQ
Ambient Temp. Range
Package
–40°C to +85°C
44-Lead LQFP
RadioWire is a trademark of Micrel, Inc.
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
March 2003
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MICRF500
MICRF500
Micrel
VB_IP
QCHC
ICHC
IFQINN
IFQINP
MIXQOUTN
MIXQOUTP
IFIINN
IFIINP
MIXIOUTN
MIXIOUTP
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
MIXERVDD
MIXERGND
LNA_C
RFGND2
RFIN
RFVDD
RFGND
RFOUT
PABIAS
PA_C
DIGGND
XOSCIN
XOSCOUT
LD_C
LOCKDET
RSSI
PDEXT
DATAC
DATAIXO
CLKIN
REGIN
DIGVDD
IFGND
IFVDD
ICHOUT
QCHOUT
OSCVDD
OSCIN
OSCGND
GND
CMPOUT
CMPR
MOD
44-Pin LQFP (BLQ)
Pin Description
Pin Number
Pin Name
1
IFGND
Pin Function
IF Ground
2
IFVDD
3
ICHOUT
I-Channel Output
4
QCHOUT
Q-Channel Output
5
OSCVDD
Colpitts Oscillator Power
6
OSCIN
7
OSCGND
8
GND
9
CMPOUT
10
CMPR
Charge Pump Resistor Input
11
MOD
Output for VCO Modulation
12
XOSCIN
13
XOSCOUT
14
LD_C
15
LOCKDET
16
RSSI
17
PDEXT
Power Down Input (0=Power Down)
18
DATAC
Data Filter Capacitor
19
DATAIXO
20
CLKIN
Clock Input for Programming
21
REGIN
Data Input for Programming
22
DIGVDD
Digital Circuitry Power
23
DIGGND
Digital Circuitry Ground
MICRF500
IF Power
Colpitts Oscillator Input
Colpitts Oscillator and Substrate Ground
Substrate Ground
Charge Pump Output
Crystal Oscillator Input
Crystal Oscillator Output
External Capacitor for Lock Detector
Lock Detector Output
Received Signal Strength Indicator Output
Data Input/Output
2
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MICRF500
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Pin Description, cont’t
Pin Number
Pin Name
24
PA_C
25
PABIAS
External Bias Resistor for Power Amplifier
26
RFOUT
Power Amplifier Output
27
RFGND
LNA, PA and Substrate Ground
28
RFVDD
LNA and PA Power
29
RFIN
30
RFGND2
31
LNA_C
32
MIXERGND
Mixer Ground
33
MIXERVDD
Mixer Power
34
MIXIOUTP
I-Channel Mixer Positive Output
35
MIXIOUTN
I-Channel Mixer Negative Output
36
IFIINP
I-Channel IF Amplifier Positive Input
37
IFIINN
I-Channel IF Amplifier Negative Input
38
MIXQOUTP
Q-Channel Mixer Positive Output
39
MIXQOUTN
Q-Channel Mixer Negative Output
40
IFQINP
Q-Channel IF Amplifier Positive Input
41
IFQINN
Q-Channel IF Amplifier Negative Input
42
ICHC
I-Channel Amplifier Capacitor
43
QCHC
Q-Channel Amplifier Capacitor
44
VB_IP
Gyrator Filter Resistor
March 2003
Pin Function
Capacitor for Slow Ramp Up/Down of PA
Low Noise RF Amplifier (LNA) Input
LNA First Stage Ground
External LNA Stabilizing Capacitor
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MICRF500
MICRF500
Micrel
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Maximum Supply Voltage (VDD) ................................... +7V
Maximum NPN Reverse Base-Emitter Voltage .......... +2.5V
Storage Temperature Range (TS) ............ –55°C to +150°C
ESD Rating, Note 3 .................................................... 500V
Supply Voltage (VIN) ................................... +2.5V to +3.4V
Ambient Temperature (TA) ......................... –40°C to +85°C
Package Thermal Resistance
TQFP(θJA)-Multilayer board ............................. 46.3°C/W
Electrical Characteristics
FREF = 850MHz, VDD = 2.5 to 3.4V, TA = 25°C, unless otherwise specified.
Parameter
Condition
Min
Typ
Max
Units
700
850
1100
MHz
<1
2
µA
Overall
Operating Frequency
Power Down Current
Logic High Input, VIH
70%
VDD
Logic Low Input, VIL
30%
DATAIXO, Logic High Output (VOH)
IOH = –500µA
DATAIXO, Logic Low Output (VOL)
IOL = 500µA
LockDet, Logic High Output (VOH)
IOH = –100µA
LockDet, Logic Low Output (VOL)
IOL = 100µA
VDD-0.3
V
0.3
VDD-0.25
25
Data Setup to Clock (rising edge)
25
V
V
Clock/Data Frequency
Clock/Data Duty-Cycle
VDD
0.25
V
10
MHz
75
%
ns
VCO and PLL Section
Prescaler Divide Ratio
64/65
Reference Frequency
40
MHz
PLL Lock Time (int. modulation)
4kHz loop filter bandwidth
1
ms
PLL Lock Time (ext. modulation)
1kHz loop filter bandwidth
4
ms
Rx – (Tx with PA on) Switch Time
1kHz loop filter bandwidth
2.5
ms
±95/±380 ±125/±500 ±155/±620
µA
10
dBm
Charge Pump Current
Transmit Section
fOUT = 850MHz
Output Power
RLOAD = 50Ω, VDD = 3.0V
Transmit Data Rate (ext. modulation)
Note 4
19.2
Transmit Data Rate (int. modulation)
Note 5
Frequency Deviation to
Modulation Rate Ratio
unfiltered FSK
Current Consumption
Transmit Mode
10 dBm, RLOAD = 50Ω
MICRF500
1.0
kbauds
2.4
kbauds
1.5
50
4
128
mA
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MICRF500
Micrel
Parameter
Condition
Receive Section
fIN = 850MHz
Receiver Sensitivity (Note 6)
BER=10-3
Min
Typ
Max
Units
–1046
dBm
Input 1dB Compression Level
–34
dBm
Input IP3
–24
dBm
22.5-j28.5
W
60
dB
PIN = –100dBm
PIN = –30dBm
0.7
2.1
V
V
25kHz channel spacing
100kHz channel spacing
200kHz channel spacing
700kHz channel spacing
26
37
45
48
dB
dB
dB
dB
RC filter:
RC filter:
RC filter:
RC filter:
66
61
59
53
dB
Input Impedance
RSSI Dynamic Range
RSSI Output Voltage
Adjacent Channel Rejection:
fC = 10kHz
fC = 30kHz
fC = 60kHz
fC = 200kHz
Blocking Immunity (1MHz)
fC = 10kHz
fC = 30kHz
fC = 60kHz
fC = 200kHz
Maximum Receiver Bandwidth
175
Receiver Settling Time
Current Consumption
Receive Mode
dB
dB
gyrator filter fC = 60kHz
Current Consumption XCO
kHz
1
ms
12
mA
300
µA
Note 1.
Exceeding the absolute maximum rating may damage the device.
Note 2.
The device is not guaranteed to function outside its operating rating.
Note 3.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
Note 4.
Modulation is applied to the VCO and therefore the modulation cannot have any DC component. Some kind of coding is needed to ensure that
the modulation is DC free, e.g., Manchester code or block code. With Manchester code the bitrate is half the baudrate, but with 3B4B block
code the bitrate is 3/4 of the baudrate.
Note 5:
Bitrate is the same as the baudrate.
Note 6:
Measured at 19.2k bauds and frequency deviation ±25kHz (external modulation), jitter of received data: < 45%.
Output Power
vs. Current @ 25°C
15
POUT (dBm)
10
5
0
-5
-10
10 15 20 25 30 35 40 45 50
ITOT (mA)
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MICRF500
MICRF500
Micrel
Functional Diagram
33
32
31
30
34
29
28
27
26
25
24
23
22
LNA
PA
C
o
n
t
r
Logic
o
l
35
90°
Prescaler
64/65
36
37
Control
A1/A0
38
A-counter
N1/N0
39
19
18
17
16
Gyrator
Filters
41
20
N-counter
R
S
S
I
RC
Filters
40
I
n
t
e
r
f
a
c
e
21
M-counter
15
M1/M0
42
LD
14
Phase
Detector
43
13
VCO
Charge
Pump
Demod
XCO
44
12
1
2
3
4
5
6
7
8
9
10
11
Figure 1. Transceiver Internal Blocks
MICRF500
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March 2003
MICRF500
Micrel
The varactor SMV1215-011 is a single variable capacitance
diode manufactured by Skyworks Solutions (formerly Alpha
Industries). The pin diode SMP1320 is also manufactured by
Skyworks Solutions.
Typical Application
Figure 2 shows an example of a transceiver with modulation
applied to the VCO. The VCO and matching components are
optimized for 915MHz, 120kbps data rate. The inductors and
trimming capacitors must have a good high frequency performance.
C7
4.7n
44
R8
39k
R13
270k
C16
39n
R10
16k
OSCVDD
6
OSCIN
28
RFGND
GND
RFOUT
CMPOUT
PABIAS
27
10
25
24
MOD
C29
100p
C4
47p
C36
1.5p
C25
470p
C35
47p
REGIN
20
21
23
DIGVDD
19
CLKIN
L3
8.7n
C37
4p
ANT
C33
47p
D3
SMP1320-079
L4
5.6n
22
C31
4.7p
C32
6.8p
R16
2.2k
L5
10n
R3
39Ω
VDD
VDD
REGIN
CLKIN
Lock
Det
C20
4p to 10p
18
DATAIX0
C23
1n
17
DATAC
16
DATAIX0
C21
100p
15
PDEXT
C22
7p
14
PDEXT
13
C28
18p
R14
2.2k
ant-switch
D2
SMP1320-079
DIGGND
RSSI
12
L2
5.1n
26
PA_C
LD_C
10MHz
29
OSCGND
XOSCIN
R12
6.8k
C17
68p
RFIN
RFVDD
CMPR
R11
100k
C26
10n
30
MICRF500
44-pin LQFP
C30
47p
31
RFGND2
9
C34
10n
C18
100n
LNA_C
5
11
C19
470p
32
ICHOUT
LOCKDET
R9
16k
MIXER
GND
XOSCOUT
C15
3.3n
IFVDD
QCHOUT
8
C5
47p
33
IFGND
R4
10Ω
R5
62Ω
34
MIXIOUTP
D1
SMV1215
35
MIXER
VDD
4
7
36
MIXIOUTN
12n
37
VDD
VDD
IFIINP
C13
4.7p
L1
38
IFIINN
C38
39
MIXQOUTP
R7
20k
40
MIXQOUTN
QchOut
3
C11
1n
IFQINP
IchOut
41
IFQINN
R2
0Ω
ICHC
2
42
QCHC
C1
47p
VDD
43
VB_IP
R1
30Ω
1
C12
1n
C10
1n
C9
1n
R6
1k
VDD
C8
4.7n
C6
47p
VDD
C24
1n
RSSI
Figure 2. Application Circuit - Optimized for 915MHz. 120kbps
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MICRF500
MICRF500
Micrel
List of components
Component
Values
Component
Values
Component
Values
R1
30Ω
C8
4.7nF
C30
47pF
R2
0Ω
C9
1nF
C31
5.6pF
R3
39Ω
C10
1nF
C32
6.8pF
R4
10Ω
C11
1nF
C33
47pF
R5
62Ω
C12
1nF
C34
10µF
R6
1kΩ
C13
4.7pF
C35
47pF
R7
20kΩ
C15
3.3nF
C36
1.5pF
R8
39kΩ
C16
39nF
C37
4pF
R9
16kΩ
C17
68pF
C38
(np)
R10
16kΩ
C18
100nF
L1
12nH
R11
100kΩ
C19
470pF
L2
5.1nH
R12
6.8kΩ
C20
4pF-100pF
L3
8.7nH
R13
270kΩ
C21
100pF
L4
5.6nH
R14
2.2kΩ
C22
7pF
L5
10nH
R16
2.2kΩ
C23
1nF
D1
SMV1215-011
C1
47pF
C24
1nF
D2
SMP1320-079
C4
47pF
C25
470pF
D3
SMP1320-079
C5
47pF
C26
10nF
crystal
10MHz
C6
47pF
C28
18pF
C7
4.7nF
C29
100pF
MICRF500
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MICRF500
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Applications Information
DIFVDD
VCO and PLL Section
The frequency synthesizer consists of a VCO, crystal oscillator, dual-modulus prescaler, programmable frequency dividers, phase-detector, charge pump, lock detector and an
external loop filter. The dual-modulus prescaler divides the
VCO-frequency by 64/65. This mode is controlled by the Adivider. There are two sets of M, N and A-frequency dividers.
Using both sets in transmit mode, FSK can be implemented
by switching between those two sets. The phase-detector is
a frequency/phase detector with back slash pulses to minimize phase noise. The VCO, crystal oscillator, charge pump,
lock detector and the loop filter will be described in detail
below.
Voltage Controlled Oscillator (VCO)
C36
1n
C20
2-6p
10MHz
C38
L1
12nH
4.7p
The crystal oscillator is tuned by varying the trimming capacitor C20. The drift of the RF frequency is the same as the drift
of crystal frequency when measured in ppm. The total difference in ppm, ∆f(ppm), between the tuned RF frequency and
the drifted frequency is given by:
∆f(ppm) = ST × ∆T + n × ∆t
where:
• ST is the total temperature coefficient of the oscillator
frequency (due to crystal and components) in ppm°C.
• ∆T is the change in temperature from room
temperature, at which the crystal was tuned.
• n is the ageing in ppm/year.
• ∆t is the time (in years) elapsed since the transceiver
was last tuned.
The demodulator will not be able to decode data when
∆f(Hz) = ∆f(ppm) × fRF is larger than the FSK frequency
deviation. For small frequency deviations, the crystal should
be pre-aged, and should have a small temperature coefficient. The circuit has been tested with a 10MHz crystal, but
other crystal frequencies can be used as well.
Pin 6
OSCOUT
D1
SMV1215
Pin 7
Figure 3. VCO
The circuit schematic of the VCO with external components
is shown in Figure 3. The VCO is basically a Colpitts oscillator. The oscillator has an external resonator and varactor.
The resonator consists of inductor L1 and the series connection of capacitor C13, the internal capacitance and the
capacitance of the varactor. The capacitance of the varactor
(D1) decreases as the input voltage increases. The VCO
frequency will therefore increase as the input voltage increases. The VCO has a positive gain (MHz/Volt). If necessary a parallel capacitor can be added next to D1 to bring the
VCO tuning voltage to its middle range or VDD/2, which is
measured at Pin 9 - CMPOUT.
If the value of capacitor C13 becomes too small the amplitude
of the VCO signal decreases, which leads to lower output
power.
The layout of the VCO is very critical. The external components should be placed as close to the input pin (Pin 6) as
possible. The anode of D1 must be placed next to Pins 7 and
8 in the PCB layout. Ground vias should be next to component
pads.
Crystal Oscillator
The crystal oscillator is the reference for the RF output
frequency as well as for the LO frequency in the receiver. The
crystal oscillator is a very critical block since very good phase
and frequency stability is required. The schematic of the
crystal oscillator with external components for 10MHz is
shown in Figure 4. These components are optimized for a
crystal with 15pF load capacitance.
March 2003
XOSCOUT
Figure 4. Crystal Oscillator
R7
20k
R8
39k
Pin 13
DIGGND
Pin 5
loopfilter_output
C22
5.6p
C21
47p
VDD
C13
Pin 12
Prestart of XCO
The start-up time of a crystal oscillator is typically some
milliseconds. Therefore, to save current consumption, the
MICRF500 circuit has been designed so that the XCO is
turned on before any other circuit block. During start-up the
XCO amplitude will eventually reach a sufficient level to
trigger the M-counter. After counting two M-counter output
pulses the rest of the circuit will be turned on. The current
consumption during the prestart period is approximately
300µA.
Lock Detector
The MICRF500 circuit has a lock detector feature that indicates whether the PLL is in lock or not. A logic high on Pin 15
(LOCKDET) means that the PLL is in lock.
The phase detector output is converted into a voltage that is
filtered by the external capacitor C23, connected to Pin 14,
LDC. The resulting DC voltage is compared to a reference
window set by bits Ref0 – Ref5. The reference window can be
stepped up/down linearly between 0V, Ref0 – Ref5 = 1, and
Ref0 – Ref5 = 0, which gives the highest value (DC voltage)
of the reference window. The size of the window can either be
equal to two (Ref6 = 1) reference steps or four reference
steps (Ref6 = 0).
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MICRF500
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Micrel
The bit setting that corresponds to lock can vary, depending
on temperature, loop filter and type of varactor. Therefore, the
lock detect circuit needs to be calibrated regularly by a
software routine that finds the correct bit setting, by running
through all combinations of bits Ref0 – Ref5. Depending on
the size of the reference window, there will be several bit
combinations that show lock. For instance, with a large
reference window, as much as five bit combinations can
make the lock detector show lock. To have the maximum
robustness to noise, the third of the bit settings should be
chosen.
Charge Pump
The charge pump can be programmed to four different modes
with two currents, ±125µA and ±500µA. Bit 70 and 71 in the
control word (cpmp1 and cpmp0) controls the operation. The
four modes are:
1. cpmp1 = 0 Current is constant ±125µA. Used in
cpmp0 = 0 applications where short PLL lock
time is not important.
2. cpmp1 = 0 Current is constant ±500µA. Used in
cpmp0 = 1 applications where a short PLL lock
time is important, e.g., internal modulation. See “Modulation Inside PLL”
section.
3. cpmp1 = 1 Current is ±500µA when PLL is out of
cpmp0 = 0 lock and ±125µA when it is in lock.
Controlled by LOCKDET (Pin 15). Lock
time is halved.
See “Modulation Outside PLL” section.
4. cpmp1 = 1 Same as above in Tx. In Rx the current
cpmp0 = 1 is ±500µA. Used when using dual-loop
filters. See “Modulation Outside PLL
Dual-Loop Filters” section.
Tuning of VCO and XCO
There are two circuit blocks that may need tuning, the VCO
and the crystal oscillator.
FSK Modulation
The circuit has two sets of frequency dividers A0, N0, M0 and
A1, N1, M1. The frequency dividers are programmed via the
control word. A0, N0, M0 are to be programmed with the
receive frequency and are used in receive mode. There are
three ways of implementing FSK:
• FSK modulation can be applied to the VCO. This
way of implementing FSK modulation is explained more in detail in the next section. The
values corresponding to the transmit frequency
should be programmed in dividers A1, N1 and
M1. Pin DATAIXO must be kept in tri-state from
the time Tx-mode is entered until one starts
sending data.
• FSK modulation by switching between the two
sets of A, N and M dividers. A, N and M values
corresponding to the receive frequency and both
transmit frequencies have to be found. In
transmit the values corresponding to data ‘0’
should be programmed in dividers A0, N0 and
M0, and the values corresponding to data ‘1’
should be programmed in dividers A1, N1 and
M1.
• FSK modulation by adding/subtracting 1 to
divider A1. The frequency deviation will be equal
to the comparison frequency. The values
corresponding to the transmit frequency should
be programmed in dividers A1, N1 and M1.
For all types of FSK modulation, data is entered at the
DATAIXO pin.
Loop Filter
The design of the loop filter is of great importance for
optimizing parameters like modulation rate, PLL lock time,
bandwidth and phase noise. Low bitrates will allow modulation inside the PLL, which means the loop will lock on different
frequency for 1s and 0s. This can be implemented by switching the internal dividers (M, N and A).
Higher modulation rates (above 2400bps) imply implementation of modulation outside the PLL. This can be implemented
by applying the modulation directly to the VCO.
Loop filter values can be found using an appropriate software
program.
VCO Tuning
When the VCO voltage is not at its mid-point, a capacitor may
be added in parallel with D1or by small increments changes
in the L1 or C13 values.
This is particularly important when using VCO modulation.
The gain curve of the VCO (MHz/Volt) is not linear and the
gain will therefore vary with loop voltage. This means that the
FSK frequency deviation also varies with loop voltage.
When using internal modulation, tuning the VCO can be
omitted as long as the VCO gain is large enough to allow the
PLL to handle variations in process parameters and temperature without going out of lock.
Modulation Inside PLL
A fast PLL requires a loop filter with relatively high bandwidth.
If a second order loop filter is chosen, it may not give
adequate attenuation of the comparison frequency. Therefore in the following example a third order loop filter is chosen.
Example 1:
868MHz
Radio frequency
fRF
Comparison frequency
fC
100kHz
Loop bandwidth
BW
3.8kHz
VCO gain
Ko
30MHz/V
Phase comparator gain
Kd
500µA/rad
Phase margin
j
62°
Breakthrough suppression A
20dB
XCO Tuning
Tune the trimming capacitor in the crystal oscillator to the
precise desired transmit frequency. It is not possible to tune
the crystal oscillator over a large frequency range. N, M and
A values must therefore be chosen to give a RF frequency
very close to the desired frequency. Because of the small
tuning range the VCO will not go out of lock when tuning the
crystal oscillator.
MICRF500
10
March 2003
MICRF500
Micrel
The component values will be:
With this loop filter, internal modulation up to 2400bps is
possible. The PLL lock time from power-down to Rx will be
approximately 1ms.
through the Mod pin (Pin 11) which is a current output. The pin
sources a current of 50µA when Logic 1 is entered at the
DATAIXO and drains the current for Logic 0. The capacitance
of C17 will set the order of filtering of the baseband signal. A
large capacitance will give a slow ramp-up and therefore a
high order of filtering of the baseband signal, while a small
capacitance gives a fast ramp-up, which in turn also gives a
broader frequency spectrum. Resistors R11 and R12 set the
frequency deviation. If C18 is large compared to C17, the
frequency deviation will be large. R13 should be large to
avoid influencing the loop filter. Pin DATAIXO must be kept
in tri-state from the time Tx-mode is entered until one starts
sending data.
Modulation Outside PLL (Closed Loop)
Modulation Outside PLL, Dual-Loop Filters
When modulation is applied outside the PLL, it means that the
PLL should not track the changes in the loop due to the
modulation signal. A loop filter with relatively low bandwidth
is therefore necessary. The exact bandwidth will depend on
the actual modulation rate. Because the loop bandwidth will
be significantly lower than the comparison frequency, a
second order loop filter will normally give adequate attenuation of the comparison frequency. If not, a third order loop filter
may give the extra attenuation needed.
Example 2:
868MHz
Radio frequency
fRF
Comparison frequency
fC
140kHz
Loop bandwidth
BW
900Hz
VCO gain
Ko
30MHz/V
Phase comparator gain
Kd
125µA/rad
Phase margin
j
61°
The component values will be:
Modulation outside the PLL requires a loop filter with a
relatively low bandwidth compared to the modulation rate.
This results in a relatively long loop lock time. In applications
where modulation is applied to the VCO, but at the same time
a short start-up time from power down to receive mode is
needed, dual-loop filters can be implemented. Figure 7
shows how to implement dual-loop filters.
R101
IN
33k
OUT
C116
22n
C115
1n
C101
100p
R109
10k
Figure 5. Third Order Loop Filter
IN
CMPOUT
Pin10
68n
4.7n
R9
10k
C116
C115
C103
1n
22n
100p
R8 89k
towards_VCO
R109
10k
DFC
Figure 7. Dual-Loop Filters
The loop filter used in transmit mode is made up of C15, C16,
R9 and R10. The fast lock feature is also included (internal
NMOS controlled by FLC, Fast Lock Control). This filter is
automatically switched in/out by an internal NMOS at Pin 4,
QchOut, which is controlled by DFC (Dual Filter Control). Bits
OutS2, OutS1, OutS0 must be set to 110. When QchOut is
used to switch the Tx loop filter to ground, neither QchOut nor
IchOut can be used as test pins to look at the different receiver
signals. The receive mode loop filter comprises C115, C116,
R109, R101 and C101.
CmpR
R10
10k
Figure 6. Second Order Loop Filter
Data rates above approximately 19200baud (including
Manchester coding) can be used with this loop filter without
significant tracking of the modulating signal. PLL lock time will
be approximately 4ms.
If a faster PLL lock time is wanted, the charge pump can be
made to deliver a current of 500µA per unit phase error, while
an open drain NMOS on chip (Pin 10, CmpR) switches in a
second damping resistor (R10) to ground as shown in Figure
6. Once locked on the correct frequency, the PLL automatically returns to standard low noise operation (charge pump
current: 125µA/rad). If correct settings have been made in the
control word (cpmp1 = 1, cpmp0 = 0), the fast locking feature
is activated and will reduce PLL lock time by a factor of two
without affecting the phase margin in the loop.
Components C17, C18 C19, R11, R12 and R13 (see application circuit) are necessary if FSK modulation is applied to the
VCO. Data entered at the DATAIXO pin will then be fed
March 2003
C15
Pin4
C16
68n
R9
10k
C16
R10
10k
FLC
OUT
C15
4.7n
R102 33k
Pin9
Modulation Outside PLL (Open Loop)
In this mode the charge pump output is tri-stated. The loop is
open and will therefore not track the modulation. This means
that the loop filter can have a relatively high bandwidth, which
give short switching times. However, the loop voltage will
decrease with time due to current leakage. The transmit time
will therefore be limited and is dependent on the bandwidth of
the loop filter. High bandwidth gives low capacitor values and
the loop voltage will decrease faster, which gives a shorter
transmit time.
The loop is closed until the PLL is locked on the desired
frequency and the power amplifier is turned on. The loop
immediately opens when the modulation starts. The loop will
not track the modulation, but the modulation still needs to be
DC free due to the AC coupling in the modulation network.
11
MICRF500
MICRF500
Micrel
Transmit
Power Amplifier (PA)
The power amplifier is biased in class AB. The last stage has
an open collector, and an external load inductor (L2) is
therefore necessary. The DC current in the amplifier is
adjusted with an external bias resistor (R14). A good starting
point when designing the PA is a 1.5kΩ bias resistor which
gives a bias current of approximately 50µA. This will give a
bias current in the last stage of about 15mA.
The impedance matching circuit will depend on the type of
antenna used, but should be designed for maximum output
power. For maximum output power the load seen by the PA
must be resistive and should be about 100Ω. The output
power is programmable in eight steps, with approximately
3dB between each step. This is controlled by bits Pa2 - Pa0.
To prevent spurious components from being transmitted the
PA should be switched on/off slowly, by allowing the bias
current to ramp up/down at a rate determined by the external
capacitor C25 connected to Pin 24. The ramp up/down
current is typically 1.1µA, which makes the on/off rate for a
3.0V power supply 2.6µs/pF. Turning the PA on/off affects the
PLL. Therefore the on/off rate must be adjusted to the PLL
bandwidth.
PA Buffer
A buffer amplifier is connected between the VCO and the PA
to ensure that the input signal of the PA has sufficient
amplitude to achieve the desired output power. This buffer
can be bypassed by setting the bit Gc to 0.
Figure 8. Input Impedance
Sallen-Key Filter and Preamplifier
Each channel includes a preamplifier and a prefilter, which is
a three-pole elliptic Sallen-Key low pass filter with 20dB
stopband attenuation. It protects the following gyrator filter
from strong adjacent channel signals. The preamplifier has a
gain of 20dB when bit Gc = 0 and 30dB when bit Gc = 1. The
output voltage swing is about 200mVPP for the 30dB gain
setting and 1VPP for the 20dB gain setting.
The third order Sallen-Key low pass filter is programmable to
four different cut-off frequencies according to the table below:
Receive
Front End (LNA and Mixers)
A low noise amplifier in RF receivers is used to boost the
incoming signal prior to the frequency conversion process.
This is important in order to prevent mixer noise from dominating the overall front end noise performance. The LNA is a
two-stage amplifier and has a nominal gain of 23dB at
900MHz. The LNA has a dc feedback loop, which provides
bias for the LNA. The external capacitor C26 decouples and
stabilizes the overall dc feedback loop, which has a large low
frequency loop gain. Figure 8 shows the input impedance of
the LNA. Input matching is very important to get high receive
sensitivity.
The LNA can be bypassed by setting bit ByLNA to ‘1’. This is
useful for very strong signal levels.
The RSSI signal can be used to drive a microcontroller in a
way when a strong RF income signal is present the LNA can
be bypassed. This will increase the dynamic range by approximately 25dB.
The mixers have a gain of about 12dB at 900MHz. The
differential outputs of the mixers are available at Pins 34, 35
and at Pins 38, 39. The output impedance of each mixer is
about 15kΩ.
MICRF500
Fc1
Fc0
Cut-Off Frequency
(kHz)
Recommended
Channel Spacing
0
0
10 ±2.5
25kHz
0
1
30 ±7.5
100kHz
1
0
60 ±15
200kHz
1
1
200 ±50
700kHz
For the 10kHz cut-off frequency the first pole must be generated externally by connecting a 820pF capacitor between the
outputs of each mixer. For the 30kHz cut-off frequency a
68pF capacitor is needed between the outputs.
As the cut-off frequency of the gyrator filter can be set by
varying an external resistor, the optimum channel spacing
will depend on the cut-off frequencies of the Sallen-Key filter.
The table above shows the recommended channel spacing
depending on the different bit settings.
Gyrator Filter
The main channel filter is a gyrator capacitor implementation
of a seven-pole elliptic low pass filter. The elliptic filter
minimizes the total capacitance required for a given selectivity and dynamic range. An external resistor can adjust the cutoff frequency of the gyrator filter. The following table shows
how the cut-off frequency varies with bias resistor:
12
March 2003
MICRF500
Micrel
30
30
14
47
8
The gyrator filter cut-off frequency should be chosen to be
approximately the same as the cut-off frequency of the
Sallen-Key filter. The maximum cut-off frequency of the
gyrator filter is 175kHz.
Cut-Off Frequency Setting
The cut-off frequency must be high enough to pass the
received signal (frequency deviation + modulation). The
minimum cut-off frequency is given by:
fC(min) = fDEV + Baudrate/2
For a frequency deviation of fDEV = 30kHz and a baudrate of
20k baud, the minimum cut-off frequency is 40kHz. Bit setting
Fc1 = 1 and Fc0 = 0, which gives a cut-off of (60 ±15) kHz,
would be the best choice. The gyrator filter bias resistor
should therefore be 7.5kΩ or 8.2 kΩ, to set the gyrator filter
cut-off frequency to approximately 60kHz.
The crystal tolerance must also be taken into account when
selecting the receiver bandwidth. If the crystal has a temperature tolerance of say ±10ppm over the total temperature
range, the incoming RF signal and the LO signal can theoretically be 20ppm away from each other.
The frequency deviation must always be larger than the
maximum frequency drift for the demodulator to be able to
demodulate the signal. The minimum frequency deviation
(fDEVmin) is equal to the baudrate, according to the specification on page 2. This means that the frequency deviation
has to be at least equal to the baudrate plus the maximum
frequency drift.
The frequency deviation may therefore vary from the minimum frequency deviation to the minimum frequency deviation plus two times the maximum frequency drift. The minimum cut-off frequency when crystal tolerances are considered is therefore given by:
fCmin = ∆f × 2 fDEVmin + Baudrate/2
where ∆f is the maximum frequency drift between the LO
signal and the incoming RF signal due to crystal tolerances.
A frequency drift of 20ppm is 8680Hz at 434MHz. The
frequency deviation must be higher than 28.68kHz for a
baudrate of 20k baud. The frequency deviation may then vary
from 20kHz, when the RF signal is 20ppm lower than the LO
signal; to 37.36kHz when the RF signal is 20ppm higher than
the LO signal. The minimum cut-off frequency is tûeref•re
47.36kHz.
March 2003
2.2
2
VOUT (V)
1.8
1.6
1.4
1.2
1
0.8
-110
0.6
-20
15
-30
55
-40
8.2
-50
70
-60
6.8
-70
175
-80
2.2
Limiter
The limiter serves as a zero crossing detector, thus removing
amplitude variations in the IF signal, while retaining only the
phase variations. The limiter outputs are ideally suited to
measure the I-Q phase difference, since its outputs are
square waves with sharp edges.
Demodulator
The demodulator demodulates the I and Q channel outputs
and produces a digital data output. It detects the relative
phase difference between the I and the Q channel signals.
For every edge (positive and negative) of the I channel limiter
output, the amplitude of the Q channel limiter output is
sampled, and vice versa. The output of the demodulator is
available on the DATAIXO pin. The data output is therefore
updated 4 times per cycle of the IF signal. This also means
that the maximum jitter of the data output is 1/(4×∆f) (valid
only for zero frequency offsets). If the I channel signal lags the
Q channel, the FSK tone frequency lies above the LO
frequency (data ‘1’). If the I channel leads the Q channel, the
FSK tone lies below the LO frequency (data ‘0’).
The inputs and the output of the demodulator are filtered by
first order RC low pass filters and then amplified by Schmitt
triggers to produce clean square waves.
It is recommended for low bitrates (<10kbps) that an additional capacitor is connected to Pin 18 (DataC) to decrease
the bandwidth of the Rx data signal filter. The bandwidth of
the filter must be adjusted for the bitrate. This functionality is
controlled by bit RxFilt.
Received Signal Strength Indicator (RSSI)
The RSSI provides a DC output voltage proportional to the
strength of the RF input signal. A graph of a typical RSSI
response is shown in Figure 9 (fDEV = 30kHz, Gc=1).
-90
Cut-Off Frequency (kHz)
-100
Bias Resistor (kΩ)
PIN (dBm)
Figure 9. Typical RSSI Characteristics
This graph shows a range of 0.7V to 2.05V over a RF input
range of 70dB.
The RSSI can be used as a signal presence indicator. When
a RF signal is received, the RSSI output increases. This could
be used to wake up circuitry that is normally in a sleep mode
configuration to conserve battery life.
Another application for which the RSSI could be used is to
determine if transmit power can be reduced in a system. If the
RSSI detects a strong signal, it could tell the transmitter to
reduce the transmit power to reduce current consumption.
13
MICRF500
MICRF500
Micrel
Programming
A two-line bus is used to program the circuit; the two lines
being CLKIN and REGIN. The 2-line serial bus interface
allows control over the frequency dividers and the selective
powering up of Tx, Rx and Synthesizer circuit blocks. The
interface consists of an 80-bit programming register. Data is
entered on the REGIN line with the most significant bit first.
The first bit entered is called p1, the last one p80. The bits in
the programming register are arranged as shown in Table 1.
p1 – p6
p7 - p12
p13 – p24
p25 – p36
p37 – p46
p47 – p56
p57
p58
A1
A0
N1
N0
M1
M0
RxFilt
Pa2
p59
p60
p61
p62
p63
p64
p65
p66
Pa1
Pa0
Gc
ByLNA
Ref6
Ref5
Ref4
Ref3
p67
p68
p69
p70
p71
p72
p73
p74
Ref2
Ref1
Ref0
Cpmp1
Cpmp0
Fc1
Fc0
OutS2
p75
p76
p77
p78
p79
p80
—
—
OutS1
OutS0
Mod1
Mod0
RT
Pu
—
—
Table 1. Bit Allocation
MICRF500
14
March 2003
MICRF500
Micrel
Name
Description
A1
frequency divider A1, 6 bits
A0
frequency divider A0, 6 bits
N1
frequency divider N1, 12 bits
N0
frequency divider N0, 12 bits
M1
frequency divider M1, 10 bits
M0
frequency divider M0, 10 bits
RxFilt
1=external capacitor for filtering of Rx data signal
Pa2
gain setting in power amplifier
Pa1
pa2, pa1, pa0 = 0 : lowest output power
Pa0
pa2, pa1, pa0 = 1 : highest output power
Gc
gain control in power amplifier buffer: 1=high gain
gain control in preamplifier in receiver: 1=high gain
ByLNA
1 = the LNA is bypassed
Ref6
Ref5
reference settings in lock detector
Ref4
Ref3
all 0’s: highest reference
Ref2
all 1’s: lowest reference
Ref1
Ref0
Cpmp1
charge pump setting:
Cpmp1=0, Cpmp0=1 : ±500µA
Cpmp1=1, Cpmp0=0 : controlled by LockDet (LD) LD=0: ±500µA, LD=1: ±125µA
Cpmp1=1, Cpmp0=1 : same as previous in Tx. In Rx the current is ±500µA.
Cpmp0
Fc1
Cpmp1=0, Cpmp0=0 : ±125µA
Active RC-filter settings
Fc0
Fc1=0, Fc0=0 : 10kHz
Fc1=1, Fc0=0 : 60kHz
Fc1=0, Fc0=1 : 30kHz
Fc1=1, Fc0=1 : 200kHz
OutS2
I- and Q-channel
OutS2 OutS1
OutS0 IchOut
QchOut
OutS2
OutS1
OutS0
IchOut
QchOut
OutS1
output select
0
0
high Z
1
0
0
lim_qch
gm_qch
OutS0
0
0
1
sk_ich
sk_qch
1
0
1
gm_ich
0
1
0
gm_ich gm_qch 1
1
0
high Z
0
1
1
lim_ich lim_qch 1
1
1
N_div
sk:_*:Sallen-Key filter output, gm_*:gyrator filter output, lim_*:limiter output, *_div:frequency divider output
(for testing). 110 is for dual-loop filter applications, see “Modulation Outside PLL, Dual-Loop Filters.”
lim_ich
Dual LF
M_div
Mod1
Mod1 = 0, Mod0 = 0: FSK modulation can be applied to the VCO
Mod0
Mod1 = 0, Mod0 = 1: FSK modulation can be applied to the VCO: open loop modulation
Mod1 = 1, Mod0 = 0: FSK modulation by switching between the two sets of dividers
Mod1 = 1, Mod0 = 1: FSK modulation by adding/subtracting 1 to divider A1: fdeviation = fcomparison
RT
0 = receive mode 1 = transmit mode
Pu
1 = power up, 0 = power down (When Pu=1, power down is controlled by PuExt)
0
high Z
Table 2. Bit Description
March 2003
15
MICRF500
MICRF500
Micrel
6. A new control word is entered into the first register. A
transition on the REGIN signal when CLKIN is high will
now turn the power amplifier off.
7. When the power amplifier is turned off an internal load
pulse is generated. The new control word is loaded into
the parallel register and the circuit enters a new mode
(in this case power down mode). CLKIN must go low
after the internal load pulse is generated.
As long as transitions on REGIN are avoided when CLKIN is
high, a new control word can be clocked into the first register
any time without affecting the operation of the transceiver.
Example 1. fRF = 869.0MHz, frequency deviation: ≈ ±10kHz,
fXCO = 10.00MHz. FSK modulation is implemented by switching between dividers.
When FSK modulation is applied to the VCO the PLL is using
the dividers A1, N1 and M1. When Mod1 = 1 and Mod0 = 0
it is possible to switch between the different dividers in the
PLL. DATAIXO controls the switching. When DATAIXO = 0
the PLL uses dividers A0, N0 and M0. When DATAIXO = 1 the
PLL uses dividers A1, N1 and M1. Switching between the
different dividers can be used to implement FSK modulation.
The N, M and A values can be calculated from the formula:
f
fRF
fC = XCO =
M
64 × N + A
where fC is the comparison frequency.
The 80bit control word is first read into a shift-register, and is
then loaded into a parallel register by a transition of the
REGIN signal (positive or negative) when the CLKIN signal is
high. The circuit then goes directly into the specified mode
(receive, transmit, etc.).
1
23
4
5
6
7
CLKIN
REGIN
LOAD_INT
A1
A0
N1
N0
M1
M0
Tx
9
27
137
134
101
99
Rx
50
50
135
135
100
100
RxFilt
Pa2
Pa1
Pa0
Gc
ByLNA
Tx
0
1
1
1
1
0
Rx
0
1
1
1
1
0
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Tx
0
0
0
0
0
0
Rx
0
0
0
0
0
0
Fc1
Fc0
OutS2
PA_C
Ref0
LOCKDET
Tx
0
1
0
0
1
0
Rx
0
1
0
0
1
0
OutS1
OutS0
Mod1
Mod0
RT
Pu
Tx
0
0
1
0
1
1
Rx
0
0
1
0
0
1
Figure 10. Timing of CLKIN, REGIN and the Internal
LOAD_INT and PA_C Signals
1. The second last bit is clocked into the first shift register
(‘1’).
2. The last bit is clocked into the first shift register (‘1’).
3. A transition on the REGIN signal generates an internal
load pulse that loads the control word into the parallel
register. The circuit enters the new mode (in this case
Tx-mode). The circuit stabilizes in the new mode.
4. When the clock signal goes low, the power amplifier
(PA) is turned on slowly in order to minimize spurious
components on the RF output signal. To be sure the
PLL is in lock before the PA is turned on, the PA should
be turned on after LOCKDET has been set.
The negative transition on the clock signal should come
a minimum time of one period of the comparison frequency after the internal load pulse is generated.
5. The power amplifier is fully turned on.
MICRF500
Cpmp1 Cpmp0
Binary form: (MSB to the left):
Tx:
001001 011011 000010001001
000010000110 0001100101 0001100011
011110000000001010001011
Rx:
110010 110010 000010000111
000010000111 0001100100 0001100100
01011110000000001010001001
When FSK modulation is implemented by switching between
the different dividers A, N and M values corresponding to the
receive frequency and both transmit frequencies have to be
found.
16
March 2003
MICRF500
Micrel
Example 2. fRF = 869.0MHz, fRF = 10.00MHz. FSK modulation is applied to the VCO.
A1
A0
N1
N0
M1
M0
Tx
50
50
135
135
100
100
Rx
50
50
135
135
100
100
RxFilt
Pa2
Pa1
Pa0
Gc
ByLNA
Tx
0
1
1
1
1
0
Rx
0
1
1
1
1
0
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Tx
0
0
0
0
0
0
Rx
0
0
0
0
0
0
Fc1
Fc0
OutS2
Ref0
Cpmp1 Cpmp0
Tx
0
0
1
1
0
0
Rx
0
0
1
1
0
0
OutS1
OutS0
Mod1
Mod0
RT
Pu
Tx
0
0
0
0
1
1
Rx
0
0
0
0
0
1
March 2003
Binary form: (MSB to the left):
Tx:
110010 110010 000010000111
000010000111 0001100100 0001100100
01011110000000010100000011
Rx:
111011 111011 000010001110
000010001110 0001101010 0001101010
01011110000000010100000001
With modulation applied to the VCO, A, N and M values
corresponding to the receive frequency have to be found. The
same set of A, N and M values are used in all modes.
Programming After Battery Reset
In order to ensure a successful programming after VDD has
been zero volts, the PDEXT needs to be kept low during the
first programming sequence. This can be done by a separate
110-line from a microcontroller, or a RC circuit on the PDEXT
pin to VDD (A capcitor between PDEXT and VDD). Using the
latter method, R and C values need to be chosen so that the
voltage on the PDEXT pin is lower than VDD/2 when the
controller word is loaded into the parallel register (see Figure
10).
17
MICRF500
MICRF500
Micrel
Package Information
0.551±0.012
(14.0±0.3)
0.394±0.012
(10.0±0.3)
0.315±0.012
(8.0±0.3)
44
34
1
33
11
23
0.031
(0.8)
12
22
0.039
(1.0)
0.085±0.004
(2.15±0.1)
0.016
(0.4)
0.002
(0.05)
0.047
(1.2)
44-Pin LQFP (BLQ)
MICREL, INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
MICRF500
18
March 2003
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