Cypress CY2313ANZ 13 output, 3.3v sdram buffer for desktop pcs with 3 dimm Datasheet

0NZCY2310
13ANZ
CY2313ANZ
13 Output, 3.3V SDRAM Buffer for
Desktop PCs with 3 DIMMs
Features
Functional Description
• One input to 13 output buffer/driver
• Supports up to three SDRAM DIMMs
• One additional outputs for feedback
• Serial interface for output control
• Low skew outputs
• Up to 100-MHz operation
• Multiple VDD and VSS pins for noise reduction
• Low EMI outputs
• 28-pin SOIC (300-mil) package
The CY2313ANZ is a 3.3V buffer designed to distribute
high-speed clocks in desktop PC applications. The part has 13
outputs, 12 of which can be used to drive up to three SDRAM
DIMMs, and the remaining can be used for external feedback
to a PLL. The device operates at 3.3V and outputs can run up
to 100 MHz, thus making it compatible with Pentium® II processors. The CY2313ANZ can be used in conjunction with the
CY2280, CY2281, CY2282 or similar clock synthesizer for a
complete Pentium II motherboard solution.
The CY2313ANZ also includes a serial interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled.
• 3.3V operation
Pin Configuration
Block Diagram
28 SOIC
Top View
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDATA
Serial Interface
Decoding
SCLOCK
VDD
SDRAM0
SDRAM1
VSS
VDD
SDRAM2
SDRAM3
VSS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDDIIC
SDATA
1
2
28
27
3
4
26
25
5
6
24
23
7
22
8
9
10
21
20
11
18
12
17
13
14
16
15
19
VDD
SDRAM11
SDRAM10
VSS
VDD
SDRAM9
SDRAM8
VSS
VDD
SDRAM7
SDRAM6
VSS
VSSIIC
SCLK
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07144 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
CY2313ANZ
Pin Summary
Name
Pins
Description
VDD
1, 5, 20, 24, 28
3.3V Digital voltage supply
VSS
4, 8, 17, 21, 25
Ground
VDDIIC
13
Serial interface voltage supply
VSSIIC
16
Ground for serial interface
BUF_IN
9
Input clock
SDATA
14
Serial data input, internal pull-up to VDD
SCLK
15
Serial clock input, internal pull-up to VDD
SDRAM [0-12]
2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23,
26, 27
SDRAM clock outputs
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”
• Serial interface address for the CY2313ANZ is:
A6
A5
1
1
A4
0
A3
A2
1
A1
0
0
A0
1
R/W
----
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enabled
Bit
Pin #
Description
Bit 7 11
SDRAM5 (Active/Inactive)
Bit 6 10
SDRAM4 (Active/Inactive)
Bit 5 --
Reserved, drive to 0
Bit 4 --
Reserved, drive to 0
Bit 3 7
SDRAM3 (Active/Inactive)
Bit 2 6
SDRAM2 (Active/Inactive)
Bit 1 3
SDRAM1 (Active/Inactive)
Bit 0 2
SDRAM0 (Active/Inactive)
Document #: 38-07144 Rev. *A
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
27
SDRAM11 (Active/Inactive)
Bit 6
26
SDRAM10 (Active/Inactive)
Bit 5
23
SDRAM9 (Active/Inactive)
Bit 4
22
SDRAM8 (Active/Inactive)
Bit 3
--
Reserved, drive to 0
Bit 2
--
Reserved, drive to 0
Bit 1
19
SDRAM7 (Active/Inactive)
Bit 0
18
SDRAM6 (Active/Inactive)
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
--
Reserved, drive to 0
Bit 6
12
SDRAM12 (Active/Inactive)
Bit 5
--
Reserved, drive to 0
Bit 4
--
Reserved, drive to 0
Bit 3
--
Reserved, drive to 0
Bit 2
--
Reserved, drive to 0
Bit 1
--
Reserved, drive to 0
Bit 0
--
Reserved, drive to 0
Page 2 of 8
CY2313ANZ
Maximum Ratings
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Storage Temperature ................................. –65°C to +150°C
DC Input Voltage (Except BUF_IN)........–0.5V to VDD + 0.5V
Junction Temperature................................................. 150°C
DC Input Voltage (BUF_IN)............................ –0.5V to +7.0V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions[1]
Parameter
Description
Min.
Max.
Unit
3.135
3.465
V
0
70
°C
Load Capacitance
30
pF
CIN
Input Capacitance
7
pF
tPU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Min.
Max.
Unit
0.8
V
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Electrical Characteristics Over the Operating Range
Parameter
Description
Voltage[2]
Test Conditions
VIL
Input LOW
VILiic
Input LOW Voltage
VIH
Input HIGH Voltage[2]
IIL
Input LOW Current
(BUF_IN input)
VIN = 0V
IIL
Input LOW Current
(Except BUF_IN Pin)
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage[3]
IOL = 25 mA
VOH
Voltage[3]
Output HIGH
Except serial interface pins
For serial interface pins only
0.7
2.0
IOH = –36 mA
–10
–10
V
V
10
µA
100
µA
10
µA
0.4
V
2.4
V
Supply
Current[3]
Unloaded outputs, 100 MHz
IDD
Supply
Current[3]
Loaded outputs, 100 MHz
290
mA
IDD
Supply Current[3]
Unloaded outputs, 66.67 MHz
150
mA
IDD
Supply Current[3]
Loaded outputs, 66.67 MHz
185
mA
IDDS
Supply Current
BUF_IN=VDD or VSS
All other inputs at VDD
500
µA
IDD
200
mA
Notes:
1. Electrical parameters are guaranteed under the operating conditions specified.
2. BUF_IN input has a threshold voltage of VDD/2.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07144 Rev. *A
Page 3 of 8
CY2313ANZ
Switching Characteristics[4] Over the Operating Range
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
100
MHz
Measured at 1.5V
45.0
50.0
55.0
%
Rising Edge
Rate[3]
Measured between 0.4V and 2.4V
0.9
1.5
4.0
V/ns
Falling Edge
Rate[3]
Measured between 2.4V and 0.4V
0.9
1.5
4.0
V/ns
Maximum Operating Frequency
Duty Cycle[3,5] = t2 ÷ t1
t3
t4
Skew[3]
t5
Output to Output
+250
ps
t6
SDRAM Buffer LH Prop. Delay[3]
Input edge greater than 1 V/ns
1.0
3.5
5.0
ns
t7
Delay[3]
SDRAM Buffer HL Prop.
t8
t9
All outputs equally loaded
–250
Input edge greater than 1 V/ns
1.0
3.5
5.0
ns
SDRAM Buffer Enable
Delay[3]
Input edge greater than 1 V/ns
1.0
5
12
ns
SDRAM Buffer Disable
Delay[3]
Input edge greater than 1 V/ns
1.0
20
30
ns
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns.
Switching Waveforms
Duty Cycle Timing
t1
t2
1.5V
1.5V
1.5V
All Outputs Rise/Fall Time
OUTPUT
2.4V
0.4V
2.4V
0.4V
3.3V
0V
t4
t3
Output-Output Skew
OUTPUT
1.5V
1.5V
OUTPUT
t5
Document #: 38-07144 Rev. *A
Page 4 of 8
CY2313ANZ
Switching Waveforms (continued)
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
t7
SDRAM Buffer Enable and Disable Times
OE
Three-State
Active
OUTPUTS
t8
t9
Test Circuit
VDD
0.1 µF
OUTPUTS
CLK out
CLOAD
GND
Document #: 38-07144 Rev. *A
Page 5 of 8
CY2313ANZ
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Application Circuit
Rs
CPUCLK
BUF_IN
PCICLK
USBCLK
REF
Rs
SDATA
SDATA
SCLK
SDRAM ( 0-12)
SDRAM ( 0-12)
SCLK
V DD 3.3V
APIC
Ct
V DD
* CY2280 48 PIN SSOP
(or CY2281 or CY2282)
Cd
0.1uF
V SS
CY2313 28
PIN SOIC
CY2313A:
28-PIN
SOIC
* THIS FREQUENCY SYNTHESIZER IS USED TO
GENERATE CPU, PCI, USB, REF, AND APIC CLOCKS.
Cd = DECOUP LING CAPACITOR S
Ct = OPTIONAL EMI-R EDUCING CAP ACI TORS
Rs = SERIES TERMINATING RESISTORS
Summary
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance
of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
Ordering Information
Ordering Code
CY2313ANZSC–1
Document #: 38-07144 Rev. *A
Package
Name
S21
Package Type
28-Pin SOIC
Operating
Range
Commercial
Page 6 of 8
CY2313ANZ
Package Diagram
28-Lead (300-Mil) Molded SOIC S21
51-85026-A
Document #: 38-07144 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2313ANZ
Document Title: CY2313ANZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Document Number: 38-07144
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110253
11/18/01
DSG
Change from Spec number: 38-00692 to 38-07144
*A
121831
12/14/02
RBI
Power up requirements added to Operating Conditions Information
Document #: 38-07144 Rev. *A
Page 8 of 8
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