TI1 ISO7240CFDWRG4 High speed quad digital isolator Datasheet

ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
HIGH SPEED QUAD DIGITAL ISOLATORS
Check for Samples: ISO7240CF, ISO7240C, ISO7240M, ISO7241C, ISO7241M, ISO7242C, ISO7242M
FEATURES
1
•
•
•
•
•
•
•
Selectable Failsafe Output (ISO7240CF)
25 and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns Max
– Low Pulse-Width Distortion (PWD);
2 ns Max
– Low Jitter Content; 1 ns Typ at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 17)
4000-Vpeak VIOTM, 560-Vpeak VIORM per IEC
60747-5-2 (VDE 0884, Rev 2)
UL 1577 , IEC 61010-1, IEC 60950-1 and CSA
Approved
•
•
4 kV ESD Protection
Operates With 2.8-V (ISO7241C), 3.3-V or 5-V
Supplies
High Electromagnetic Immunity
(see application report SLLA181)
–40°C to 125°C Operating Range
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging
sensitive circuitry.
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same
direction and one channel in opposition. The ISO7242 has two channels in each direction.
The C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from
being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds and do not
have the input noise-filter or the additional propagation delay.
The ISO7240CF has an input disable function on pin 7, and a selectable high or low failsafe-output function with
the CTRL pin (pin 10). The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left
unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output
state. The ISO7240CF input disable function prevents data from being passed across the isolation barrier to the
output. When the inputs are disabled, the outputs are set by the CTRL pin.
These devices may be powered from 2.8-V (ISO7241C only), 3.3-V or 5-V supplies on either side in any
combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
VCC1
GND1
INA
INB
INC
IND
DISABLE
GND1
ISO7240CF
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
ISO7240
VCC2 VCC1
GND2 GND1
OUTA
INA
INB
OUTB
INC
OUTC
OUTD
IND
CTRL
NC
GND2 GND1
1
2
3
4
5
6
7
8
ISO7241
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
OUTD
EN
GND2
VCC1
GND1
INA
INB
INC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
ISO7242
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
IND
EN2
GND2
VCC1
GND1
INA
INB
OUTC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
IND
EN2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. Device Function Table ISO724x
INPUT VCC
(1)
OUTPUT VCC
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
PU
PU
Open
H or Open
H
PD
PU
X
H or Open
H
PD
PU
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
Table 2. ISO7240CF Function Table
VCC1
VCC2
DATA INPUT
(IN)
DISABLE INPUT
(DISABLE)
FAILSAFE CONTROL INPUT
(CTRL)
DATA OUTPUT
(OUT)
PU
PU
H
L or Open
X
H
PU
PU
L
L or Open
X
L
X
PU
X
H
H or Open
H
X
PU
X
H
L
L
PD
PU
X
X
H or Open
H
PD
PU
X
X
L
L
AVAILABLE OPTIONS
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ISO7240C
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7240CF
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7240M
150 Mbps
Vcc/2 (CMOS)
ISO7240M
ISO7241C
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7241C
ISO7241M
150 Mbps
Vcc/2 (CMOS)
ISO7241M
ISO7242C
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7242C
ISO7240C
4/0
ISO7240CF
3/1
2/2
ISO7242M
(1)
2
150 Mbps
Vcc/2 (CMOS)
ISO7242M
ORDERING
NUMBER (1)
ISO7240CDW (rail)
ISO7240CDWR (reel)
ISO7240CFDW (rail)
ISO7240CFDWR (reel)
ISO7240MDW (rail)
ISO7240MDWR (reel)
ISO7241CDW (rail)
ISO7241CDWR (reel)
ISO7241MDW (rail)
ISO7241MDWR (reel)
ISO7242CDW (rail)
ISO7242CDWR (reel)
ISO7242MDW (rail)
ISO7242MDWR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 to 6
V
VI
Voltage at IN, OUT, EN, DISABLE, CTRL
–0.5 to 6
V
IO
Output current
±15
mA
ESD
Electrostatic
discharge
TJ
Maximum junction temperature
(1)
(2)
Human Body Model
JEDEC Standard 22, Test Method A114-C.01
Field-Induced-Charged Device Model
JEDEC Standard 22, Test Method C101
Machine Model
ANSI/ESDS5.2-1996
±4
kV
±1
All pins
±200
V
170
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
ISO7240C/CF, ISO7242C,
ISO724xM,
Supply voltage (1), VCC1, VCC2
VCC
ISO7241C
IOH
High-level output current
IOL
Low-level output current
3.15
5.5
2.8
5.5
ISO724xC
40
ISO724xM
6.67
5
ISO724xC
0
30 (2)
25
ISO724xM
0
200 (2)
150
1/tui
Signaling rate
VIH
High-level input voltage (IN)
VIL
Low-level input voltage (IN)
VIH
High-level input voltage (IN, DISABLE, CTRL, EN)
VIL
Low-level input voltage (IN, DISABLE, CTRL, EN)
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification
ISO724xM
ISO724xC
UNIT
V
mA
4
Input pulse width
(2)
MAX
-4
tui
(1)
TYP
mA
ns
Mbps
0.7 VCC
VCC
V
0
0.3 VCC
V
2
VCC
V
0
0.8
V
150
°C
1000
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
For the 2.8-V operation (ISO7241C-only), VCC1 or VCC2 is specified at 2.8 V.
Typical value at room temperature and well-regulated power supply.
IEC 60747-5-2 INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
Maximum working insulation voltage
Input to output test voltage
SPECIFICATIONS
UNIT
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
V
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
V
VIOTM
Transient overvoltage
t = 60 s
4000
V
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Copyright © 2007–2012, Texas Instruments Incorporated
3
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7240C/M
ICC1
ISO7241C/M
ISO7242C/M
ISO7240C/M
ICC2
ISO7241C/M
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V-
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V-
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
1
3
7
10.5
All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
12
18
All channels, no load,
EN1 at 3 V, EN2 at 3 V
10
16
15
24
All channels, no load,
EN at 3 V
15
22
17
25
All channels, no load,
EN1 at 3 V, EN2 at 3 V
13
20
18
28
All channels, no load,
EN1 at 3 V, EN2 at 3 V
10
16
15
24
All channels, no load,
EN at 3 V
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
VOL
Low-level output voltage
EN at 0 V, Single channel
VCC–0.8
IOH = –20 μA, See Figure 1
VCC–0.1
0.4
IOL = 20 μA, See Figure 1
0.1
150
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
4
V
IOL = 4 mA, See Figure 1
VI(HYS) Input voltage hysteresis
(1)
μA
0
IOH = –4 mA, See Figure 1
IN from 0 V to VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
12
μs
twake
Wake time from input disable
See Figure 4
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps NRZ data input, Same
polarity input on all channels, See
Figure 6
1
ns
(1)
(2)
(3)
ISO724xC
See Figure 1
ISO724xM
42
UNIT
tPLH, tPHL
tjit(pp)
18
MAX
2.5
10
23
1
ISO724xC
(2)
8
ISO724xM
(3)
0
ISO724xC
3
2
ISO724xM
0
See Figure 1
ISO724xM
2
See Figure 2
1
2
ns
ns
ns
ns
ns
2
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2012, Texas Instruments Incorporated
5
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7240C/M
ICC1
ISO7241C/M
ISO7242C/M
ISO7240C/M
ICC2
ISO7241C/M
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock
Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock
Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock
Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock
Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock
Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock
Signal
1
3
7
10.5
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
6.5
11
12
18
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
10
16
15
24
9.5
15
10.5
17
8
13
11.5
18
6
10
9
14
All channels, no load,
EN at 3 V
All channels, no load,
EN at 3 V
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
ISO7240
VCC–0.4
ISO724x (5-V side)
VCC–0.8
IOH = –20 μA, See Figure 1
0.4
IOL = 20 μA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
6
V
VCC–0.1
IOL = 4 mA, See Figure 1
VOL
(1)
μA
0
150
IN from 0 V to VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
Propagation delay
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
18
μs
twake
Wake time from input disable
See Figure 4
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data
input, Same polarity input on
all channels, See Figure 6
1
ns
(1)
(2)
(3)
50
UNIT
PWD
tjit(pp)
20
MAX
tPLH, tPHL
ISO724xC
See Figure 1
MIN
3
ISO724xM
12
29
1
ISO724xC
(2)
10
ISO724xM
(3)
0
ISO724xC
5
3
ISO724xM
0
See Figure 1
ISO724xM
2
See Figure 2
1
2
ns
ns
ns
ns
ns
2
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2012, Texas Instruments Incorporated
7
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
3
5
4
7
6.5
11
All channels, no
load, EN1 at 3 V,
EN2 at 3 V
6
10
9
14
All channels, no
load, EN at 3 V
15
22
17
25
All channels, no
load, EN1 at 3 V,
EN2 at 3 V
13
20
18
28
All channels, no
load, EN1 at 3 V,
EN2 at 3 V
10
16
15
24
UNIT
SUPPLY CURRENT
ISO7240C/M
ISO7241C/M
ICC1
ISO724C/M
ISO7240C/M
ISO7241C/M
ICC2
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
All channels, no
load, EN at 3 V
All channels, no
load, EN1 at 3 V,
EN2 at 3 V
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
ISO724x (5-V side)
VCC – 0.8
V
VCC – 0.1
0.4
IOL = 20 μA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
8
VCC – 0.4
IOL = 4 mA, See Figure 1
VOL
(1)
μA
0
ISO7240
150
IN from 0 V to VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
22
51
UNIT
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
12
μs
twake
Wake time from input disable
See Figure 4
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps NRZ data input, Same
polarity input on all channels, See
Figure 6
1
ns
tjit(pp)
(1)
(2)
(3)
ISO724xC
See Figure 1
ISO724xM
3
12
30
1
ISO724xC
(2)
10
ISO724xM
(3)
0
ISO724xC
5
2.5
ISO724xM
0
See Figure 1
ISO724xM
2
See Figure 2
1
2
ns
ns
ns
ns
ns
2
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2012, Texas Instruments Incorporated
9
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7240C/M
ISO7241C/M
ICC1
ISO7242C/M
ISO7240C/M
ISO7241C/M
ICC2
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
All channels, no load,
EN at 3 V
All channels, no load,
EN1 at 3 V, EN2 at 3 V
All channels, no load,
EN1 at 3 V, EN2 at 3 V
All channels, no load,
EN at 3 V
All channels, no load,
EN1 at 3 V, EN2 at 3 V
All channels, no load,
EN1 at 3 V, EN2 at 3 V
0.5
1
3
5
4
7
6.5
11
6
10
9
14
9.5
15
10.5
17
8
13
11.5
18
6
10
9
14
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
VOL
Low-level output voltage
EN at 0 V, single channel
VCC–0.4
IOH = –20 μA, See Figure 1
VCC–0.1
0.4
IOL = 20 μA, See Figure 1
0.1
150
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
10
V
IOL = 4 mA, See Figure 1
VI(HYS) Input voltage hysteresis
(1)
μA
0
IOH = –4 mA, See Figure 1
IN from 0 V or VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
25
56
UNIT
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
18
μs
twake
Wake time from input disable
See Figure 4
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input,
same polarity input on all channels,
See Figure 6
1
ns
tjit(pp)
(1)
(2)
(3)
ISO724xC
See Figure 1
ISO724xM
4
12
34
1
ISO724xC
(2)
10
ISO724xM
(3)
0
ISO724xC
5
3.5
ISO724xM
0
See Figure 1
ISO724xM
2
See Figure 2
1
ns
ns
ns
ns
2
ns
2
ns
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2012, Texas Instruments Incorporated
11
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 2.8 V (ISO7241C only) (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ICC1
ISO7241C
ICC2
ISO7241C
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
All channels, no load,
EN1 at 3 V, EN2 at 3 V
3.9
6.8
6.2
10.5
All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.9
12
9.4
16
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
VOL
Low-level output voltage
EN1 at 0 V, single channel
μA
0
IOH = –4 mA, See Figure 1
VCC–0.6
IOH = –20 μA, See Figure 1
VCC–0.1
V
IOL = 4 mA, See Figure 1
0.6
IOL = 20 μA, See Figure 1
0.1
VI(HYS) Input voltage hysteresis
150
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
IN from 0 V or VCC
mV
10
–10
10
V
μA
2
pF
45
kV/μs
(1)
For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8-V.
2.8-V operation is only guaranteed for ISO7241C with production screening starting in January 2012. The first two digits of the Lot Trace
Code (YMLLLLS) written on top of each device can be used to identify year and month of production respectively.
12
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 2.8-V OPERATION (ISO7241C only)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
25
70
UNIT
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
tPZH
Propagation delay, high-impedance-to-high-level output
tPLZ
Propagation delay, low-level-to-high-impedance output
tPZL
Propagation delay, high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
See Figure 3
7
μs
twake
Wake time from input disable
See Figure 4
12
μs
(1)
(2)
(3)
(2)
(3)
ISO7241C
See Figure 1
5
ns
ISO7241C
12
ns
ISO7241C
5
ns
See Figure 1
See Figure 2
2
ns
2
ns
15
25
15
25
15
25
15
25
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2012, Texas Instruments Incorporated
13
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC
VI
VCC/2
VCC/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
VCC
ISOLATION BARRIER
0V
RL = 1 kW ±1%
IN
Input
Generator
VI
OUT
EN
VCC/2
VI
t PZL
VO
VO
CL
VCC/2
0V
t PLZ
VCC
0.5 V
50%
NOTE
B
50 W
VOL
3V
ISOLATION BARRIER
NOTE A
IN
Input
Generator
VI
OUT
VO
VCC
VCC/2
VI
VCC/2
0V
EN
50 W
t PZH
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
14
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VI
0V
or
VCC1
A.
IN
VCC
ISOLATION BARRIER
VCC
2.7 V
VI
OUT
0V
VO
tfs
VOH
CL
NOTE A
VO
50%
fs low
VOL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
3V
IN
DISABLE
ISOLATION BARRIER
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
OUT
VCC
VO
VI
0V
CTRL
t wake
VCC
CL
Input
VI
Generator
0V
50 %
( Note B)
50 W
VO
IN
0V
DISABLE
ISOLATION BARRIER
( Note A)
0V
VCC
OUT
VO
VI
VCC/2
0V
t wake
CTRL
VCC2
CL
Input
Generator
VCC/2
VI
3V
50 W
(Note B )
VO
( Note A )
50 %
0V
NOTE: Which ever test yields the longest time is used in this data sheet
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Wake Time From Input Disable Test Circuit and Voltage Waveforms
Copyright © 2007–2012, Texas Instruments Incorporated
15
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VCC1
VCC2
IN
S1
C = 0.1 mF± 1%
ISOLATION BARRIER
C = 0.1 mF± 1%
OUT
Pass-fail criteria:
Output must
remain stable
VOH or VOL
NOTE B
GND1
GND2
VCM
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
VCC
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
L(I01)
TEST CONDITIONS
MIN
TYP MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
CTI
Tracking resistance (comparative
tracking index)
DIN IEC 60112/VDE 0303 Part 1
≥ 400
V
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
mm
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
CIO
Barrier capacitance Input to output
CI
Input capacitance to ground
>1012
Ω
VI = 0.4 sin (4E6πt)
2
pF
VI = 0.4 sin (4E6πt)
2
pF
IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
Installation classification
16
TEST CONDITIONS
Material group
SPECIFICATION
II
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
spacer
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice 5A
Recognized under 1577
Component Recognition Program
Basic Insulation
Maximum Transient Overvoltage,
4000 VPK
Maximum Surge Votlage, 4000
VPK
Maximum Working Voltage, 560
VPK
Basic insulation per CSA
60950-1-07 and IEC 60950-1
(2nd Ed), 395 VRMS maximum
working voltage, 4000 VPK
maximum isolation rating
Single protection, 2500 VRMS (1)
File Number: 40016131
File Number: 220991
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
spacer
DEVICE I/O SCHEMATICS
Enable
VCC
Output
Input
VCC
VCC
VCC
VCC
VCC
1 MW
1 MW
500 W
EN
VCC
IN
8W
500 W
OUT
13 W
ISO7240CF
Input
VCC
VCC
IN
500 W
1 MW
Copyright © 2007–2012, Texas Instruments Incorporated
17
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
θJC
Junction-to-Case Thermal Resistance
PD
(1)
MIN
TYP MAX
(1)
168
High-K Thermal Resistance
°C/W
96.1
61
°C/W
48
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
Device Power Dissipation
UNIT
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
spacer
TYPICAL CHARACTERISTIC CURVES
ISO7240C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
ISO7241C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
45
45
TA = 25°C,
Load = 15 pF,
All Channels
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
40
35
5-V ICC2
30
3.3-V ICC2
25
20
5-V ICC1
15
10
5
35
5-V ICC2
30
20
3.3-V ICC2
15
50
75
100
Signaling Rate - Mbps
125
5
0
0
150
100
ISO7242C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
125
150
45
TA = 25°C,
Load = 15 pF,
All Channels
40
C 3.3-V tpLH, tpHL
35
30
Propagation Delay - ns
ICC - Supply Current - mA/RMS
75
Figure 8.
5-V ICC1,ICC2
25
20
15
3.3-V ICC1,ICC2
C 5-V tpLH, tpHL
30
25
M 3.3-V tpLH, tpHL
20
15
M 5-V tpLH, tpHL
10
10
5
5
TA = 25°C,
Load = 15 pF,
All Channels
0
25
50
75
100
Signaling Rate - Mbps
Figure 9.
18
50
Figure 7.
35
0
0
25
Signaling Rate - Mbps
45
40
3.3-V ICC1
10
0
25
5-V ICC1
25
3.3-V ICC1
0
TA = 25°C,
Load = 15 pF,
All Channels
125
150
-40
-25
-10
5
80
65
35
20
50
TA - Free-Air Temperature - °C
95
110
125
Figure 10.
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
INPUT VOLTAGE THRESHOLD
vs
FREE-AIR TEMPERATURE
VCC UNDERVOLTAGE THRESHOLD
vs
FREE-AIR TEMPERATURE
1.4
3
5 V Vth+
1.3
2.9
VCC - Undervoltage Threshold - V
Input Voltage Threshold - V
1.35
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low_K Board
1.15
5 V Vth1.1
1.05
1
-40
3.3 V Vth-25
-10
VCC Rising
2.7
2.6
2.5
VCC Falling
2.4
2.3
2.2
2.1
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
2
-40
125
-25
-10
5
20
35
50
65
80
95
110
125
TA - Free-Air Temperature - °C
Figure 11.
Figure 12.
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
50
VCC = 5 V
Load = 15 pF,
TA = 25°C
Load = 15 pF,
TA = 25°C
45
40
IO - Output Current - mA
40
IO - Output Current - mA
2.8
VCC = 3.3 V
30
20
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
10
5
0
0
0
2
4
VO - Output Voltage - V
Figure 13.
Copyright © 2007–2012, Texas Instruments Incorporated
6
0
1
2
3
VO - Output Voltage - V
4
5
Figure 14.
19
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
APPLICATION INFORMATION
2 mm
max. from
VCC1
VCC1
2 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
IN D
6
11
GND1
GND2
NC
7
10
8
9
OUT D
EN
GND2
GND1
ISO7240x
Figure 15. Typical ISO7240x Application Circuit
2 mm
max. from
VCC1
VCC1
2 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
6
11
GND1
IN D
GND2
DISABLE
OUT D
CTRL
7
10
8
9
GND2
GND1
ISO7240CF
Figure 16. Typical ISO7240CF Failsafe-Low Application Circuit
20
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
www.ti.com
LIFE EXPECTANCY vs. WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 17. Time-Dependant Dielectric Breakdown Testing Results
REVISION HISTORY
Changes from Original (September 2007) to Revision A
Page
•
Deleted Product Preview note .............................................................................................................................................. 2
•
Changed VCC Supply Voltage in the ROC Table From: 3.6 To: 3.45 ................................................................................... 3
•
Changed VCC Supply Voltage in the ROC Table From: 3 To: 3.15 ...................................................................................... 3
•
Changed TBDs to actual values. .......................................................................................................................................... 4
•
Changed CI - typ value From: 1 To: 2 .................................................................................................................................. 4
•
Changed Propagation delay max From: 22 To: 23 .............................................................................................................. 5
•
Changed CI - typ value From: 1 To: 2 .................................................................................................................................. 6
•
Changed Propagation delay max From: 46 To: 50 .............................................................................................................. 7
•
Changed Propagation delay max From: 28 To: 29 .............................................................................................................. 7
•
Changed ISO724xA/C max value From: 2.5 To: 3 ............................................................................................................... 7
•
Changed CI - typ value From: 1 To: 2 .................................................................................................................................. 8
•
Changed Propagation delay max From: 26 To: 30 .............................................................................................................. 9
•
Changed typ value From: 1 To: 2 ....................................................................................................................................... 10
•
Changed Propagation delay max From: 32 To: 34 ............................................................................................................ 11
•
Changed ISO724xA/C max value From: 3 To: 3.5 ............................................................................................................. 11
•
Changed CIO - typ value From: 1 To: 2 .............................................................................................................................. 16
•
Changed CI - typ value From: 1 To: 2 ................................................................................................................................ 16
•
Changed the REGULATORY INFORMATION Table ......................................................................................................... 17
•
Changed Figure 7, Figure 8, and Figure 10. Added Figure 9. ........................................................................................... 18
Changes from Revision A (December 2007) to Revision B
•
Page
Changed VCC Supply Voltage in the ROC Table From: 3.45 To: 3.6 ................................................................................... 3
Changes from Revision B (August 2008) to Revision C
Page
•
Deleted Min = 4.5 V and max = 5.5 V for Supply Voltage of the ROC Table. ..................................................................... 3
•
Changed VCC Supply Voltage in the ROC Table From: 3.6 To: 5.5 ..................................................................................... 3
Copyright © 2007–2012, Texas Instruments Incorporated
21
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
Changes from Revision C (April 2008) to Revision D
www.ti.com
Page
•
Changed Feature Bullet 4000-Vpeak Isolation ........................................................................................................................ 1
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 5
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 7
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 9
•
Added tsk(pp) Part-to-part skew ............................................................................................................................................ 11
•
Changed Typical ISO724x Application Circuit Figure 15 .................................................................................................... 20
Changes from Revision D (April 2008) to Revision E
Page
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. .............................................. 3
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V ............................................... 6
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V ............................................... 8
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V ............................................. 10
Changes from Revision E (May 2008) to Revision F
Page
•
Changed Title From: QUAD DIGITAL ISOLATORS To: HIGH SPEED QUAD DIGITAL ISOLATORS ............................... 1
•
Deleted ISO724xA devices. See SLLS905 for the ISO7240A, ISO7241A, and ISO7242A. ................................................ 1
•
Changed Feature Low Jitter Content - From: 1, 25, and 150-Mbps Signaling Rate Options To: 25, and 150-Mbps
Signaling Rate Options ......................................................................................................................................................... 1
•
Added tsk(pp) footnote. ............................................................................................................................................................ 5
•
Added tsk(o) footnote. ............................................................................................................................................................. 5
•
Added tsk(pp) footnote. .......................................................................................................................................................... 11
•
Added tsk(o) footnote. ........................................................................................................................................................... 11
Changes from Revision F (May 2008) to Revision G
•
Page
Changed the PACKAGE CHARACTERISTICS table, line , L(IO1) MIN value from7.7mm to 8.34mm ................................ 16
Changes from Revision G (July 2008) to Revision H
Page
•
Added Device number ISO7240CF. ..................................................................................................................................... 1
•
Added Features Bullet: Selectable Failsafe Output (ISO7240CF) ....................................................................................... 1
•
Changed description paragraph 4 text. ................................................................................................................................. 1
•
Added for device number ISO7240CF. ................................................................................................................................. 2
•
Changed VI in the Abs Max Table From: Voltage at IN, OUT, EN To: Voltage at IN, OUT, EN, DISABLE, CTRL ............. 3
•
Added twake, Wake time from input disable ........................................................................................................................... 5
•
Added twake, Wake time from input disable ........................................................................................................................... 7
•
Added twake, Wake time from input disable ........................................................................................................................... 9
•
Added twake, Wake time from input disable ......................................................................................................................... 11
Changes from Revision H (October 2008) to Revision I
•
22
Page
Added information to the Features bullet to include CSA and IEC 60950-1 certification ..................................................... 1
Copyright © 2007–2012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
Changes from Revision I (December 2008) to Revision J
SLLS868N – SEPTEMBER 2007 – REVISED JANUARY 2012
Page
•
Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 4
•
Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 6
Changes from Revision J (April 2009) to Revision K
•
Page
Changed the Input circuit in the DEVICE I/O SCHEMATICS illustration ............................................................................ 17
Changes from Revision K (Decemberl 2009) to Revision L
Page
•
Added the IEC 60747-5-2 INSULATION CHARACTERISTIC table ..................................................................................... 3
•
Added CTI - Tracking resistance (comparative tracking index to the PACKAGE CHARACTERISTICS table .................. 16
•
Added the IEC 60664-1 RATINGS TABLE ......................................................................................................................... 16
Changes from Revision L (January 2010) to Revision M
Page
•
Changed Figure 1, Figure 3, and Figure 4 ......................................................................................................................... 14
•
Changed the CSA File Number From: 1698195 To: 220991 ............................................................................................. 17
Changes from Revision M (January 2011) to Revision N
Page
•
Changed Feature From: 4000-Vpeak Isolation, 560-Vpeak VIORM To: 4000-Vpeak VIOTM, 560-Vpeak VIORM per IEC
60747-5-2 (VDE 0884, Rev 2) .............................................................................................................................................. 1
•
Changed Feature From: Operates 3.3-V or 5-V Supplies To: Operates With 2.8-V (ISO7241C), 3.3-V or 5-V
Supplies ................................................................................................................................................................................ 1
•
Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table .................................................. 3
•
Changed Table Note (1) ....................................................................................................................................................... 3
•
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 5-V table ............................................................................. 4
•
Changed Table Note (1) ....................................................................................................................................................... 4
•
Changed ICC1 and ICC2 test conditions in the VCC1 at 5-V, VCC2 at 3.3-V table ...................................................................... 6
•
Changed Table Note (1) ....................................................................................................................................................... 6
•
Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3-V, VCC2 at 5-V table ...................................................................... 8
•
Changed Table Note (1) ....................................................................................................................................................... 8
•
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table ........................................................................ 10
•
Changed Table Note (1) ..................................................................................................................................................... 10
•
Added ELECTRICAL and Switching CHARACTERISTICS tables forVCC1 and VCC2 at 2.8V (ISO722xC-only) ................. 12
•
Changed the CTI MIN value From: ≥175 V To:≥400 V ...................................................................................................... 16
•
Changed the REGULATORY INFORMATION Table ......................................................................................................... 17
•
Changed Figure 12 From VCC1 Failsafe Threshold To: VCC Undervoltage Threshold ........................................................ 19
Copyright © 2007–2012, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
ISO7240CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CFDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CFDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CFDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240CFDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240MDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7240MDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241CDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 1
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Aug-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
ISO7241MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241MDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7241MDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242CDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242MDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ISO7242MDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7240CF, ISO7241C, ISO7242C :
• Automotive: ISO7240CF-Q1, ISO7241C-Q1, ISO7242C-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7240CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7240CFDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7240MDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7241CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7242CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7240CDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7240CFDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7240MDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7241CDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7242CDWR
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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