Cypress CY7C1049B-15VI 512k x 8 static ram Datasheet

049B
CY7C1049B
512K x 8 Static RAM
Features
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
• High speed
— tAA = 12 ns
• Low active power
— 1320 mW (max.)
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description[1]
The CY7C1049B is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
512K x 8
ARRAY
I/O3
I/O4
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
A 11
A 12
A 13
A14
A15
A16
A17
A18
WE
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Selection Guide
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20
7C1049B-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA)
240
220
195
185
180
Com’l
8
8
8
8
8
Com’l/Ind’l L
-
-
0.5
0.5
0.5
Ind’l
-
-
-
9
9
Maximum CMOS Standby
Current (mA)
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05169 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C1049B
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in High Z State[2] ....................................–0.5V to VCC + 0.5V
VCC
Commercial
0°C to +70°C
4.5V–5.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1049B-12
7C1049B-15
7C1049B-17
Min.
Min.
Min.
Max.
2.4
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
V
VIL
Input LOW Voltage[2]
–0.3
0.8
–0.3
0.8
–0.3
0.3
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1
+1
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
240
220
195
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40
40
40
mA
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
8
8
8
mA
-
-
0.5
mA
-
-
8
mA
-
-
0.5
mA
0.4
Com’l
Com’l
L
Ind’l
Ind’l
2.4
Max.
L
2.4
0.4
V
Note:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
Document #: 38-05169 Rev. *A
Page 2 of 10
CY7C1049B
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
Parameter
7C1049B-20
Description
Min.
7C1049B-25
Max.
Min.
2.4
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
2.4
VIH
Input HIGH Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VIL
Input LOW Voltage[2]
–0.3
0.8
–0.3
0.8
V
0.4
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
185
180
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40
40
mA
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Com’l
Com’l
8
8
mA
L
0.5
0.5
mA
8
8
mA
L
0.5
0.5
mA
Ind’l
Ind’l
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
8
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481Ω
5V
R1 481 Ω
5V
OUTPUT
ALL INPUT PULSES
3.0V
90%
OUTPUT
30 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
(a)
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤ 3 ns
10%
90%
10%
≤ 3 ns
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Equivalent to:
Document #: 38-05169 Rev. *A
Page 3 of 10
CY7C1049B
Switching Characteristics[4] Over the Operating Range
7C1049B-12
Parameter
Description
Min.
Max.
7C1049B-15
Min.
Max.
7C1049B-17
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the First Access[5]
1
1
1
ms
tRC
Read Cycle Time
12
15
17
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
17
ns
tDOE
OE LOW to Data Valid
6
7
8
ns
[7]
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
CE LOW to Low
Z[7]
CE HIGH to High
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
15
3
0
3
6
ns
3
0
12
ns
7
7
ns
7
ns
0
15
ns
ns
0
7
3
0
17
3
0
6
Z[6, 7]
tHZCE
Write Cycle
12
3
ns
17
ns
[8, 9]
tWC
Write Cycle Time
12
15
17
ns
tSCE
CE LOW to Write End
10
12
12
ns
tAW
Address Set-Up to Write End
10
12
12
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
12
ns
tSD
Data Set-Up to Write End
7
8
8
ns
tHD
Data Hold from Write End
0
0
0
ns
3
3
3
ns
tLZWE
tHZWE
WE HIGH to Low
Z[7]
WE LOW to High
Z[6, 7]
6
7
8
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation
is started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05169 Rev. *A
Page 4 of 10
CY7C1049B
Switching Characteristics[4] Over the Operating Range (continued)
7C1049B-20
Parameter
Description
Min.
Max.
7C1049B-25
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the First Access[5]
1
1
1
tRC
Read Cycle Time
20
25
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low
CE HIGH to High
CE LOW to Power-Up
tPD
25
ns
8
10
ns
5
ns
0
3
ns
10
ns
5
ns
8
0
CE HIGH to Power-Down
Write
20
8
Z[6, 7]
tHZCE
ns
0
Z[7]
tPU
25
3
[7]
tHZOE
tLZCE
20
10
ns
0
ns
20
25
ns
Cycle[8]
tWC
Write Cycle Time
20
25
ns
tSCE
CE LOW to Write End
13
15
ns
tAW
Address Set-Up to Write End
13
15
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
13
15
ns
tSD
Data Set-Up to Write End
9
10
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
5
ns
tHZWE
WE LOW to High
Z[6, 7]
8
10
ns
Data Retention Characteristics Over the Operating Range
Parameter
Conditions[11]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
tR[10]
Chip Deselect to Data Retention Time
Max
2.0
Com’l
Ind’l
[3]
Min.
L VCC = VDR = 3.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
Operation Recovery Time
Unit
V
200
µA
1
mA
0
ns
tRC
ns
Notes:
10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
11. No input may exceed VCC + 0.5V.
Document #: 38-05169 Rev. *A
Page 5 of 10
CY7C1049B
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05169 Rev. *A
Page 6 of 10
CY7C1049B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Notes:
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05169 Rev. *A
Page 7 of 10
CY7C1049B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 17
tHD
DATA VALID
tLZWE
tHZWE
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
12
CY7C1049B-12VC
V36
36-Lead (400-Mil) Molded SOJ
15
CY7C1049B-15VC
V36
36-Lead (400-Mil) Molded SOJ
17
20
25
Operating
Range
Commercial
CY7C1049B-15VI
V36
36-Lead (400-Mil) Molded SOJ
Industrial
CY7C1049B-17VC
V36
36-Lead (400-Mil) Molded SOJ
Commercial
CY7C1049BL-17VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049B-17VI
V36
36-Lead (400-Mil) Molded SOJ
Industrial
CY7C1049B-20VC
V36
36-Lead (400-Mil) Molded SOJ
Commercial
CY7C1049BL-20VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049B-20VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BL-20VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049B-25VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BL-25VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049B-25VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BL-25VI
V36
36-Lead (400-Mil) Molded SOJ
Document #: 38-05169 Rev. *A
Industrial
Commercial
Industrial
Page 8 of 10
CY7C1049B
Package Diagram
36-Lead (400-Mil) Molded SOJ V36
51-85090-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05169 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1049B
Document History Page
Document Title: CY7C1049B 512K x 8 Static RAM
Document Number: 38-05169
ECN NO.
Issue
Date
**
110209
12/02/01
SZV
Change from Spec number: 38-00937 to 38-05169
*A
116465
09/16/02
CEA
Add applications foot note to data sheet, page 1.
REV.
Document #: 38-05169 Rev. *A
Orig. of
Change
Description of Change
Page 10 of 10
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