TI ADS8383 18-bit, 500-khz, unipolar input, micropower sampling analog-to-digital converter with parallel interface Datasheet

ADS8383
SLAS005B – DECEMBER 2002 – REVISED MAY 2003
18-BIT, 500-kHz, UNIPOLAR INPUT, MICROPOWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE
FEATURES
D Zero Latency
APPLICATIONS
D Medical Instruments
D Optical Networking
D Transducer Interface
D High Accuracy Data Acquisition Systems
D Magnetometers
D Low Power: 110 mW at 500 kHz
DESCRIPTION
D 500-kHz Sample Rate
D 18-Bit NMC Ensured Over Temperature
D Unipolar Input Range
The ADS8383 is an 18-bit, 500 kHz A/D converter. The
device includes a 18-bit capacitor-based SAR A/D
converter with inherent sample and hold. The ADS8383
offers a full 18-bit interface, a 16-bit option where data is
read using two read cycles or an 8-bit bus option using
three read cycles.
D Onboard Reference Buffer
D High-Speed Parallel Interface
D Wide Digital Supply
D 8-/16-/18-Bit Bus Transfer
The ADS8383 is available in a 48-lead TQFP package and
is characterized over the industrial –40°C to 85°C
temperature range.
D 48-Pin TQFP Package
BUS 18/16
SAR
+IN
–IN
+
_
Output
Latches
and
3-State
Drivers
CDAC
BYTE
18-/16-/8-Bit
Parallel DATA
Output Bus
Comparator
REFIN
Clock
Conversion
and
Control Logic
CONVST
BUSY
CS
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002–2003, Texas Instruments Incorporated
ADS8383
www.ti.com
SLAS005B – DECEMBER 2002 – REVISED MAY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
ADS8383I
ADS8383IB
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
±10
±7
–2~7
2 7
–1~2.5
1 25
NO
MISSING
CODES
RESOLUTION (BIT)
PACKAGE
TYPE
17
48 Pin
TQFP
18
48 Pin
TQFP
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PFB
–40 C to
–40°C
85°C
PFB
–40 C to
–40°C
85°C
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
ADS8383IPFBT
Tape and
reel 250
ADS8383IPFBR
Tape and
reel 1000
ADS8383IBPFBT
Tape and
reel 250
ADS8383IBPFBR
Tape and
reel 1000
NOTE: For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
+IN to AGND
Voltage
Voltage range
+VA + 0.1 V
–IN to AGND
0.5 V
+VA to AGND
–0.3 V to 7 V
+VBD to BDGND
–0.3 V to 7 V
+VA to +VBD
–0.3 V to 2.5 V
Digital input voltage to BDGND
–0.3 V to +VBD + 0.3 V
Digital output voltage to BDGND
–0.3 V to +VBD + 0.3 V
Operating free-air temperature range, TA
–40°C to 85°C
Storage temperature range, Tstg
–65°C to 150°C
Junction temperature (TJ max)
Power dissipation
TQFP package
θJA thermal impedance
Vapor phase (60 sec)
Lead temperature,
temperature soldering
Infrared (15 sec)
150°C
(TJMax – TA)/θJA
86°C/W
215°C
220°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Full-scale input voltage (see Note 1)
+IN – –IN
Absolute input voltage
0
+IN
–0.2
–IN
–0.2
Input capacitance
Input leakage current
Vref
Vref + 0.2
0.2
V
V
45
pF
1
nA
18
Bits
System Performance
Resolution
No missing codes
ADS8383I
(+IN – –IN) < 0.5 FS
18
(+IN – –IN) ≥ 0.5 FS
17
ADS8383IB
Integral linearity (see Notes 2 and 3)
ADS8383I
(+IN – –IN) < 0.125 FS
–4
(+IN – –IN) < 0.5 FS
–6
6
(+IN – –IN) ≥ 0.5 FS
–10
10
ADS8383IB
Differentiallinearity
Differential
linearity
Offset error (see Note 4)
ADS8383I
–7
–2/3
–1
2
(+IN – –IN) < 0.5 FS
–1
3
(+IN – –IN) ≥ 0.5 FS
–2
7
–1
–1/1.4
2.5
ADS8383I
–1
±0.5
1
–0.75
±0.25
0.75
ADS8383IB
ADS8383IB
Vref = 4.096 V
Vref = 4.096 V
–0.1
0.1
–0.06
At 3FFFFh output code
LSB
((18 bit))
7
(+IN – –IN) < 0.125 FS
Noise
Power supply rejection ratio
4
ADS8383IB
ADS8383I
Gain error (see Note 4)
Bits
18
0.06
LSB (18 bit)
mV
%FS
%FS
60
µV RMS
75
dB
Sampling Dynamics
Conversion time
Acquisition time
1.5
Throughput rate
Aperture delay
µs
µs
0.4
500
kHz
4
ns
Aperture jitter
15
ps
Step response
150
ns
150
ns
Over voltage recovery
(1) Ideal input span, does not include gain or offset error.
(2) LSB means least significant bit
(3) This is endpoint INL, not best fit.
(4) Measured relative to an ideal full-scale input (+IN – –IN) of 4.096 V
3
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
SPECIFICATIONS (CONTINUED)
TA = –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic Characteristics
ADS8383I
ADS8383IB
–110
VIN = 4 Vpp at 1 kHz
–112
VIN = 4 Vpp at 10 kHz
–108
ADS8383I
Total harmonic distortion (THD)
((see Note 1))
ADS8383IB
–98
ADS8383I
ADS8383IB
–99
ADS8383I
ADS8383IB
–90
VIN = 4 Vpp at 100 kHz
–91
ADS8383I
ADS8383IB
87
VIN = 4 Vpp at 1 kHz
88
ADS8383I
ADS8383IB
Signal to noise ratio (SNR) (see Note 1)
87
VIN = 4 Vpp at 10 kHz
87
ADS8383I
ADS8383IB
87
87
VIN = 4 Vpp at 100 kHz
87
ADS8383I
ADS8383IB
86
VIN = 4 Vpp at 1 kHz
87
ADS8383I
Signal to noise + distortion (SINAD)
((see Note 1))
ADS8383IB
86
VIN = 4 Vpp at 10 kHz
86
ADS8383I
ADS8383IB
86
85
VIN = 4 Vpp at 100 kHz
85
ADS8383I
ADS8383IB
110
VIN = 4 Vpp at 1 kHz
112
ADS8383I
S urious free dynamic range (SFDR)
Spurious
((see Note 1))
ADS8383IB
98
VIN = 4 Vpp at 10 kHz
108
ADS8383I
ADS8383IB
dB
98
VIN = 4 Vpp at 50 kHz
98
ADS8383I
ADS8383IB
dB
86
VIN = 4 Vpp at 50 kHz
ADS8383I
ADS8383IB
dB
87
VIN = 4 Vpp at 50 kHz
ADS8383I
ADS8383IB
dB
–98
VIN = 4 Vpp at 50 kHz
90
VIN = 4 Vpp at 100 kHz
94
–3dB Small signal bandwidth
3
MHz
Voltage Reference Input
Reference voltage at REFIN, Vref
2.5
Reference resistance (see Note 2)
Reference current drain
4.096
4.2
500
fs = 500 kHz
V
kΩ
1
mA
Bias Input
Bias input range
2
2.048
Bias input drift
Bias input current, sink
(1) Calculated on the first nine harmonics of the input frequency
(2) Can vary ±20%
4
–150
–100
2.1
V
±5
%FS
µA
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
SPECIFICATIONS (CONTINUED)
TA = –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Input/Output
Logic family
Logic level
CMOS
VIH
VIL
IIH = 5 µA
IIL = 5 µA
VOH
VOL
IOH = 2 TTL loads
IOL = 2 TTL loads
+VBD–1
+VBD + 0.3
0.8
–0.3
V
+VBD – 0.6
0.4
Straight
Binary
Data format
Power Supply Requirements
Power supply voltage
+VBD (see Notes 1 and 2)
2.95
+VA (see Note 2)
4.75
Supply current, 500-kHz sample rate (see Note 3)
Power dissipation, 500-kHz sample rate (see Note 3)
3.3
5.25
V
5
5.25
22
26
mA
V
110
130
mW
85
°C
Temperature Range
Operating free-air
–40
(1) The difference between +VA and +VBD should be no less than 2.3 V, i.e. if +VA is 5.5 V, +VBD should be at least 2.95 V.
(2) +VBD ≥ +VA – 2.3 V
(3) This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins.
5
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)
PARAMETER
MIN
TYP
MAX
1.5
UNIT
µs
tCONV
tACQ
Conversion time
Acquisition time
0.4
tpd1
tpd2
CONVST low to conversion started (BUSY high)
10
50
ns
Propagation delay time, End of conversion to BUSY low
10
20
ns
tw1
tsu1
Pulse duration, CONVST low
40
ns
Setup time, CS low to CONVST low
20
ns
tw2
Pulse duration, CONVST high
20
CONVST falling edge jitter
tw3
tw4
th1
Pulse duration, BUSY signal low
Min(tACQ)
Pulse duration, BUSY signal high
Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE or
BUS18/16 input changes) after CONVST low
µs
ns
10
ps
1
µs
1.52
µs
40
ns
0
ns
0
ns
50
ns
td1
tsu2
Delay time, CS low to RD low
tw5
ten
Pulse duration, RD low time
td2
td3
Delay time, data hold from RD high
tw6
th2
RD high
tpd4
td4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge
tsu3
th3
tdis
Disable time, RD High (CS high for read cycle) to 3-stated data bus
20
ns
td5
Delay time, BUSY low to MSB data valid
30
ns
20
µs
Setup time, RD high to CS high
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
20
5
10
ns
20
ns
20
ns
125
ns
Max(td5)
0
ns
Setup time, BYTE or BUS18/16 rising edge to RD falling edge
10
ns
Hold time, BYTE or BUS18/16 falling edge to RD falling edge
10
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
Delay time, BYTE edge to BUS18/16 edge skew
tsu4
Setup time, BYTE or BUS18/16 change before BUSY falling edge
10
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
6
ns
ns
ns
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3)
PARAMETER
MIN
TYP
MAX
1.5
UNIT
µs
tCONV
tACQ
Conversion time
Acquisition time
0.4
tpd1
tpd2
CONVST low to conversion started (BUSY high)
10
50
ns
Propagation delay time, end of conversion to BUSY low
10
20
ns
tw1
tsu1
Pulse duration, CONVST low
40
ns
Setup time, CS low to CONVST low
20
ns
tw2
Pulse duration, CONVST high
20
CONVST falling edge jitter
Min(tACQ)
µs
ns
10
ps
1
µs
1.52
µs
tw3
tw4
Pulse duration, BUSY signal low
th1
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS
18/16 input changes) after CONVST low
td1
tsu2
Delay time, CS low to RD low
tw5
ten
Pulse duration, RD low
td2
td3
Delay time, data hold from RD high
10
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
10
tw6
th2
Pulse duration, RD high time
tpd4
td4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge
tsu3
th3
Setup time, BYTE or BUS18/16 rising edge to RD falling edge
Hold time, BYTE or BUS18/16 falling edge to RD falling edge
10
tdis
Disable time, RD High (CS high for read cycle) to 3-stated data bus
30
ns
td5
Delay time, BUSY low to MSB data valid delay time
40
ns
30
µs
Pulse duration, BUSY signal high
Setup time, RD high to CS high
40
ns
0
ns
0
ns
50
ns
Enable time, RD low (or CS low for read cycle) to data valid
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
Delay time, BYTE edge to BUS18/16 edge skew
30
ns
ns
30
ns
20
ns
125
ns
Max(td5)
ns
0
ns
10
ns
tsu4
Setup time, BYTE or BUS18/16 change before BUSY falling edge
10
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timing are measured with 10 pF equivalent loads on all data bits and BUSY pins.
ns
7
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
PIN ASSIGNMENTS
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
BDGND
PFB PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
3
4 5
6 7 8
13
9 10 11 12
REFIN
BIAS
NC
+VA
AGND
+IN
–IN
AGND
+VA
+VA
1 2
NC – No connection.
8
AGND
AGND
+VBD
BUS18/16
BYTE
CONVST
RD
CS
+VA
AGND
AGND
+VA
REFM
REFM
+VBD
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
AGND
AGND
+VA
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
TERMINAL FUNCTIONS
NAME
NO.
I/O
5, 8, 11,
12, 14, 15,
44, 45
–
Analog ground
BDGND
25
–
Digital ground for bus interface digital supply
BIAS
2
I
Bias to internal circuit
BUSY
36
O
Status output. High when a conversion is in progress.
BUS18/16
38
I
Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer.
0: Data bits output on the 18-bit data bus pins DB[17:0].
1: Last two data bits D[1:0] from 18-bit wide bus output on:
a) the low byte pins DB[9:2] if BYTE = 0
b) the high byte pins DB[17:10] if BYTE = 1
BYTE
39
I
Byte select input. Used for 8-bit bus reading.
0: No fold back
1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant
pins DB[17:10].
CONVST
40
I
Convert start
CS
42
I
Chip select
AGND
DESCRIPTION
8-Bit Bus
BYTE = 0
Data Bus
BYTE = 1
16-Bit Bus
BYTE = 1
BYTE = 0
BYTE = 0
18-Bit Bus
BYTE = 0
BUS18/16 = 0
BUS18/16 = 0
BUS18/16 = 1
BUS18/16 = 0
BUS18/16 = 1
BUS18/16 = 0
DB17
16
O
D17 (MSB)
D9
All ones
D17 (MSB)
All ones
D17 (MSB)
DB16
17
O
D16
D8
All ones
D16
All ones
D16
DB15
18
O
D15
D7
All ones
D15
All ones
D15
DB14
19
O
D14
D6
All ones
D14
All ones
D14
DB13
20
O
D13
D5
All ones
D13
All ones
D13
DB12
21
O
D12
D4
All ones
D12
All ones
D12
DB11
22
O
D11
D3
D1
D11
All ones
D11
DB10
23
O
D10
D2
D0(LSB)
D10
All ones
D10
DB9
26
O
D9
All ones
All ones
D9
All ones
D9
DB8
27
O
D8
All ones
All ones
D8
All ones
D8
DB7
28
O
D7
All ones
All ones
D7
All ones
D7
DB6
29
O
D6
All ones
All ones
D6
All ones
D6
DB5
30
O
D5
All ones
All ones
D5
All ones
D5
DB4
31
O
D4
All ones
All ones
D4
All ones
D4
DB3
32
O
D3
All ones
All ones
D3
D1
D3
DB2
33
O
D2
All ones
All ones
D2
D0 (LSB)
D2
DB1
34
O
D1
All ones
All ones
D1
All ones
D1
DB0
35
O
D0 (LSB)
All ones
All ones
D0 (LSB)
All ones
D0 (LSB)
–IN
7
I
Inverting input channel
+IN
6
I
Noninverting input channel
NC
3
–
No connection
REFIN
1
I
Reference input.
REFM
47, 48
I
Reference ground.
RD
41
I
Synchronization pulse for the parallel output.
+VA
4, 9, 10,
13, 43, 46
–
Analog power supplies, 5-V dc
24, 37
–
Digital power supply for bus
+VBD
9
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
TIMING DIAGRAMS
tw2
tw1
CONVST
tpd1
tpd2
tw4
tw3
BUSY
tsu1
CS
CONVERT†
t(CONV)
t(CONV)
SAMPLING†
(When CS Toggle)
t(ACQ)
BYTE
th1
BUS 18/16
tsu2
tpd4
th2
td1
RD
tdis
ten
DB[17:12]
Hi–Z
MSB
Hi–Z
D[17:12] D[9:4]
DB[11:10]
Hi–Z
Hi–Z
D[11:10] D[3:2] D[1:0]
DB[9:0]
Hi–Z
Hi–Z
D[9:0]
†Signal internal to device
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
10
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
tw1
tw2
CONVST
tpd1
tpd2
tw4
tw3
BUSY
tsu1
CS
CONVERT†
t(CONV)
t(CONV)
SAMPLING†
(When CS Toggle)
t(ACQ)
BYTE
th1
BUS 18/16
tpd4
th2
RD = 0
ten
DB[17:12]
Hi–Z
tdis
MSB
Hi–Z
D[17:12] D[9:4]
DB[11:10]
Hi–Z
Hi–Z
D[11:10] D[3:2] D[1:0]
DB[9:0]
Hi–Z
Hi–Z
D[9:0]
†Signal internal to device
NOTE: RD cannot be tied to BDGND. Three read cycles are required at power on.
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Held at BDGND After
Power-On Initialization
11
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
tw1
tw2
CONVST
tpd1
tpd2
tw4
tw3
BUSY
CS = 0
CONVERT†
t(CONV)
t(CONV)
t(ACQ)
SAMPLING†
(When CS = 0)
BYTE
th1
BUS 18/16
tpd4
th2
RD
tdis
ten
DB[17:12]
Hi–Z
MSB
Hi–Z
D[17:12] D[9:4]
DB[11:10]
Hi–Z
Hi–Z
D[11:10] D[3:2] D[1:0]
DB[9:0]
Hi–Z
Hi–Z
D[9:0]
†Signal internal to device
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
12
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
tw2
tw1
CONVST
tpd1
tpd2
tw4
tw3
BUSY
CS = 0
CONVERT†
t(CONV)
t(CONV)
t(ACQ)
SAMPLING†
(When CS = 0)
BYTE
BUS 18/16
RD = 0
th1
th1
td5
D[9:4]
DB[17:12]
Next D[17:12]
D[17:12]
DB[11:10]
D[11:10] D[3:2]
D[1:0]
Next D[11:10]
DB[9:0]
D[9:0]
Next D[9:0]
†Signal internal to device
NOTE: RD cannot be tied to BDGND. Three read cycles are required at power on.
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Held at BDGND After Power-On
Initialization - Auto Read
13
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
CS
RD
BYTE
BUS 18/16
ten
ten
DB[17:0]
Hi–Z
tdis
Valid
Hi–Z
td3
tdis
td3
Valid
Valid
Figure 5. Detailed Timing for Read Cycles
14
Hi–Z
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
TYPICAL CHARACTERISTICS†
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
HISTOGRAM (DC Code Spread)
HALF SCALE 131071 CONVERSIONS
18000
87.9
+VA = 5 V,
+VBD = 3 V
Code = 131046
14000
12000
10000
8000
6000
4000
87.7
87.6
87.5
87.4
87.3
2000
87.2
–40
131064
131046
0
131027
+VA = 5 V,
+VBD = 3 V
87.8
SNR – Signal-to-Noise Ratio – dB
16000
–25
SIGNAL-TO-NOISE + DISTORTION
vs
FREE-AIR TEMPERATURE
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
87.9
116
+VA = 5 V,
+VBD = 3 V
87.8
SFDR – Spurious Free Dynamic Range – dB
SINAD– Signal-To-Noise + Distortion – dB
80
Figure 7
Figure 6
87.7
87.6
87.5
87.4
87.3
87.2
–40
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
–25
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
Figure 8
80
+VA = 5 V,
+VBD = 3 V
115
114
113
112
111
110
109
108
107
106
–40
–25
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
80
Figure 9
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
15
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
14.31
+VA = 5 V,
+VBD = 3 V
–105
ENOB – Effective Number of Bits – Bits
THD – Total Harmonic Distortion – dB
–104
–106
–107
–108
–109
–110
–111
–40
14.29
14.28
14.27
14.26
14.25
14.24
14.23
14.22
14.21
–25
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
14.20
–40
80
–25
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE + DISTORTION
vs
INPUT FREQUENCY
87.26
89.0
87.25
87.24
SINAD– Signal-To-Noise + Distortion – dB
+VA = 5 V,
+VBD = 3 V
87.23
87.22
87.21
87.20
87.19
87.18
87.17
87.16
87.15
0
20
40
60
fi – Input Frequency – kHz
Figure 12
80
100
+VA = 5 V,
+VBD = 3 V
88.5
88.0
87.5
87.0
86.5
86.0
85.5
85.0
0
20
40
60
80
fi – Input Frequency – kHz
Figure 13
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
16
80
Figure 11
Figure 10
SNR – Signal-to-Noise Ratio – dB
+VA = 5 V,
+VBD = 3 V
14.30
100
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
120
+VA = 5 V,
+VBD = 3 V
14.20
ENOB – Effective Number of Bits – Bits
SFDR – Spurious Free Dynamic Range – dB
14.25
14.15
14.10
14.05
14.00
13.95
13.90
+VA = 5 V,
+VBD = 3 V
115
110
105
100
95
90
13.85
0
20
40
60
fi – Input Frequency – kHz
80
0
100
40
60
80
fi – Input Frequency – kHz
100
Figure 15
Figure 14
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
SUPPLY CURRENT
vs
SAMPLE RATE
–80
19
+VA = 5 V,
+VBD = 3 V
–85
+VA = 5 V,
Current of +VA only
18
–90
Supply Current – mA
THD – Total Harmonic Distortion – dB
20
–95
–100
–105
17
16
15
–110
–115
0
20
40
60
80
fi – Input Frequency – kHZ
Figure 16
100
14
125
250
375
Sample Rate – KSPS
500
Figure 17
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
17
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
INTEGRAL NONLINEARITY
vs
SAMPLE RATE
DIFFERENTIAL NONLINEARITY
vs
SAMPLE RATE
3.0
1.50
2.5
1.25
1.5
DNL – Differential Nonlinearity – LSB
INL – Integral Nonlinearity – LSB
2.0
Max
1.0
0.5
+VA = 5 V,
TA = 25 °C
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
Min
–3.0
+VA = 5 V,
TA = 25 °C
0.75
0.50
0.25
0.00
–0.25
–0.50
Min
–0.75
–3.5
–4.0
125
Max
1.00
200
275
350
425
Sample Rate – KSPS
–1.00
125
500
Figure 18
200
275
350
425
Sample Rate – KSPS
500
Figure 19
OFFSET VOLTAGE
vs
SUPPLY VOLTAGE
GAIN ERROR
vs
SUPPLY VOLTAGE
–0.30
0
–0.32
TA = 25 °C
–2
–0.002
Offset Voltage – mV
Gain Error – %FS
–0.34
–0.004
–4
–0.006
–6
–0.008
–8
–0.36
–0.38
–0.40
–0.42
–0.44
–0.010
–10
–0.46
–0.012
–12
4.75
5.00
+VA – Supply Voltage – V
Figure 20
5.25
–0.48
4.75
5.00
+VA – Supply Voltage – V
Figure 21
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
18
5.25
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
GAIN ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
–0.01
20.0
TA = 25 °C,
Current of +VA only
19.5
19.0
Gain Error – %FS
Supply Current – mA
Vref = 4.1 V
18.5
18.0
–0.02
Vref = 2.5 V
17.5
17.0
4.75
5.00
+VA – Supply Voltage – V
–0.03
–40
5.25
–20
0
20
40
60
80
TA – Free-Air Temperature – °C
Figure 23
Figure 22
OFFSET VOLTAGE
vs
TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
–0.20
18.14
Vref = 4.096 V
+VA = 5 V,
TA = 25 °C
–0.22
+VA = 5 V
18.12
Supply Current – mA
Offset Voltage – mV
18.10
–0.24
–0.26
–0.28
18.08
18.06
18.04
18.02
18.00
–0.30
Vref = 2.5 V
–0.32
–40
–25
–10
5
20
35
50
TA – Temperature – °C
Figure 24
17.98
65
80
17.96
–40
–20
0
20
40
60
TA – Temperature – °C
80
Figure 25
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
19
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
DIFFERENTIAL NONLINEARITY (Min)
vs
TEMPERATURE
DIFFERENTIAL NONLINEARITY (Max)
vs
TEMPERATURE
–0.60
1.7
DNL – Differential Nonlinearity (min) – LSB
DNL – Differential Nonlinearity (max) – LSB
1.8
+VA = 5 V,
TA = 25 °C
Max
1.6
1.5
1.4
1.3
1.2
–40
–25
–10
5
20
35
50
TA – Temperature – °C
65
–0.65
–0.70
–0.75
–0.80
Min
–0.85
–0.90
–0.95
–1.00
–40
80
+VA = 5 V,
TA = 25 °C
–25
INTEGRAL NONLINEARITY (Max)
vs
TEMPERATURE
+VA = 5 V,
TA = 25 °C
INL – Integral Nonlinearity (min) – LSB
INL – Integral Nonlinearity (max) – LSB
–2.0
Max
3.5
3.0
2.5
–25
–10
5
20
35
50
TA – Temperature – °C
Figure 28
65
80
–2.2
+VA = 5 V,
TA = 25 °C
–2.4
–2.6
–2.8
Min
–3.0
–3.2
–3.4
–3.6
–40
–25
–10
5
20
35
50
TA – Temperature – °C
Figure 29
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
20
80
INTEGRAL NONLINEARITY (Min)
vs
TEMPERATURE
4.5
2.0
–40
65
Figure 27
Figure 26
4.0
–10
5
20
35
50
TA – Temperature – °C
65
80
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
OFFSET VOLTAGE
vs
REFERENCE VOLTAGE
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
–0.20
5
–0.22
Max
3
–0.24
2
Offset Voltage – mV
INL – Integral Nonlinearity – LSB
4
1
+VA = 5 V
0
–1
–2
Min
+VA = 5 V,
TA = 25 °C
–0.26
–0.28
–0.30
–0.32
–0.34
–3
–0.36
–4
–0.38
–5
–6
2.0
2.5
3.0
3.5
4.0
–0.40
2.5
4.5
Vref – Reference Voltage – V
Figure 30
3.0
3.5
Vref – Reference Voltage – V
4.0
Figure 31
DIFFERENTIAL NONLINEARITY
vs
REFERENCE VOLTAGE
5
DNL – Differential Nonlinearity – LSB
+VA = 5 V
4
Max
3
2
1
0
Min
–1
–2
2.0
2.5
3.0
3.5
4.0
Vref – Reference Voltage – V
4.5
Figure 32
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
21
ADS8383
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DNL – Differential Linearity Error – LSBs
SLAS005B – DECEMBER 2002 – REVISED MAY 2003
DIFFERENTIAL LINEARITY ERROR
vs
CODE
3
2.5
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
–2.5
–3
0
65536
196605
131072
262144
Code
Figure 33
INL – Integral Linearity Error – LSBs
INTEGRAL LINEARITY ERROR
vs
CODE
7
5
3
1
–1
–3
–5
–7
0
65536
131072
196608
262144
Code
Figure 34
FFT SPECTRAL RESPONSE (100 kHz Input)
0
–20
16384 Points, fs = 500 kHz,
(+IN – –IN) = 4 VP-P
Amplitude – dB
–40
–60
–80
–100
–120
–140
–160
–180
0
50000
100000
150000
200000
f – Frequency – Hz
Figure 35
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
22
250000
ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
FFT SPECTRAL RESPONSE (50 kHz Input)
0
–20
Amplitude – dB
–40
16384 Points, fs = 500 kHz,
(+IN – –IN) = 4 VP-P
–60
–80
–100
–120
–140
–160
–180
0
50000
100000
150000
200000
250000
f – Frequency – Hz
Figure 36
† At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and fsample = 500 kHz (unless otherwise noted)
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ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8383 to 8-Bit Microcontroller Interface
Figure 37 shows a parallel interface between the ADS8383 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microprocessor.
Analog 5 V
0.1 µF
AGND
10 µF
Ext Ref Input
0.1 µF
Micro
Controller
GPIO
GPIO
GPIO
GPIO
RD
AD[7:0]
–IN
+IN
+VA
REFIN
REFM
AGND
Analog Input
Ext Bias Voltage
BIAS
1 µF
Digital 3 V
Data Bus D[17:0]
CS
AD8383
BYTE
BUS18/16
CONVST
RD
DB[17:10]
AGND
0.1 µF
BDGND
BDGND
+VBD
Figure 37. ADS8383 Application Circuitry
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ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
PRINCIPLES OF OPERATION
The ADS8383 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 37 for
the application circuit for the ADS8383.
The conversion clock is generated internally. The conversion time of 1.6 µs is capable of sustaining a 500-kHz
throughput.
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on
these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected
from any internal function.
REFERENCE
The ADS8383 can operate with an external 4.096-V reference for a corresponding full-scale range of 4.096 V.
BIASING THE ADS8383
The ADS8383 requires an external 2.048-V bandgap reference to generate the bias currents for internal circuitry.
Figure 38 shows the internal circuitry used to generate the bias currents. The bias generation circuit also pumps
100 µA (150 µA max) out from the BIAS pin. The bandgap used should be capable of sinking 100 µA (150 µA max)
while holding the voltage on the pin steady. Table 1 shows the specification of the bandgap used to drive the BIAS
pin of the ADS8383.
5V
+VA
ADS8383
100 µA
BIAS_INT
BIAS
AGND
Figure 38. Bias Current Generation
Table 1. Bias Specifications
PARAMETER
MIN
TYP
Output Voltage
2
2.048
2.1
V
100
150
µA
Isink
MAX
UNITS
Any common bandgap like REF3020 can be used to drive the BIAS pin of the ADS8383. Figure 39 shows how
REF3020 can be used with the ADS8383. A 1 µF decoupling capacitor is recommended between pins 2 and AGND
of the ADS8383 for optimal performance.
5V
1
0.47 µF
50 Ω
REF3020
2
3
2
22 µF
ADS8383
AGND
AGND
Figure 39. Using the REF3020 to Drive the ADS8383 BIAS Pin
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ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the
internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to reject
small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V.
The input span (+IN – (–IN)) is limited to 0 V to Vref.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8383 charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage
must be able to charge the input capacitance (45 pF) to an 18-bit settling level within the acquisition time (400 ns)
of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN
and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters
should be used.
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched.
If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and
linearity error which changes with temperature and input voltage.
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their requirements.
The ADS8383 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8383 switches from the
sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal
is important to the performance of the converter. The BUSY output is brought high immediately following CONVST
going low. BUSY stays high through the conversion process and returns low when the conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when
BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST
goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus
with the conversion.
Reading Data
The ADS8383 outputs full parallel data in straight binary format as shown in Table 2. The parallel output is active when
CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 125
ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this
zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16 are used for
multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus.
BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the higher 16-bit bus. Refer
to Table 2 for ideal output codes.
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ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
Table 2. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
FULL SCALE RANGE
Vref
Vref/262144
Least significant bit (LSB)
Full scale
Midscale
Midscale – 1 LSB
Zero
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
HEX CODE
Vref – 1 LSB
Vref/2
11 1111 1111 1111 1111
3FFFF
10 0000 0000 0000 0000
20000
Vref/2 – 1 LSB
0V
01 1111 1111 1111 1111
1FFFF
00 0000 0000 0000 0000
00000
The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are low.
The result may also be read on a 16-bit bus by using only pins DB17–DB2. In this case two reads are necessary:
the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits (D17–D2) on pins
DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high, the lower two bits
(D1–D0) appear on pins DB3–DB2.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In this
case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8 most
significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is high, the
medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high while holding
BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The last read cycle
is not necessary if only the first 16 most significant bits are of interest.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for
simplicity. This is referred to as the AUTO READ operation. Note that RD may not be tied to BDGND permanently
due to the requirement of power-on initialization.
Table 3. Conversion Data Read Out
DATA READ OUT
BYTE
BUS18/16
DB17–DB12
DB11–DB10
DB9–DB4
DB3–DB2
DB1–DB0
High
High
All One’s
D1–D0
All One’s
All One’s
All One’s
Low
High
All One’s
All One’s
All One’s
D1–D0
All One’s
High
Low
D9–D4
D3–D2
All One’s
All One’s
All One’s
Low
Low
D17–D12
D11–D10
D9–D4
D3–D2
D1–D0
POWER-ON INITIALIZATION
At first power on there are three read cycles required (RD must be toggled three times). If conversion cycle is
attempted before these intialization read cycles, the first three conversion cycles will not produce valid results. This
is used to load factory trimming data for a specific device to assure high accuracy of the converter. Because of this
requirement, the RD pin cannot be tied permanently to BDGND. System designers can still achieve the AUTO READ
function if the power-on requirement is satisfied.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8383 circuitry.
As the ADS8383 offers single-supply operation, it will often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the
higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any
single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages
can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,
or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external
event.
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ADS8383
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SLAS005B – DECEMBER 2002 – REVISED MAY 2003
On average, the ADS8383 draws very little current from an external reference as the reference voltage is internally
buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1 (REFIN) directly
to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog
ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor.
If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists
of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from
the connection for digital logic until they are connected at the power entry point. Power to the ADS8383 should be
clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible.
See Table 4 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some
situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up
of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency
noise.
Table 4. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
SUPPLY PINS
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
Pin pairs that require shortest path to decoupling capacitors
(4,5), (8,9), (10,11), (13,15),
(43,44), (45,46)
(24,25)
Pins that require no decoupling
12, 14
37
28
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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