IDT IDT70V657S12DRI High-speed 3.3v 128/64/32k x 36 asynchronous dual-port static ram Datasheet

HIGH-SPEED 3.3V
IDT70V659/58/57S
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
Features
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
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Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
R/WL
R/W R
B
E
0
L
CE0L
CE1L
B
E
1
L
B
E
2
L
B
E
3
L
BBBB
EEEE
3 2 10
RRRR
CE0R
CE1R
OEL
OER
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
128/64/32K x 36
MEMORY
ARRAY
I/O0L- I/O35L
A16 L(1)
A0L
Di n_L
Address
Decoder
Di n_R
ADDR_L
CE0L
CE1L
OEL
R/WL
BUSYL(2,3)
SEML
INTL(3)
I/O0R -I/O35R
Address
Decoder
ADDR_R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OER
JTAG
A0R
CE0R
CE1R
R/WR
BUSYR(2,3)
SEMR
INTR(3)
M/S
TDI
TDO
A16R(1)
TMS
TCK
TRST
NOTES:
1. A16 is a NC for IDT70V658. Also, Addresses A 16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4869 drw 01
MARCH 2004
1
©2004 Integrated Device Technology, Inc.
DSC-4869/5
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Description
The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchronous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used
as a stand-alone 4/2/1Mbit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
Industrial and Commercial Temperature Ranges
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The 70V659/58/57 can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controlled by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
2
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(3,4,5,6,7,8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70V659/58/57DR
DR-208(7)
208-Pin PQFP
Top View(8)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
VSS
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS
VDDQR
I/O18R
I/O18L
VSS
VDD
TDI
TDO
NC
NC
NC
A16L(1)
A15L(2)
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
BE3L
BE2L
BE1L
BE0L
CE1L
CE0L
VDD
VDD
VSS
VSS
SEML
OEL
R/WL
BUSYL
INTL
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
VDD
VSS
OPTL
I/O17L
I/O17R
VDDQR
VSS
03/19/04
I/O16L
I/O16R
I/O15L
I/O15R
VSS
VDDQL
I/O14L
I/O14R
I/O13L
I/O13R
VSS
VDDQR
I/O12L
I/O12R
I/O11L
I/O11R
VSS
VDDQL
I/O10L
I/O10R
I/O9L
I/O9R
VSS
VDDQR
VDD
VDD
VSS
VSS
VSS
VDDQL
I/O8R
I/O8L
I/O7R
I/O7L
VSS
VDDQR
I/O6R
I/O6L
I/O5R
I/O5L
VSS
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
VSS
VDDQL
I/O35R
I/O35L
VDD
TMS
TCK
TRST
NC
NC
NC
A16R(1)
A15R(2)
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
BE3R
BE2R
BE1R
BE0R
CE1R
CE0R
VDD
VDD
VSS
VSS
SEMR
OER
R/WR
BUSYR
INTR
M/S
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
VSS
VSS
OPTR
I/O0L
I/O0R
VDDQL
VSS
4869 drw 02a
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All VDD pins must be connected to 3.3V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground.
6. Package body is approximately 28mm x 28mm x 3.5mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
3
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
,5,6,7,8
,5,6,7,8)
Pin Configurations(3,4,5,6,7,8
(con't.)
70V659/58/57BC
BC-256(7)
256-Pin BGA
Top View(8)
03/19/04
A1
NC
B1
I/O18L
C1
A2
TDI
B2
NC
C2
I/O18R I/O19L
D1
D2
A3
NC
B3
TDO
C3
VSS
D3
I/O20R I/O19R I/O20L
E1
E2
E3
A4
NC
B4
NC
C4
A5
A6
A14L
A11L
B5
C5
A16L(1) A13L
D4
VDD
E4
D5
F2
F3
F4
E5
F5
I/O23L I/O22R I/O23R VDDQL V DD
G1
G2
G3
G4
G5
I/O24R I/O24L I/O25L VDDQR VSS
H1
H2
H3
H4
H5
I/O26L I/O25R I/O26R VDDQR VSS
J1
J2
J3
J4
I/O27L I/O28R I/O27R VDDQL
K1
K2
K3
K4
J5
VSS
K5
I/O29R I/O29L I/O28L VDDQL VSS
L1
L2
L3
L4
L5
I/O30L I/O31R I/O30R VDDQR VDD
M1
M2
M3
M4
I/O32R I/O32L I/O31L VDDQR
N1
N2
N3
N4
I/O33L I/O34R I/O33R VDD
P1
P2
P3
P4
M5
VDD
I/O35L
T1
NC
R2
NC
T2
TCK
R3
TRST
T3
NC
R4
A10L
D6
N5
E6
VDD
F6
VSS
G6
VSS
H6
VSS
J6
VSS
K6
V SS
L6
VSS
M6
VDD
N6
P5
R5
P6
A 10R
R6
NC A 15R(2) A12R
T4
NC
B7
A9L
C7
A7L
D7
A8
BE2L
B8
BE3L
C8
A9
CE1L
B9
A10
OE L
B10
CE0L R/WL
C9
C10
A11
INTL
B11
NC
C11
BE1L BE0L SEML BUSYL
D8
D9
D10
D11
A12
A5L
B12
A4L
C12
A6L
D12
E7
VSS
F7
VSS
G7
V SS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
F8
VSS
F9
VSS
VSS
G8
G9
V SS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
M8
VSS
M9
VSS
N8
VSS
N9
E10
V SS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
V SS
L10
VSS
M10
VSS
N10
E11
VDD
F11
V SS
G11
V SS
H11
VSS
J11
VSS
K11
V SS
L11
VSS
M11
VDD
N11
E12
A13
A 2L
B13
A 1L
C13
A 3L
D13
A14
A0L
B14
NC
C14
A15
NC
B15
I/O17L
C15
A16
NC
B16
NC
C16
OPTL I/O17R I/O16L
D14
D15
D16
T5
A14R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
P10
P11
BE1R BE0R SEMR BUSYR
R8
R9
R10
BE3R CE0R R/WR
T8
T9
BE2R CE1R
T10
OER
R11
M/S
T11
INTR
E13
E14
E15
E16
VDD VDDQR I/O13L I/O14L I/O14R
F12
F13
F14
F15
F16
V DD VDDQR I/O12R I/O13R I/O12L
G12
V SS
H12
VSS
J12
G13
G14
G15
G16
V DDQL I/O10L I/O11L I/O11R
H13
H14
V DDQL I/O9R
J13
J14
H15
H16
IO9L I/O10R
J15
J16
VSS VDDQR I/O8R I/O7R I/O8L
K12
V SS
L12
VDD
M12
K13
K14
K15
K16
VDDQR I/O6R I/O6L I/O7L
L13
L14
VDDQL I/O5L
M13
M14
L15
L16
I/O4R I/O5R
M15
M16
V DD VDDQL I/O3R I/O3L I/O4L
N12
VDDQR VDDQR V DDQL VDDQL VDDQR VDDQR V DDQL VDDQL
I/O35R I/O34L TMS A16R(1) A13R
R1
C6
A8L
VDDQL VDDQL VDDQR VDDQR V DDQL VDDQL V DDQR VDDQR VDD I/O15R I/O15L I/O16R
I/O21R I/O21L I/O22L VDDQL VDD
F1
B6
A15L(2) A12L
A7
P12
A6R
R12
A4R
T12
A5R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
I/O2L
P14
N15
P15
I/O0L I/O0R
R14
OPTR
T14
A0R
N16
I/O1R I/O2R
R15
NC
T15
NC
P16
I/O1L
R16
NC
,
T16
NC
4869 drw 02c
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All VDD pins must be connected to 3.3V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
4
,
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(3,4,5,6,7,8) (con't.)
03/19/04
1
2
3
4
5
6
7
8
9
10 11
12
13 14
15
16 17
A
A
I/O19L
I/O 18L
VSS
TDO
NC
A16L(1)
A 12L
A 8L
BE1L
VDD
SEML
INTL
A4L
A0L
OPTL
I/O 17L
B
I/O 20R
VS S
I/O18R
TDI
NC
A 13L
A9L
BE2L
CE0L
V SS
BUSYL
A5L
A 1L
VSS
VDDQR
I/O16L I/O 15R
C
V DDQL
I/O19R
V DDQR
V DD
NC
A 14L
A10L
BE3L
CE1L
V SS
R/W L
A6L
A2L
VDD
I/O 16R
I/O15L
VSS
C
D
I/O 22L
VSS
I/O21L
I/O 20L
A7L
BE0L
V DD
OEL
NC
A 3L
VDD
I/O 17R
VDDQL
I/O14L
I/O 14R
D
E
I/O 23L
I/O22R
VDDQR I/O 21R
I/O 12L
I/O13R
V SS
I/O 13L
E
F
VDDQL
I/O23R
I/O24L
VSS
VSS
I/O12R
I/O11L
VDDQR
F
G
I/O 26L
VSS
I/O25L
I/O 24R
I/O9L
V DDQL
I/O 10L
I/O 11R
G
VDD
I/O 9R
VSS
I/O10R
H
VS S
VDD
VSS
V DDQR
J
I/O 7R
VDDQL
I/O8R
V SS
K
I/O 8L
L
A 15L (2) A 11L
70V659/58/57BF
BF-208(7)
VSS
B
H
VDD
I/O26R
J
VDDQL
VDD
VSS
VSS
K
I/O28R
VSS
I/O2 7R
VS S
L
I/O 29R
I/O28L
VDDQR
I/O 27L
I/O 6R
I/O 7L
V SS
M
V DDQL
I/O29L
I/O 30R
VSS
VSS
I/O 6L
I/O5R
VDDQR
M
N
I/O 31L
VS S
I/O31R
I/O 30L
I/O 3R
VD DQL
I/O 4R
I/O5L
N
P
I/O32R
I/O32L
VDDQR I/O 35R
R
VSS
I/O33L
I/O34 R
T
I/O 33R
I/O34L
U
VS S
I/O35L
V DDQR I/O 25R
208-Ball BGA
Top View(8)
TRST
A16R (1 )
A 12R
A 8R
BE1R
V DD
SEM R
INTR
A 4R
I/O2L
I/O 3L
V SS
I/O 4L
P
TCK
NC
A13R
A9R
BE2R
CE0R
VS S
BUSYR
A5R
A1R
V SS
VDDQL
I/O 1R
VDDQR
R
VDDQL
TMS
NC
A14R
A10R
BE3R
CE1R
VSS
R/ WR
A6R
A2R
VS S
I/O 0R
VS S
I/O2R
T
VDD
NC
A15R (2) A 11R
A7R
BE0R
VDD
OER
M/ S
A 3R
A0R
VDD
OPT R
I/O 0L
I/O1L
U
4869 drw 02b
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All VDD pins must be connected to 3.3V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
5
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables - (Input)
R/WL
R/WR
Read/Write Enable - (Input)
Output Enable - (Input)
OER
OEL
(3)
(3)
A0L - A16L
A0R - A16R
Address - (Input)
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
SEML
SEMR
Semaphore Enable - (Input)
INTL
INTR
Interrupt Flag - (Output)
BUSYL
BUSYR
Busy Flag - (Output)(4)
BE0L - BE3L
BE0R - BE3R
Byte Enables (9-bit bytes) - (Input)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V) - (Input)(1)
OPTL
OPTR
Option for selecting V DDQX - (Input)(1,2)
M/S
Master or Slave Select - (Input)
VDD
Power (3.3V) - (Input)(1)
VSS
Ground (0V) - (Input)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
3. Addresses A16 x is a NC for IDT70V658. Also, Addresses A16x and A15 x are
NC's for IDT70V657.
4. BUSY is an input as a slave (M/S = VIL).
4869 tbl 01
6
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2)
OE
SEM
CE0
CE1
BE3
BE2
BE1
BE0
R/W
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X
H
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
H
X
L
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
H
L
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
H
L
H
H
H
H
L
L
High-Z
High-Z
High-Z
DIN
Write to Byte 0 Only
X
H
L
H
H
H
L
H
L
High-Z
High-Z
DIN
High-Z
Write to Byte 1 Only
X
H
L
H
H
L
H
H
L
High-Z
DIN
High-Z
High-Z
Write to Byte 2 Only
X
H
L
H
L
H
H
H
L
DIN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
H
L
H
H
H
L
L
L
High-Z
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
X
H
L
H
L
L
H
H
L
DIN
DIN
High-Z
High-Z
Write to Upper 2 bytes Only
X
H
L
H
L
L
L
L
L
DIN
DIN
DIN
DIN
L
H
L
H
H
H
H
L
H
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
H
L
H
H
H
L
H
H
High-Z
High-Z
DOUT
High-Z
Read Byte 1 Only
L
H
L
H
H
L
H
H
H
High-Z
DOUT
High-Z
High-Z
Read Byte 2 Only
L
H
L
H
L
H
H
H
H
DOUT
High-Z
High-Z
High-Z
Read Byte 3 Only
L
H
L
H
H
H
L
L
H
High-Z
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
H
L
H
L
L
H
H
H
DOUT
DOUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
H
L
H
L
L
L
L
H
DOUT
DOUT
DOUT
DOUT
H
H
L
H
L
L
L
L
X
High-Z
High-Z
High-Z
High-Z
Write to All Bytes
Read All Bytes
Outputs Disabled
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
4869 tbl 02
Truth Table II – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE(2)
R/W
OE
BE3
BE2
BE1
BE0
SEM
I/O1-35
I/O0
H
H
L
L
L
L
L
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag(3)
H
↑
X
X
X
X
L
L
X
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
X
X
X
X
L
______
______
Mode
Not Allowed
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A 0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH.
3. Each byte is controlled by the respective BEn. To read data BEn = VIL.
7
4869 tbl 03
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Recommended DC Operating
Conditions with VDDQ at 3.3V
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Industrial and Commercial Temperature Ranges
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.15
3.3
3.45
V
V DD
Core Supply Voltage
3.15
VDDQ
I/O Supply Voltage (3)
2.4
2.5
2.6
V
VDDQ
I/O Supply Voltage (3)
3.15
VSS
Ground
0
0
0
0
(3)
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.3
3.45
V
3.3
3.45
V
0
0
V
V
V SS
Ground
(2)
V
VIH
Input High Voltage
(Address & Control Inputs)(3)
2.0
____
VDDQ + 150mV(2)
V
VIH
Input High Voltage - I/O(3)
2.0
____
VDDQ + 150mV(2)
V
____
0.8
VIH
Input High Voltage
(Address & Control Inputs)
1.7
____
VDDQ + 100mV
VIH
Input High Voltage - I/O(3)
1.7
____
VDDQ + 100mV(2)
V
VIL
Input Low Voltage
-0.5(1)
____
0.7
V
Input Low Voltage
VIL
4869 tbl 06
-0.3
(1)
V
4869 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 100mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS (0V), and V DDQX for that port must be
supplied as indicated above.
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (3.3V), and VDDQX for that port must be
supplied as indicated above.
Capacitance(1)
Maximum Operating
Temperature and Supply Voltage(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
CIN
COUT(2)
Parameter
Input Capacitance
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
8
pF
VOUT = 0V
10.5
pF
Grade
Commercial
Industrial
4869 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
Ambient
Temperature
GND
VDD
0 C to +70 C
0V
3.3V + 150mV
-40 C to +85 C
0V
3.3V + 150mV
O
O
O
O
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
4869 tbl 04
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
(VDD)
VDD Terminal Voltage
with Respect to GND
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
-0.5 to + 4.6
V
IOUT(For VDDQ = 3.3V) DC Output Current
50
mA
IOUT(For VDDQ = 2.5V) DC Output Current
40
mA
4869 tbl 05
8
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time
or 4ns maximum, and is limited to < 20mA for the period of V TERM > VDD
+ 150mV.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V659/58/57S
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDDQ = Max., VIN = 0V to V DDQ
___
10
µA
|ILO |
Output Leakage Current
10
µA
CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ
___
VOL (3.3V)
Output Low Voltage
(2)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
Output High Voltage (2)
IOH = -4mA, VDDQ = Min.
2.4
___
V
VOL (2.5V)
Output Low Voltage (2)
IOL = +2mA, VDDQ = Min.
___
0.4
V
VOH (2.5V)
(2)
IOH = -2mA, VDDQ = Min.
2.0
___
Output High Voltage
V
4869 tbl 09
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V659/58/57S10 70V659/58/57S12 70V659/58/57S15
Com'l Only
Com'l
Com'l
& Ind
& Ind
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled
f = fMAX(1)
COM'L
S
340
500
315
465
300
440
IND
S
____
____
365
515
350
490
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
115
165
90
125
75
100
IND
S
____
____
115
150
100
125
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
225
340
200
325
175
315
IND
S
____
____
225
365
200
350
COM'L
S
3
15
3
15
3
15
IND
S
____
____
6
15
6
15
S
220
335
195
320
170
310
S
____
____
220
360
195
345
Full Standby Current Both Ports CEL and
(Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V
Level Inputs)
or VIN < 0.2V, f = 0(2)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) COM'L
VIN > VDD - 0.2V or VIN < 0.2V, Active
IND
Port, Outputs Disabled, f = fMAX(1)
mA
mA
mA
mA
4869 tbl 10
NOTES:
1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, T A = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CE X = VIL means CE0X = VIL and CE1X = VIH
CE X = VIH means CE0X = VIH or CE1X = V IL
CE X < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CE X > VCC - 0.2V means CE0X > VCC - 0.2V or CE 1X - 0.2V
"X" represents "L" for left port or "R" for right port.
9
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
2.5V
GND to 3.0V / GND to 2.5V
Input Pulse Levels
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
833Ω
DATAOUT
Figures 1 and 2
Output Load
5pF*
770Ω
4869 tbl 11
,
3.3V
590Ω
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
,
DATAOUT
435Ω
5pF*
4869 drw 03
Figure 1. AC Output Test load.
4869 drw 04
Figure 2. Output Test Load
(For tCKLZ , tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
∆tAA
(Typical, ns) 3
2
1
20.5
-1
30
50
80
100
200
Figure 3. Typical Output Derating (Lumped Capacitive Load).
Capacitance (pF)
4869 drw 05
10
,
,
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(5)
70V659/58/57S10
Com'l Only
Symbol
Parameter
Min.
Max.
70V659/58/57S12
Com'l
& Ind
Min.
Max.
70V659/58/57S15
Com'l
& Ind
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
10
____
12
____
15
____
ns
tAA
Address Access Time
____
10
____
12
____
15
ns
Chip Enable Access Time
(3)
____
10
____
12
____
15
ns
tABE
Byte Enable Access Time
(3)
____
5
____
6
____
7
ns
tAOE
Output Enable Access Time
____
5
____
6
____
7
ns
tOH
Output Hold from Address Change
ns
tACE
Output Low-Z Time
tLZ
3
____
3
____
3
____
(1,2)
0
____
0
____
0
____
ns
(1,2)
0
4
0
6
0
8
ns
0
____
0
____
0
____
ns
tHZ
Output High-Z Time
tPU
Chip Enable to Power Up Time (2)
tPD
Chip Disable to Power Down Time (2)
____
10
____
10
____
15
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
____
4
____
6
____
8
ns
tSAA
Semaphore Address Access Time
3
10
3
12
3
20
ns
4869 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V659/58/57S10
Com'l Only
Symbol
Parameter
70V659/58/57S12
Com'l
& Ind
70V659/58/57S15
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
10
____
12
____
15
____
ns
tEW
Chip Enable to End-of-Write
(3)
8
____
10
____
12
____
ns
tAW
Address Valid to End-of-Write
8
____
10
____
12
____
ns
0
____
0
____
0
____
ns
ns
WRITE CYCLE
tWC
Write Cycle Time
(3)
tAS
Address Set-up Time
tWP
Write Pulse Width
8
____
10
____
12
____
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
6
____
8
____
10
____
ns
tDH
tWZ
tOW
tSWRD
tSPS
Data Hold Time
(4)
0
____
0
____
0
____
ns
(1,2)
____
4
____
4
____
4
ns
(1,2,4)
0
____
0
____
0
____
ns
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
SEM Flag Contention Window
5
____
5
____
5
____
ns
Write Enable to Output in High-Z
Output Active from End-of-Write
4869 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
11
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
(6)
CE
tAOE
(4)
OE
tABE (4)
BEn
R/W
tLZ
tOH
(1)
DATAOUT
VALID DATA
(4)
tHZ
(2)
BUSYOUT
tBDD
(3,4)
4869 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE, CE or BEn.
2. Timing depends on which signal is de-asserted first CE, OE or BEn.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD .
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
ISB
.
4869 drw 07
12
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
(9)
(9)
BEn
tAS (6)
tWP
(2)
tWR
(3)
R/W
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
4869 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tWR(3)
tEW (2)
(9)
BEn
R/W
tDW
tDH
DATAIN
4869 drw 09
NOTES:
1. R/W or CE or BEn = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
13
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM/BEn(1)
tOH
tSOP
tDW
I/O
DATA OUT(2)
VALID
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
4869 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
4869 drw 11
NOTES:
1. DOR = D OL = VIL, CEL = CE R = VIH. Refer to Truth Table II for appropriate BE controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
14
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V659/58/57S10
Com'l Only
Symbol
Parameter
70V659/58/57S12
Com'l
& Ind
70V659/58/57S15
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
10
____
12
____
15
ns
tBDA
BUSY Disable Time from Address Not Matched
____
10
____
12
____
15
ns
tBAC
BUSY Access Time from Chip Enable Low
____
10
____
12
____
15
ns
tBDC
BUSY Disable Time from Chip Enable High
____
10
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
5
____
ns
____
10
____
12
____
15
ns
8
____
10
____
12
____
ns
tBDD
tWH
(3)
BUSY Disable to Valid Data
Write Hold After BUSY
(5)
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
8
____
10
____
12
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
22
____
25
____
30
ns
tDDD
Write Data Valid to Read Data Delay (1)
____
20
____
22
____
25
ns
4869 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
15
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
4869 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
16
.
4869 drw 12
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
tBDC
BUSY"B"
4869 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
tAPS (2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
4869 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
Parameter
70V659/58/57S10
Com'l Only
70V659/58/57S12
Com'l
& Ind
70V659/58/57S15
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
10
____
12
____
15
ns
tINR
Interrupt Reset Time
____
10
____
12
____
15
ns
4869 tbl 15
17
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS
ADDR"A"
(2)
tWR (4)
tAS(3)
CE"A"
R/W"A"
tINS
(3)
INT"B"
4869 drw 16
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
tAS
(2)
(3)
CE"B"
OE"B"
tINR (3)
INT"B"
4869 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL
L
L
X
X
X
X
X
X
L
X
X
L
Right Port
A16L-A0L
(5,6)
1FFFF
INTL
R/WR
CER
OER
A16R-A0R(5,6)
INTR
X
X
X
X
X
L(2)
(3)
Function
Set Right INTR Flag
X
X
X
L
L
1FFFF
H
X
(3)
L
L
X
1FFFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
1FFFE
L
H
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A16x is a NC for IDT70V658, therefore Interrupt Addresses are FFFF and FFFE.
6. A16x and A15 x are NC's for IDT70V657, therefore Interrupt Addresses are 7FFF and 7FFE.
18
Reset Right INTR Flag
4869 tbl 16
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV —
Address BUSY Arbitration
Inputs
Outputs
CEL
CER
AOL-A16L(4)
AOR-A16R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
4869 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V659/58/57 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A16X is a NC for IDT70V658, therefore Address comparison will be for A0 - A 15. Also, A16X and A15X are NC's for IDT70V657, therefore Address comparison will
be for A0 - A 14.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D35 Left
D0 - D35 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V659/58/57.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35 ). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Interrupts
Functional Description
The IDT70V659/58/57 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT70V659/58/57 has an automatic power
down feature controlled by CE. The CE0 and CE1 control the on-chip
power down circuitry that permits the respective port to go into a standby
mode when not selected (CE = HIGH). When a port is enabled, access
to the entire memory array is permitted.
19
4869 tbl 18
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 1FFFE
(HEX) (FFFE for IDT70V658 and 7FFE for IDT70V657), where a write
is defined as CER = R/WR = VIL per the Truth Table III. The left port clears
the interrupt through access of address location 1FFFE (FFFE for
IDT70V658 and 7FFE for IDT70V657) when CEL = OEL = VIL, R/W is
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when
the left port writes to memory location 1FFFF (HEX) (FFFF for IDT70V658
and 7FFF for IDT70V657) and to clear the interrupt flag (INTR), the right
port must read the memory location 1FFFF (FFFF for IDT70V658 and
7FFF for IDT70V657). The message (36 bits) at 1FFFE (FFFE for
IDT70V658 and 7FFE for IDT70V657)or 1FFFF (FFFF for IDT70V658
and 7FFF for IDT70V657) is user-defined since it is an addressable
SRAM location. If the interrupt function is not used, address locations
1FFFE (FFFE for IDT70V658 and 7FFE for IDT70V657) and 1FFFF
(FFFF for IDT70V658 and 7FFF for IDT70V657) are not used as mail
boxes, but as part of the random access memory. Refer to Truth Table III
for the interrupt operation.
number of slaves to be addressed in the same address range as the master
use the BUSY signal as a write inhibit signal. Thus on the IDT70V659/58/
57 RAM the BUSY pin is an output if the part is used as a master (M/S pin
= VIH), and the BUSY pin is an input if the part used as a slave (M/S pin
= VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part of
a word and inhibit the write operations from the other port for the other part
of the word.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing
can result in a glitched internal write inhibit signal and corrupted data in the
slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V659/58/57 RAM in master mode,
are push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Semaphores
A17(1,2)
CE0
MASTER
Dual Port RAM
BUSYL
BUSYR
CE0
SLAVE
Dual Port RAM
BUSYL
BUSYR
CE1
MASTER
Dual Port RAM
CE1
SLAVE
Dual Port RAM
BUSYL
BUSYL
BUSYR
BUSYR
4869 drw 18
Industrial and Commercial Temperature Ranges
.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V659/58/57 RAMs.
NOTES:
1. A16 for IDT70V658.
2. A15 for IDT70V657.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V659/58/57 RAM array in width while
using BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
20
The IDT70V659/58/57 is an extremely fast Dual-Port 128/64/32K x
36 CMOS Static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example,
the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, with both ports being
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from
or written to at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected.
Systems which can best use the IDT70V659/58/57 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V659/58/
57s hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V659/58/57 does not use its semaphore
flags to control any resources through hardware, thus allowing the system
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use assignment
method called “Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that a shared resource is
in use. If the left processor wants to use this resource, it requests the token
by setting the latch. This processor then verifies its success in setting the
latch by reading it. If it was successful, it proceeds to assume control over
the shared resource. If it was not successful in setting the latch, it determines
that the right side processorhas set the latch first, has the token and is using
the shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70V659/58/57 in a
separate memory space from the Dual-Port RAM. This address space is
accessed by placing a low input on the SEM pin (which acts as a chip select
for the semaphore flags) and using the other control pins (Address, CE,
R/W and BEo) as they would be used in accessing a standard Static RAM.
Each of the flags has a unique address which can be accessed by either
side through address pins A0 – A2. When accessing the semaphores, none
of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM, BEn) and output enable
(OE) signals go active. This serves to disallow the semaphore from
changing state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a semaphore in a test
loop must cause either signal (SEM or OE) to go inactive or the output will
never change. However, during reads BEn functions only as an output
for semaphore. It does not have any influence on the semaphore control
logic.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
21
Industrial and Commercial Temperature Ranges
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
V). As an example, assume a processor writes a zero to the left port at a
free semaphore location. On used instead, system contention problems
could have occurred during the gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
D
WRITE
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
Figure 4. IDT70V659/58/57 Semaphore Logic
4869 drw 19
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
x
4869 drw 20
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
(1)
3
ns
tJF
JTAG Clock Fall Time
____
3(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
4869 tbl 19
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
22
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x0
IDT Device ID (27:12)
0x303(1)
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number
Defines IDT part number
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
4869 tbl 20
NOTE:
1. Device ID for IDT70V658 is 0x30B. Device ID for IDT70V657 is 0x323.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
4869 tbl 21
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan registe r (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) be tween TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
SAMPLE/PRELOAD
0001
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
23
4869 tbl 22
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
DR
BC
208-ball fpBGA (BF-208)
208-pin PQFP (DR-208)
256-ball BGA (BC-256)
10
12
15
Commercial Only
Commercial & Industrial
Commercial & Industrial
S
Standard Power
70V659
70V658
70V657
4Mbit (128K x 36) 3.3V Asynchronous Dual-Port RAM
2Mbit (64K x 36) 3.3V Asynchronous Dual-Port RAM
1Mbit (32K x 36) 3.3V Asynchronous Dual-Port RAM
.
Speed in nanoseconds
4869 drw 21
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
Datasheet Document History:
6/2/00:
8/11/00:
6/20/01:
12/17/01:
03/19/04:
Initial Public Offering
Page 6, 13 & 20 Inserted additional BEn information
Page 14 Increased BUSY TIMING parameters tBDA, tBAC, tBDC and tBDD for all speeds
Page 21 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns
Page 2, 3 & 4 Added date revision for pin configurations
Page 8, 10, 14 & 16 Removed I-temp 15ns speed from DC & AC Electrical Characteristics
Page 23 Removed I-temp 15ns speed from ordering information
Added I-temp footnote
Page 1 & 23 Replaced TM logo with ® logo
Consolidated multiple devices into one data sheet
Removed "Preliminary" Status
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fax: 408-492-8674
www.idt.com
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24
for Tech Support:
831-754-4613
[email protected]
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